LAMPIRAN VHDL

Praktikan: Nama Lengkap Praktikan (Nomor Induk Mahasiswa)

Asisten: Nama Lengkap Asisten
Waktu Percobaan: Tanggal Pelaksanaan Praktikum
Kode-Nama Matakuliah
Laboratorium Dasar Teknik Elektro
Sekolah Teknik Elektro dan Informatika – ITB

1. Kondisi Rem LED5 <= '0';

LIBRARY ieee; LED6 <= '0';

USE ieee.std_logic_1164.all; LED7 <= '0';

entity brake is LED8 <= '0';

port (brake : IN std_logic; end case;

LED1, LED2, LED3, LED4, end process;

LED5, LED6, LED7, LED8 : OUT std_logic);
end cond;
end entity;
2. Kondisi Malam
architecture cond of brake is
LIBRARY ieee;
TYPE states is (srem, srem_idle);
USE ieee.std_logic_1164.all;
SIGNAL state : states;

begin
entity nightlamp is
state_rem:
port ( malam : IN std_logic;
state <= srem when brake = '1' else srem_idle;
LED1, LED2, LED3, LED4,
lampu : LED5, LED6, LED7, LED8 : OUT std_logic);

process (state) begin end entity;

case state is architecture cond of nightlamp is

when srem => TYPE states is (smalam, smalam_idle);

LED1 <= '1'; SIGNAL state : states;

LED2 <= '1'; begin

LED3 <= '1'; state_malam:

LED4 <= '1'; state <= smalam when malam = '1' else smalam_idle;

LED5 <= '1'; lampu :

1

LED6 <= '1'; process (state) begin

Halaman

LED7 <= '1'; case state is

LED8 <= '1'; when smalam =>

when srem_idle => LED1 <= '1';

LED1 <= '0'; LED2 <= '1';

LED2 <= '0'; LED3 <= '0';

LED3 <= '0'; LED4 <= '0';

LED4 <= '0'; LED5 <= '0';

 LED6 <= '0'; LED3 <= clock;

LED7 <= '1'; LED4 <= clock;

LED8 <= '1'; LED5 <= '0';

when smalam_idle => LED6 <= '0';

LED1 <= '0'; LED7 <= '0';

LED2 <= '0'; LED8 <= '0';

LED3 <= '0'; when skiri_idle =>

LED4 <= '0'; LED1 <= '0';

LED5 <= '0'; LED2 <= '0';

LED6 <= '0'; LED3 <= '0';

LED7 <= '0'; LED4 <= '0';

LED8 <= '0'; LED5 <= '0';

end case; LED6 <= '0';

end process; LED7 <= '0';

end cond; LED8 <= '0';

3. Kondisi Kiri end case;

end process;
a. Satu kondisi aktif
end cond;
LIBRARY ieee;

USE ieee.std_logic_1164.all; b. Dua kondisi aktif

entity left is LIBRARY ieee;

port ( kiri, clock : IN std_logic; USE ieee.std_logic_1164.all;

LED1, LED2, LED3, LED4, entity left_rem is

LED5, LED6, LED7, LED8 : OUT std_logic);
port ( kiri, clock : IN std_logic;
end entity;
LED1, LED2, LED3, LED4,
architecture cond of left is LED5, LED6, LED7, LED8 : OUT std_logic);

TYPE states is (skiri, skiri_idle); end entity;

SIGNAL state : states; architecture cond of left_rem is

begin TYPE states is (skiri1, skiri2, skiri3, skiri4, skiri_rem_idle);

2

state_kiri: SIGNAL state : states;

Halaman

state <= skiri when kiri = '1' else skiri_idle; begin

lampu : state_kiri_rem:

process (state) begin process (clock)

case state is variable count: integer:=0;

when skiri => constant div: integer:=3;

LED1 <= clock; begin

LED2 <= clock;

 if (count = 0 and kiri = '1') then state <= when skiri2 =>
skiri1;
LED1 <= '0';
elsif (count = 1 and kiri = '1') then
state <= skiri2; LED2 <= '0';

elsif (count = 2 and kiri = '1') then LED3 <= '1';

state <= skiri3;
LED4 <= '0';
elsif (count = 3 and kiri = '1') then
state <= skiri4;
LED5 <= '1';
elsif (kiri = '0') then state <=
skiri_rem_idle; end if; LED6 <= '1';

if (clock'event and clock = '1') then LED7 <= '1';

count := count + 1; LED8 <= '1';

if (count = 4) then when skiri3 =>

count:=0; LED1 <= '0';

end if; LED2 <= '1';

end if; LED3 <= '0';

end process; LED4 <= '0';

lampu : LED5 <= '1';

process (state) begin LED6 <= '1';

case state is LED7 <= '1';

when skiri_rem_idle => LED8 <= '1';

LED1 <= '0'; when skiri4 =>

LED2 <= '0'; LED1 <= '1';

LED3 <= '0'; LED2 <= '0';

LED4 <= '0'; LED3 <= '0';

LED5 <= '1'; LED4 <= '0';

LED6 <= '1'; LED5 <= '1';

LED7 <= '1'; LED6 <= '1';

LED8 <= '1'; LED7 <= '1';

when skiri1 => LED8 <= '1';

LED1 <= '0';

3

end case;
Halaman

LED2 <= '0';

LED3 <= '0'; end process;

LED4 <= '1'; end cond;

LED5 <= '1'; 4. Kondisi Kanan

LED6 <= '1'; a. Satu kondisi aktif

LED7 <= '1'; LIBRARY ieee;

LED8 <= '1'; USE ieee.std_logic_1164.all;

entity right is LIBRARY ieee;

port ( kanan, clock : IN std_logic; USE ieee.std_logic_1164.all;

LED1, LED2, LED3, LED4, entity right_rem is

LED5, LED6, LED7, LED8 : OUT std_logic);
port ( kanan, clock : IN std_logic;
end entity;
LED1, LED2, LED3, LED4,
architecture cond of right is LED5, LED6, LED7, LED8 : OUT std_logic);

TYPE states is (skanan, skanan_idle); end entity;

SIGNAL state : states; architecture cond of right_rem is

begin TYPE states is (skanan1, skanan2, skanan3, skanan4,

skanan_rem_idle);
state_kanan:
SIGNAL state : states;
state <= skanan when kanan = '1' else skanan_idle;
begin
lampu :
state_kanan_rem:
process (state) begin
process (clock)
case state is
variable count: integer:=0;
when skanan =>
constant div: integer:=3;
LED1 <= '0';
begin
LED2 <= '0';
if (count = 0 and kanan = '1') then state <=
LED3 <= '0'; skanan1;

LED4 <= '0'; elsif (count = 1 and kanan = '1')

then state <= skanan2;
LED5 <= clock;
elsif (count = 2 and kanan = '1')
then state <= skanan3;
LED6 <= clock;
elsif (count = 3 and kanan = '1')
LED7 <= clock; then state <= skanan4;

LED8 <= clock; elsif (kanan = '0') then state <=

skanan_rem_idle; end if;
when skanan_idle =>
if (clock'event and clock = '1') then
LED1 <= '0';
count := count + 1;
LED2 <= '0';
if (count = 4) then
LED3 <= '0';
count:=0;
LED4 <= '0';
end if;
4

LED5 <= '0';

end if;
Halaman

LED6 <= '0';

end process;
LED7 <= '0';
lampu :
LED8 <= '0';
process (state) begin
end case;
case state is
end process;
when skanan_rem_idle =>
end cond;
LED1 <= '1';
b. Dua kondisi aktif
 LED2 <= '1'; LED1 <= '1';

LED3 <= '1'; LED2 <= '1';

LED4 <= '1'; LED3 <= '1';

LED5 <= '0'; LED4 <= '1';

LED6 <= '0'; LED5 <= '0';

LED7 <= '0'; LED6 <= '0';

LED8 <= '0'; LED7 <= '0';

when skanan1 => LED8 <= '1';

LED1 <= '1'; end case;

LED2 <= '1'; end process;

LED3 <= '1'; end cond;

LED4 <= '1'; 5. Kondisi Darurat

LED5 <= '1'; LIBRARY ieee;

LED6 <= '0'; USE ieee.std_logic_1164.all;

LED7 <= '0'; entity darurat is

LED8 <= '0'; port ( darurat, clock : IN std_logic;

when skanan2 => LED1, LED2, LED3, LED4,

LED5, LED6, LED7, LED8 : OUT std_logic);
LED1 <= '1';
end entity;
LED2 <= '1';
architecture cond of darurat is
LED3 <= '1';
TYPE states is (sdarurat, sdarurat_idle);
LED4 <= '1';
SIGNAL state : states;
LED5 <= '0';

LED6 <= '1';

begin
LED7 <= '0';
state_darurat:
LED8 <= '0';
state <= sdarurat when darurat = '1' else sdarurat_idle;
when skanan3 =>
lampu :
LED1 <= '1';
process (state) begin
LED2 <= '1';
5

case state is
LED3 <= '1';
Halaman

when sdarurat =>

LED4 <= '1';
LED1 <= clock;
LED5 <= '0';
LED2 <= clock;
LED6 <= '0';
LED3 <= clock;
LED7 <= '1';
LED4 <= clock;
LED8 <= '0';
LED5 <= clock;
when skanan4 =>
LED6 <= clock;
 LED7 <= clock; end component;

LED8 <= clock; component right_rem is

when sdarurat_idle => port ( kanan, clock : IN std_logic;

LED1 <= '0'; LED1, LED2, LED3, LED4,

LED5, LED6, LED7, LED8 : OUT std_logic);
LED2 <= '0';
end component;
LED3 <= '0';

LED4 <= '0';

component left is
LED5 <= '0';
port ( kiri, clock : IN std_logic;
LED6 <= '0';
LED1, LED2, LED3, LED4,
LED7 <= '0'; LED5, LED6, LED7, LED8 : OUT std_logic);

LED8 <= '0'; end component;

end case; component left_rem is

end process; port ( kiri, clock : IN std_logic;

end cond; LED1, LED2, LED3, LED4,

LED5, LED6, LED7, LED8 : OUT std_logic);

6. Program Utama end component;

LIBRARY ieee;
component darurat is

USE ieee.std_logic_1164.all;
port ( darurat, clock : IN std_logic;

entity rearlights is
LED1, LED2, LED3, LED4,
LED5, LED6, LED7, LED8 : OUT std_logic);
PORT( switch_darurat, switch_rem, switch_malam,
switch_kanan, switch_kiri, Clocks : IN STD_LOGIC;
end component;

out_1, out_2, out_3, out_4, out_5,

component CLOCKDIV is port(
out_6, out_7, out_8 : OUT STD_LOGIC);

CLK: IN std_logic;
end rearlights;

DIVOUT: OUT std_logic);

architecture structural of rearlights is

end component;
component brake is

signal Output1b, Output2b, Output3b, Output4b, Output5b,

port (brake : IN std_logic;
Output6b, Output7b, Output8b,

LED1, LED2, LED3, LED4,

Output1n, Output2n, Output3n, Output4n,
LED5, LED6, LED7, LED8 : OUT std_logic);
Output5n, Output6n, Output7n, Output8n,

end component;
Output1r, Output2r, Output3r, Output4r,
Output5r, Output6r, Output7r, Output8r,
6

component nightlamp is
Output1rr, Output2rr, Output3rr, Output4rr,
Halaman

port ( malam : IN std_logic; Output5rr, Output6rr, Output7rr, Output8rr,

LED1, LED2, LED3, LED4, Output1l, Output2l, Output3l, Output4l,

LED5, LED6, LED7, LED8 : OUT std_logic); Output5l, Output6l, Output7l, Output8l,

end component; Output1lr, Output2lr, Output3lr, Output4lr,

Output5lr, Output6lr, Output7lr, Output8lr,
component right is
Output1d, Output2d, Output3d, Output4d,
port ( kanan, clock : IN std_logic; Output5d, Output6d, Output7d, Output8d, clockin, clockout :
std_logic;
LED1, LED2, LED3, LED4,
LED5, LED6, LED7, LED8 : OUT std_logic); begin
state1: brake port map (switch_rem, Output1b, Output2b, Output3b, out_1 <= Output1r or Output1n;
Output4b, Output5b, Output6b, Output7b, Output8b );
out_2 <= Output2r or Output2n;
state2: nightlamp port map ( switch_malam, Output1n, Output2n,
Output3n, Output4n, Output5n, Output6n, Output7n, Output8n); out_3 <= Output3r;

out_4 <= Output4r;

state3: right port map (switch_kanan, clockin, Output1r, Output2r, out_5 <= Output5r;
Output3r, Output4r, Output5r, Output6r, Output7r, Output8r);
out_6 <= Output6r;

out_7 <= Output7r;

state4: right_rem PORT map (switch_kanan, clockin, Output1rr,
Output2rr, Output3rr, Output4rr, Output5rr, Output6rr, Output7rr,
Output8rr); out_8 <= Output8r;

state5: left PORT map (switch_kiri, clockin, Output1l, Output2l, elsif (switch_kanan = '0' and switch_darurat = '0' and switch_rem =
Output3l, Output4l, Output5l, Output6l, Output7l, Output8l); '0' and (switch_malam = '1' or switch_kiri = '1')) then

state6: left_rem PORT map (switch_kiri, clockin, Output1lr, out_1 <= Output1l;
Output2lr, Output3lr, Output4lr, Output5lr, Output6lr, Output7lr,
Output8lr); out_2 <= Output2l;

state7: darurat PORT map (switch_darurat, clockin, Output1d, out_3 <= Output3l;
Output2d, Output3d, Output4d, Output5d, Output6d, Output7d,
Output8d); out_4 <= Output4l;

state8: CLOCKDIV PORT map (Clocks, clockin); out_5 <= Output5l;

process (switch_darurat, switch_rem, switch_malam, switch_kanan, out_6 <= Output6l;

switch_kiri) begin
out_7 <= Output7l or Output7n;
if (switch_darurat = '1') then
out_8 <= Output8l or Output8n;
out_1 <= Output1d;
elsif (switch_kanan = '1' and switch_darurat = '0' and switch_rem =
out_2 <= Output2d; '1' and switch_malam = '0' and switch_kiri = '0') then

out_3 <= Output3d; out_1 <= Output1rr;

out_4 <= Output4d; out_2 <= Output2rr;

out_5 <= Output5d; out_3 <= Output3rr;

out_6 <= Output6d; out_4 <= Output4rr;

out_7 <= Output7d; out_5 <= Output5rr;

out_8 <= Output8d; out_6 <= Output6rr;

elsif ((switch_rem = '1' or switch_malam = '1') and switch_kanan = out_7 <= Output7rr;
'0' and switch_darurat = '0' and switch_kiri = '0') then
out_8 <= Output8rr;
out_1 <= Output1b or Output1n;
elsif (switch_kanan = '0' and switch_darurat = '0' and switch_rem =
out_2 <= Output2b or Output2n; '1' and switch_malam = '0' and switch_kiri = '1') then
7
Halaman

out_3 <= Output3b or Output3n; out_1 <= Output1lr;

out_4 <= Output4b or Output4n; out_2 <= Output2lr;

out_5 <= Output5b or Output5n; out_3 <= Output3lr;

out_6 <= Output6b or Output6n; out_4 <= Output4lr;

out_7 <= Output7b or Output7n; out_5 <= Output5lr;

out_8 <= Output8b or Output8n; out_6 <= Output6lr;

elsif ((switch_kanan = '1' or switch_malam = '1') and switch_darurat out_7 <= Output7lr;
= '0' and switch_rem = '0' and switch_kiri = '0') then
out_8 <= Output8lr; out_6 <= '0';

elsif (switch_kanan = '1' and switch_darurat = '0' and switch_rem = out_7 <= '0';
'1' and switch_malam = '1' and switch_kiri = '0') then
out_8 <= '0';
out_1 <= Output1rr;
end if;
out_2 <= Output2rr;
end process;
out_3 <= Output3rr;
end structural;
out_4 <= Output4rr;

out_5 <= not Output5rr;

out_6 <= not Output6rr;

out_7 <= not Output7rr;

out_8 <= not Output8rr;

elsif (switch_kanan = '0' and switch_darurat = '0' and switch_rem =

'1' and switch_malam = '1' and switch_kiri = '1') then

out_1 <= not Output1lr;

out_2 <= not Output2lr;

out_3 <= not Output3lr;

out_4 <= not Output4lr;

out_5 <= Output5lr;

out_6 <= Output6lr;

out_7 <= Output7lr;

out_8 <= Output8lr;

elsif (switch_kanan = '1' and switch_darurat = '0' and switch_rem =

'1' and switch_malam = '1' and switch_kiri = '1') then

out_1 <= not Output1lr;

out_2 <= not Output2lr;

out_3 <= not Output3lr;

out_4 <= not Output4lr;

out_5 <= not Output5rr;

out_6 <= not Output6rr;

out_7 <= not Output7rr;

8
Halaman

out_8 <= not Output8rr;

else

out_1 <= '0';

out_2 <= '0';

out_3 <= '0';

out_4 <= '0';

out_5 <= '0';