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A Novel Design Evaluation of Low-Voltage RF front-end with VCO in 0.18-m CMOS

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M.SUMATHI1 Research Scholar, Department of Electronics & Communication Engineering, Sathyabama University, Chennai-119, India S.MALARVIZHI2 Professor/ Head of the Department, Electronics & Communication Engineering, SRM University, Kattankulathur, India

Abstract A low-voltage direct-conversion receiver front-end for 2.4GHz radio applications is presented. It consists of a low-noise amplifier (LNA), a down-conversion mixer and a voltage-controlled oscillator (VCO). The proposed LNA uses modified cascode structure in differential topology and mixer utilizes folded switching technique for supply voltage reduction. The VCO uses novel cross coupling topology with high Q inductor. The design theory and performance evaluation done i n TSMC 0.18-m CMOS technology scale. The RF front-end achieves a voltage conversion gain of 13 dB and a noise figure of 7.9 dB. The designed 3.5GHz VCO has a phase noise of -95.19 dBc/Hz at 1MHz offset. Index Terms Direct Conversion, LNA, Mixer, Radio Frequency (RF), Voltage Controlled Oscillator.

1 INTRODUCTION
Recently, RF CMOS have become more popular and dominant technology for realization of analog receiver integrated circuits. Wireless applications in 2.4GHz frequency range are receiving more attention due to their potential for low cost and system on chip integration [1]. The selection of receiver architecture based on high performance and less number of off-chip components. Many research papers conveyed that Superheterodyne architecture can provide sufficiently low noise figure but more external filter circuitry required which also increases receiver size and power dissipation. Some reported direct conversion receivers utilized operational amplifiers in RF section which require high supply voltage of 2.5V and complicates the supply power management of RFIC.The most important aspect of adopting new technology scale in RF analog design is the reduction of the supply voltage.Existing circuit topologiesof LNA, Mixer and oscillator could not satisfy the required specifications under low operating voltage. Also by increasing the operating frequency above 1GHz, the front-end circuits require more power to achieve ahigh gain and low noise performance inspite of the reduced noise ratio of operation frequency to small unity gain frequency of MOSFET. Therefore, by considering all these problems, the research towards the proposal of low voltage circuit topologies is important [4]. The block diagram of the direct conversion RF front-end designed in this paper is illustrated in Fig.1.It consists of RF amplifier (LNA), Mixer and Local Oscillator. The operation of front-end is, the incoming RF signal downconverted into IF signal. It is the difference between the RF and LO signals frequencies. The following are the design constraints considered such as optimized impedance matching of front-end blocks, moderate conversion gain and low noise figure (NF). The existing topologies are revised and modified structures proposed for three circuit designs. The work is organized as follows. The design theory of the front-end and VCO are described in Section II. The performance analysis of these blocks using ADS software discussed in Section III. Finally, Conclusion is presented in Section IV.

Figure.1. Block diagram of Receiver front-end

2 DESIGN OF THE FRONT-END

The front-end circuit designs are evaluated from 1.8V power supply. All designs utilize the balanced topology which has the advantage of rejecting unwanted noise and other interferences from substrate and supply.

2.1 Low Noise Amplifier Cascode structure is the one, commonly used in LNA. It is composed of common source and common gate (CS-CG) stages. Recently reported designs [3] based on inductively degenerated Cascode LNAs which does not satisfy all the

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objectives. These are optimum gain, lowest NF, better impedance matching and high linearity. In order to satisfy all objectives, a modified cascode structure proposed in differential LNA configuration. The simplified structure is shown in Fig.2.Two nMOS transistors M1, M2 are connected in parallel for each CS stage. Therefore, the gatesource capacitances and device currents are paralleled in the equivalent circuit model, shown in Fig.4. Fig.3. shows a schematic of CMOS Differential LNA. It is constructed by using two single-stage cascode LNAs. Each stage composed of input, output matching block, amplification block and output stage. A cascade output buffer is also added with LNA for betterment of gain, noise figure and reverse isolation.

Figure.4.Equivalent circuit for input stage of LNA

From the equivalent circuit, the total current flowing through CS stage is represented by assuming that the transistors are operated in saturation region and it is shown in eqn.(1).

It =

k [W1 (V gs 1 Vt ) 2 + W2 (V gs 2 Vt ) 2 ] L

(1)

where W 1 & W 2 are the gate widths of M1, M2 and V gs1 , V gs2 , V t are the gate-source voltages and threshold voltages of transistors. L is the channel length. Similarly, the input impedance at the dual transistors is calculated from this Eqn.(2) at resonance 0,

Z in

( g m1 + g m 2 ) Ls C gs1 + C gs 2

(2)

Figure.2. Single CS stage using two transistors

where g m , L s and C gs are the transconductances , source inductances and gate-source capacitances of dual transistors. The optimized width of the transistors and inductor values are evaluated from Cgs , L g and L s . These values were chosen to ensure impedance matching of 50 ohms and resonance at 2.4GHz.

2.2 Down-Conversion Mixer

Low voltage design has become an important issue in most digital, analog IC applications. Gilbert mixer is the commonly used double balanced mixer configuration. It comprises of RF transconductance stage, LO switching stage and output loads. In many reported mixer designs [6], better performance can be achieved by increasing the current through the transconductance stage and switching stage and therefore higher supply voltage will be required. The proposed mixer uses folded switching technique, which biasing the RF and LO stages separately by resistive loads and inter-stage inductor L. Therefore, only current through the RF stage increased, but allows smaller drive voltage for LO stage and improves the entire performance. Fig.5 represents the proposed front-end schematic.

Figure.3.Proposed CMOS Differential LNA

It comprises an input stage formed by inductors L g and L s , two inter-stage inductors (L is ), four CS transistors(M1-M4), two CG transistors(M5-M6), two drain inductors L D and cascaded output stage transistor M7.

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proposed active part of circuitry compensates the losses in LC tank and provides stable oscillation. The W/L ratio of active devices calculated from this design Eqn.4. The proper values of g m and inductor L decide the entire performance of the VCO.

gm W = L 2( K n I D )
Figure.5.Proposed Front-end

(4)

The double balanced down-conversion mixer comprises differential pair RF transconductance stage (M5-M6), four differential switching quads (M1-M4) and load resistors (R1, R2). R3 and R4 are the biasing resistors of the transconductance stage. Inductor L is placed between the RF and LO stages. L g and L s inductors used for the input impedance matching at 50 ohm. The optimum gate width of the transistors for better performance is evaluated by using this Eqn. 3, where L, C ox and R gen is the channel length, oxide capacitance and resistance of the source connected to the mixer typically 50 ohms.

where K n is the process dependent term and I D is the drain current. The expression for K n and C ox is given in eqn.(5)&(6).

K n = nCox Cox =

(5) (6)

o r
tox

The typical values of

o , r & tox are 3.97, 8.85*10-12F/m

and

4.1*10-9m respectively. For better oscillation, the minimum g m value should be > 9mS.

Wopt =

1 3LC ox R gen

(3)

3 Simulation Results
The simulation of the front-end and VCO are based on TSMC 0.18-m CMOS RF models. Agilents Advanced Design System (version 9.0) EDA tools used to evaluate the performances of these three circuitry designs. The proposed front-end operated at RF frequency of 2.4GHz, LO frequency of 2.25GHz and IF frequency of 150MHz. The input impedance matching and forward gain of LNA analysed by Sparameter test and shown in Fig.8 and Fig.7. The conversion gain and noise figure of the front-end are measured and shown in Fig.9 &10, while sweeping LO power at 5dBm.

2.3 Voltage Controlled Oscillator

Generally, the tuned circuit and amplifier circuit of oscillator decides the frequency of oscillation. The concept of VCO is that, frequency can be varied by control voltage. Cross coupling pair is the commonly used topology in VCO. Reported designs [5] concentrated only by providing changes of elements in tuned circuitry and analyzed the performance.

Figure.7 Forward gain of LNA Figure.6 .Proposed VCO

The basic difference between this proposed design and conventional design is that by providing four nMOS transistors in cross-coupling structure rather than by two for betterment of oscillation and phase noise. Fig.6. shows the proposed VCO.It consists of cross coupled pair of nMOS transistors [M1,2 M3,4] and two pMOS transistors [M5-M6] with tail current source. The high Q off-chip inductor is used as feedback element alongwith series connection of capacitors. The

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Figure.8 LNA impedance matching

Figure.12. Phase Noise of the VCO

Table I. Performance Comparison Frontend [6] [7] This work

Figure9. Conversion Gain of Front-end

Tech.(m) 0.18 0.35 0.18

Freq.(GHz) 2.4 2.4 2.4

CG(dB) 11 8.5 13

NF(dB) 14 10 7.9

The LNA input impedance matching and maximum voltage gain values at 2.4GHz RF frequency are -8.5dB, 28.75dB respectively. The peak conversion voltage gain is about 13dB and noise figure of 7.9 dB indicated by markers m1 and m2.

Table I. shows the performance comparison of front-end with recently published designs. The results are comparably better and suitable for low voltage applications.

4 CONCLUSION
A 1.8-V, 2.4GHz RF front-end with 3.5 GHz VCO for direct conversion receiver is presented in this paper. The design concept and performance analysis of LNA, Mixer and VCO are described. The simulated performance includes a voltage gain of 13dB, a noise figure of 9dB and phase noise of VCO 95.19dBc/1MHz offset. Further, the VCO performance can be analyzed with different control voltages. The topology and technology scale can also be revised for betterment of design performance. Further, the work can be extended for layout designs and GDS II files.

REFERENCES
Figure.10. Noise Figure of Front-end

Fig.11 shows the output signal of VCO at 3.5GHz. The phase noise plot at 1MHz offset is shown in Fig.12. The phase noise value is -95.19dBc/Hz.

[1]

[2] [3] [4] [5] [6] Figure.11. VCO output

Shinill chang, et al., Design of a 2.4GHz fully differential zeroIF CMOS receiver employing a novel Hybrid Balun for WSN, Journal of Semiconductor Technology and Science, vol.8,No.2, June 2008. Tae-Sung Kim, et al.., Post-Linearization of Differential CMOS LNA Using Cross-Coupled FETs, Journal of Semiconductor technology and Science, vol.8,No.4,December 2008. Trung-kien Nguyen, et al., CMOS Low-Noise Amplifier Design Optimization Techniques, IEEE Transactions on Microwave Theory and Techniques, vol.52, No.5, May 2004. Vidojkovic.V, et al., A low-voltage folded-switching mixer in 0.18m CMOS, IEEE Journal of solid-state circuits, vol.40, no.6,1259-1264, 2005. M.Rahimi, et al., Design and Simulation of a 2.4GHz VCO with High Q MEMS Inductor, International Journal of Computer and Electrical Engineering, vol.1,No.3,August 2009. Jenn-Tzer Yang, et al., A 2.4GHz Low Power Mixer for Direct Conversion Receivers, International Journal of Circuits,Systems and Signal processing,issue 2,vol.1,2007.

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[7]

Wan-Rone Liou,et al.,Design and Implementation of 2.4GHz CMOS Front-end for Wireless Communication, Journal of Marine Science and Technology,vol.13,No.3,pp.170-175, 2005.

[8] M.Arasu, et al., A 2.4GHz CMOS RF front-end for wireless sensor network applications,IEEE Radio Frequency Integrated Circuits Symposium, 2006. [9] A.Zolfaghari, B.Razavi, A low power 2.4GHz Transmitter /ReceiverIC,IEEE journal of solid state circuits, vol.38, no.2,pp.176- 183, 2003. [10] Mihai A.T .Sanduleanu, Maja Vidojkovic, Arthur, Receiver Front- End Circuits Communications, IEEE Transactions on Circuits and Systems II, vol.55, No.4, April 2008. [11] H.Darabi, J.Chiu, A Noise cancellation technique in active RF CMOS mixers, IEEE Journal of solid-state circuits, vol.40, no.12, pp.2628- 2632, 2005. [12] J.A.M.Jarvinen et al.,2.4GHz receiver for Sensor Applications, IEEE Journal of Solid State Circuits, vol.40, no.7, pp.1426-1433, July 2005. [13] Hsieh Wang, Lu.,Gain enhancement techniques for CMOS folded cascode LNAs at low-voltage operations IEEE Transactions on Microwave Theory and Techniques, vol.56, no.8, pp.1807-1816, 2008. [14] Baimei Liu,et al.,An Ultra-Low Voltage and Ultra-Low Power 2.4GHz LNA Design, Radio Engineering, vol.18, no.4, pp.527531, December 2009. [15] TSMC, Taiwan Semiconductor Manufacturing Co., TSMC 0.18-m Mixed Signal/RF 1p6M model file, Document No. TA-10A9-4001. [16] Gianluca Cornetta, et.al., A Direct Down-Conversion Receiver for low-power Wireless Sensor Networks, International Journal of Electrical and Computer Engineering,vol.4,no.16,pp.992-1001, 2009. [17] Taeksang Song, et.al., A low-power 2.4GHz Current Reused Receiver Front-end and Frequency source for Wireless Sensor NetworksIEEE Journal of solid-state circuits, vol.42, no.5, May 2007. Sumathi M. received the Undergraduate Degree in Electronics and Communication Engineering from Madras University, in 1992 and the Post Graduate degree in Applied Electronics from Anna University, Chennai in 2002. She is currently doing her research in Faculty of Electronics Engineering at Sathyabama University, Chennai-119. She has more than 20 publications in international/national journals and Conference proceedings. She has more than 16 years of teaching experience . Her areas of interest includes RF,Microwaves, Communication Systems, CMOS VLSI, Mixed Signal VLSI and Testing of VLSI circuits.