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Digital System Design Lab Lab Name Allotted PC Name Allotted PC IP Address Home Directory : : : : Class Work : 25 Exam

: 25 Total : 50 Duration of Exam: 3 hrs

INDEX
S No. Name of Experiment File Name Date of Experiment Date of Submission Faculty Signature Date Of Checking Marks

Design all the gates using VHDL Write VHDL program for the following circuits, check the wave forms and the hardware generated 1. HALF ADDER 2. FULL ADDER

Write VHDL program for the following circuits, check the wave forms and the hardware generated 1. Multiplexer
2.

Demultiplexer

Write VHDL program for the following circuits, check the wave forms and the hardware generated 1. ENCODER 2. DECODER Write VHDL program for a comparator and check the wave forms and the hardware generated

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