Biasing with Source Degeneration

1
?
?
1
=
=
V
V
GS
Example: I
D
and Maximum R
D
for Source Degeneration Biasing

2
0
18 . 0 / 5 /
/ 100
5 . 0
2
=
=
=
=

L W
V A C
V V
ox n
TH
Find V
1
, V
GS
, R
D
?
Example: Maximum W/L and Minimum R
S


3
0
5 . 2
/ 100
5 . 0
2
=
O =
=
=

K R
V A C
V V
D
ox n
TH
Find I
Dmax
, W/L
max
V
GS
R
smin ?
Example: Self-Biased MOS Stage
4
0
5 . 0
/ 100
2
=
=
=

V V
V A C
TH
ox n
Find I
D
, R
D
?
Example: PMOS Stage with Biasing
V V
K R
K R
L W
V A C
TH
ox p
5 . 0
15
20
0
18 . 0 5
/ 50
2
1
2
=
O =
O =
=
=
=

5
Find I
D
R
D
V
GS

Example: PMOS Stage with Self-Biasing
V V
L W
V A C
TH
ox p
5 . 0
0
18 . 0 5
/ 50
2
=
=
=
=

6
Find I
D
Example: CS Stage
7
0
5 . 0
/ 100
1
2
=
=
=
=

V V
V A C
mA I
TH
ox n
D
Saturation
I R V V V
V
D D DD TH GS
GS
>
= =
=
6 . 0 8 . 0
? ?,
?
Find gm, A
v
Example: Faulty CS Stage Design
8
0
18 . 0 5
/ 100
5 . 0
5
8 . 1
1
2
=
=
=
=
=
=
=

L W
V A C
V V
A
V V
mW Power
ox n
TH
v
DD
? ?
? ? ?
= =
= = =
D v
m D
R A
g I Power
However, no solution exists since M
1
is out of the saturation
region (V
DD
-I
D
R
D
<V
GS
-V
TH
).
Example: Degeneration Resistor
8
200 1
=
O =
v
m
A
g
4
200 1
=
O =
v
m
A
g
9
?
?
=
=
S
D
R
R
Without Degeneration With Degeneration
Example: NMOS Current Source Design
V V
V
V A C
K R
mA I
DS
ox n
out
D
3 . 0
25 . 0
/ 100
20
1
min
1
2
=
=
=
O =
=

10
?
?
min
=
= =
S
TH GS DS
R
V V V
Example: Source Degeneration with Bypass Capacitor Design
mV V
V V
V V
V A C
mW Power
K R
A
S
R
DD
TH
ox n
in
v
400
8 . 1
0
5 . 0
/ 100
5
50
5
2
=
=
=
=
=
=
O =
=

11
? ?,
?
?
?
?
2 1
= =
=
=
=
=
R R
R
L W
g
R
D
m
S
Example: Common-Gate Stage Design
V V
V V
V A C
L W
mA I
DD
TH
ox n
D
8 . 1
5 . 0
/ 100
50
5 . 0
2
=
=
=
=
=

12
06 . 6 447 1
71 . 2
s O =
O < >
v m
D TH b D D DD
A g
k R V V R I V
CG and CS Stages Output Impedance Comparison
13
( ) | |
S O S m D outCS outCG
R r R g R R R + + = = 1 ||
Since when calculating the output impedance, the input voltage
source of the CG stage is grounded, the result will be identical
to that of a CS stage if the same assumptions are made for both
circuits.
Example: A
V
and R
out
14
( )
S m m
D m
in
out
R g g
R g
v
v
2 1
1
1 + +
=
= 0
D O S
m
O m out
R r R
g
r g R || ||
1
1
2
1 1
(

+
|
|
.
|

\
|
~
> 0
Example: CG with Complete Bias Network

15
V V
mW Power
g
R R
A
V V
V A C
DD
m
S
v
TH
ox n
8 . 1
2
50 / 1
500 , 0
5
0
5 . 0
/ 100
1
2
=
=
O =
O = =
=
=
=
=

( )
? ?,
?
? / 2
?
?
2 1
= =
=
= =
=
=
G G
D
TH GS D m
GS
R R
R
V V I g
L W
V
Example: Min W/L

16
V V
mW Power
g
R R
A
V V
V A C
DD
m
S
v
TH
ox n
8 . 1
2
50 / 1
500 , 0
5
0
5 . 0
/ 100
1
2
=
=
O =
O = =
=
=
=
=

( )
2
1
1
1
2
2
2
2
|
|
.
|

\
|
+

>
+ >
+ >
v
R DD
ox n
D
R TH GS TH GS
v
DD
TH R GS D D DD
A
V V
C
I
L
W
V V V V V
A
V
V V V R I V