`define `define `define `define `define `define

S0 S1 S2 S3 3 S4 S5

0 1 2 4 5

module clock1 (clk,reset,clk_out); input clk,reset; output reg clk_out=0; integer x = 0; always@(posedge clk ) begin if ( reset == 1 ) x<=0; else begin x <= x+1; if(x == 2) begin x<=0; clk_out <= ~clk_out; end end end endmodule module clock2 (clk,reset,clk_out); input clk,reset; output reg clk_out=0; integer x = 0; always@(posedge clk ) begin if ( reset == 1 ) x<=0; else begin x <= x+1; if(x == 3) begin x<=0; clk_out <= ~clk_out; end end end endmodule module counter (cout, clk, rst, roll); input wire clk, rst, roll; output reg [2:0] cout=4'b001; always @ ( posedge clk ) begin

if ( rst == 1 ) cout = 1; else begin if ( roll ==1 ) begin cout = cout+ 1; if ( cout== 6 ) cout=1; end end end endmodule /*module adder (add1, add2, clk, rst,sum); input wire [3:0] add1, add2; input wire clk, rst; output reg [3:0] sum; always @ ( posedge clk or add1 or add2 ) begin if ( rst==1 ) sum = 0; else sum = add1 + add2; end endmodule*/ module dice_roller ( roll, reset, clk, sum); input wire roll, clk, reset; output reg [3:0] sum; reg [2:0] add1=0,add2=0; wire clk1,clk2; integer x=0,y=0; always @ ( posedge clk1 or posedge roll or posedge reset) begin if ( reset == 1 ) add1 = 1; else begin if ( roll ==1 ) begin add1 = add1+ 1; if ( add1 == 6 ) add1=1; end end end always @ ( posedge clk2 or posedge roll or posedge reset ) begin if ( reset == 1 ) add2 = 1; else begin

if ( roll ==1 ) begin add2 = add2+ 1; if ( add2== 6 ) add2=1; end end end clock1 L1 ( clk, reset, clk1); clock2 L2 ( clk, reset, clk2); // counter C0 ( add1, clk1, reset, roll); // counter C1 ( add2, clk2, reset, roll); //ADDER A1 (add1, add2, clk, reset, sum); always @ ( add1 or add2 ) sum = add1 + add2 ; endmodule module displayhex(hex, led); input [3:0] hex; output reg [6:0] led; always @(hex) case (hex) 4'b0000 4'b0001 4'b0010 4'b0011 4'b0100 4'b0101 4'b0110 default endcase endmodule

: : : : : : : :

led led led led led led led led

= = = = = = = =

7'b1000000; 7'b1111001; 7'b0100100; 7'b0110000; 7'b0011001; 7'b0010010; 7'b0000010; 7'b1000000;

//0 //1 //2 //3 //4 //5 //6

module dice( clk, reset, datain, sum, win, lose, roll, point, save, rb ); output wire rb; output wire [3:0] sum; input wire clk, reset, datain; reg d7, d711,d2312, equal; output reg win, lose, roll,save; // output reg [2:0] next_state; output reg [3:0] point; reg [2:0] state,next_state ; //wire save; dice_roller D0 ( datain, reset, clk, sum); assign rb = ( datain == 0 ) && ( state == `S4); always @(sum) begin d7 = (sum == 7); d711 = (sum == 7) || (sum == 11); d2312 = ((sum == 2) || (sum == 3) || (sum == 12)) ; end always @(point or sum) equal = ( state == `S5 )&&(point == sum);

always @( posedge clk ) if (save) point = sum; always @(posedge clk or posedge reset) if ( reset == 1) begin state = `S0; end else begin state = next_state; if ( datain == 1 && next_state != `S2 && next_state != `S3) begin roll = 1; end else begin roll = 0; end end always @( state or datain or d7 or d711 or d2312 or equal or reset ) begin save=0; win=0;lose=0; case(state) `S0: begin // Defining output // Defining next state using if~else statement if( datain == 1) begin next_state = `S0; end else begin next_state = `S1; end end `S1:begin if ( datain != 1 ) begin //save = 1; if (d711) next_state = `S2; else if (d2312) next_state = `S3; else begin save = 1; next_state = `S4; end end end `S2: begin win=1; lose=0; if ( reset==1 ) next_state = `S0; else next_state = `S2; end

`S3 : begin win=0 ; lose =1 ; if ( reset==1 ) next_state = `S0; else next_state = `S3; end `S4 : begin if ( rb != 1) next_state = `S5; else next_state = `S4; end `S5 : begin if ( datain != 1 ) begin if ( equal ) next_state = `S2; else begin if ( d7 ) next_state = `S3; else next_state = `S4; end end else next_state = `S5; end endcase end endmodule /*module test_logic ( sum, n_state, D7, D711, D2312, clk); input wire [3:0] sum; input wire [2:0] n_state; input wire clk; output reg D7, D711, D2312; always @ begin assign assign assign ))); end endmodule module luu (data_out, data_in, load, clk, rst); ( posedge clk) D7 = ((n_state == `S5) && (sum ==7)); D711 = ((n_state == `S1) && ((sum ==7) || (sum == 11))); D2312 = ((n_state == `S1) && ((sum ==2) || ( sum ==3 ) || ( sum == 12

output reg [3:0] input [3:0] input input

data_out; data_in; load; clk, rst;

always @ (posedge clk or negedge rst) begin if ( rst==1 ) data_out <= 0; else if (load) data_out <= data_in; end endmodule module cmp ( in1, in2, equal, clk); input [3:0] in1,in2; input wire clk; output reg equal; always @ ( posedge clk ) begin equal = ( in1 == in2 ); end endmodule /* module dice_game ( clk, reset, win, lose, datain, sum, point ); input wire clk, reset, datain; output reg win, lose; output reg [3:0] sum, point; wire roll, equal, D7, D711, D2312, save ; wire [2:0] next_state; always @ ( posedge clk or negedge reset) begin if ( reset==1 ) begin point <= 0; end else begin if (save) point <= sum; end end dice_roller D0 ( roll, reset, clk, sum); luu R0 ( point, sum, save, clk, reset); cmp P0 ( sum, point, equal, clk ); test_logic T0 ( sum, next_state, D7, D711, D2312, clk); controller C0 ( clk, reset, datain, win, lose, roll, D7, equal, D711, D2312 , next_state, save ); endmodule */