Unit 11 Problem Solutions

11.1 Z responds to X and to Y after 10 ns; Y responds to Z after 5 ns. See FLD p. 646 for answer. P and Q will oscillate. See FLD p. 646 for timing chart. See FLD p. 647 for solution. See FLD p. 647 for solution. 11.2 See FLD p. 646 for solution. For part (b), also use the following Karnaugh map. Dont cares come from the restriction in part (a).
H Q R 00 01 11 0 0 0 1 0 1 X X 1 1

11.3

11.4 11.5

10

Q+ = R + H Q

11.6 (a)

S R Q Q+ 00 0 0 00 1 1 01 0 0 01 1 0 10 0 1 10 1 1 11 0 1 11 1 1

R Q

S 00 01 11 10

0 0 1 0 0

1 1 1 0 0

11.6 (b) See FLD p. 647 for solution. 11.7 11.8 11.9 11.10 11.12 See FLD p. 647 for solution. See FLD p. 647 for solution. See FLD p. 648 for solution. See FLD p. 648 for solution. For every input/state combination with the condition SR = 0 holding, each circuit obeys the next-state equation Q+ = S + R'Q. When S = R = 1, in (a), both outputs are 1, and in (b), the latch holds its state.

Q+ = R'Q + S R'

11.11

S R Q

11.13

D G Q

S R

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11.14

Clock D Q P
11.15 (b) A set-dominant FF from an S-R FFThe arrangement will ensure that when S = R = 1, S1 = 1, R1 = 0, and Q+ = 1.

11.15 (a) S R Q 00 0 00 1 01 0 01 1 10 0 10 1 11 0 11 1

Q+ 0 1 0 0 1 1 1 1

R Q

S 00 01 11 10

0 0 1 0 0

1 1 1 1 1

S CK R

S1 R1

Q+ = S + R'Q

Q'

11.16

Clock S R Q

11.17 (a)-(b)

Clock J K

(a) Q (b) Q
11.18 (a)-(b)

Clock Q

(a) D (b) T

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11.19

Clock Q0 Q1 Q2
5 10 15 20 25 30 35 40 45 50 t (ns)

11.20

Clock PreN T Q

11.21

Clock ClrN D Q1 Q2

11.22 (a)

D CK

11.22 (b) R will not be ready until D goes through the inverter, so we must add the delay of the inverter to the setup time: Setup time = 1.5 + 1 = 2.5 ns Propagation delay for the DFF: 2.5 ns (same as for the S-R flip-flop, since the propagation delay is measured with respect to the clock)

Q'

When D = 0, then S = 0, and R = 1, so Q+ = 0. When D = 1, then S = 1, and R = 0, so Q+ = 1. 11.23

+V S Q

+V

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