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592

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 4, APRIL 1998

MOS Charge Pumps for Low-Voltage Operation


Jieh-Tsorng Wu, Member, IEEE, and Kuen-Long Chang

AbstractNew MOS charge pumps utilizing the charge transfer switches (CTSs) to direct charge ow and generate boosted output voltage are described. Using the internal boosted voltage to backward control the CTS of a previous stage yields charge pumps that are suitable for low-voltage operation. Applying dynamic control to the CTSs can eliminate the reverse charge sharing phenomenon and further improve the voltage pumping gain. The limitation imposed by the diode-congured output stage can be mitigated by pumping it with a clock of enhanced voltage amplitude. Using the new circuit techniques, a 1.2-V-to-3.5-V charge pump and a 2-V-to-16-V charge pump are demonstrated. Index Terms Charge pump, high-voltage generator, voltage multiplier.

voltage at node 2 is settled to , where and are dened as the steady-state lower voltage at node 1 and node 2, respectively. Both MD1 and MD3 are reverse biased, and the charges are being pushed from node 1 to node 2 through MD2. The nal voltage difference between node 1 and 2 is the threshold voltage of MD2. The necessary condition for the must be larger than the charge pump to function is that , i.e., MOSTs threshold voltage (2) The voltage pumping gain for the second pumping stage is dened as the voltage difference between and , which can be expressed as (3) is the threshold voltage of MD2, modied by where the body effect due to the source voltage . The geometric dimension of the MOSTs has no effect on the voltage pumping ratio of the MOST diodes is too gain. However, if the small so that the transient response of the pumping operation cannot settle within the period when the corresponding clock is high, then the resulting voltage pumping gain will be smaller than that predicted by (3). and are As the supply voltage decreases, both decreased accordingly, and the voltage pumping gain per stage is not much larger than the is also reduced. Furthermore, if MOSTs threshold voltage, then the inuence of the MOSTs body effect cannot be neglected. Especially at the high-voltage nodes near the output, the increase in the threshold voltage can lower the voltage pumping gain signicantly. In fact, the circuits output voltage reaches its maximum when the body [6]. It effect causes the threshold voltage to be equal to is possible to use oating-well devices to eliminate the body effect [8]. However, the resulting charge pumps may generate substrate currents and the voltage pumping gain per stage is still reduced by the threshold voltage. This paper describes new charge pumps that are suitable for low-voltage operation and offer better voltage pumping gains and higher output voltages than the Dickson charge pump. The charge pump utilizing the static charge transfer switches (CTSs) is described in Section II. A ve-stage prototype implemented in a standard 0.8- m CMOS technology is demonstrated. The circuit can operate with a 1.2-V supply and generate a boosted output of 3.5 V. For higher supply voltages, such as 2 V, charge pumps described in Section III can be used. They are new charge pumps employing the dynamic CTSs to increase the voltage pumping gain. The performance improvement is veried by both simulation and measurement results. In Section IV, a modication to the diode-congured

I. INTRODUCTION HARGE pumps are circuits that can pump charge upward to produce voltages higher than the regular supply voltage. Charge pumps have been used in the nonvolatile memories, such as EEPROM and Flash memories, for the programming of the oating-gate devices [1], [2]. They can also be used in the low-supply-voltage switched-capacitor systems that require high voltage to drive the analog switches [3], [4]. Most MOS charge pumps are based on the circuit proposed by Dickson [5][7]. As shown in Fig. 1, the MOSTs in the Dickson charge pump function as diodes, so that the charges can be pushed only in one direction. The two pumping clocks and are out-of-phase and have a voltage amplitude . The value of is usually identical to the supply of . Through the coupling capacitors C1C4, the two voltage clocks push the charge voltage upward through the transistors. Neglecting the boundary conditions, the voltage uctuation at is identical and can be expressed as each pumping node (1) is the capacitance of C1C4, is the parasitic where is the capacitance associated with each pumping node, is the output current frequency of the pumping clocks, and loading. goes from low to high and from high to When , and the low, the voltage at node 1 is settled to
Manuscript received June 29, 1997; revised October 27, 1997. This work was supported by the National Science Council, Contract NSC-84-2221-E009-013, and Macronix International Co., Ltd. J. T. Wu is with the Department of Electronics Engineering, National ChiaoTung University, Hsin-Chu, 300, Taiwan, R.O.C. K.-L. Chang is with Macronix International Co., Ltd., Hsin-Chu, Taiwan, R.O.C. Publisher Item Identier S 0018-9200(98)02330-0.

00189200/98$10.00 1998 IEEE

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Fig. 1. A four-stage Dickson charge pump.

Fig. 2. A four-stage charge pump using static CTSs (NCP-1).

output stage is described. The change is necessary if the charge pumps are required to generate boosted outputs of more than 10 V. Using the technique, a 2-V-to-16-V charge pump can be implemented efciently. And nally, conclusions are given in Section V. II. CHARGE PUMPS USING STATIC CTSs Instead of using the diodes to direct the ow of charges in pumping operation, the MOST switches with proper on/off cycles, referred to as CTSs, have been used to realize the charge pumps and show better voltage pumping gain than the diodes [9][13]. Fig. 2 shows a new charge pump (NCP-1) using the MOST CTSs with static backward control [3]. MD1MD4 are diodes for setting up the initial voltage at each pumping node. They are not involved in the pumping operation. MS1MS4 are the CTSs. The idea is using the already established high voltage to control the CTS of the previous stage. If the switches can be turned on and turned off at the designated clock phases, they can also allow the charge to be pushed in only one direction. Then for each pumping stage, the upper voltage of the input is equal to the lower

Fig. 3. Measured output voltage of a 5-stage NCP-1 chip.

DD = 1:2 V.

voltage of output, since the MOST switch is turned on at this moment. The voltage pumping gain per stage can be expressed

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 4, APRIL 1998

Fig. 4. A four-stage charge pump using dynamic CTSs (NCP-2).

as (4)

node 3 is determined only by the threshold voltage of MS2, i.e., (7)

Comparing with (3), the NCP-1 is expected to have better charge pumping performance. is high and is low, the voltage at In Fig. 2, when to , the voltage at node 2 is , node 1 is pushed from . For nominal operation, and the voltage at node 3 is the MS2 switch must be turned on by the voltage at node 3. , which must be The gate-to-source voltage of MS2 is modied by the source larger than the threshold voltage voltage , i.e., (5) Comparing with (2), the NCP-1 is more suitable for lowvoltage operation. is low and is high, the On the other hand, when voltage at node 1 is , the voltage at node 2 is , and the voltage at node 3 is also . For ideal operation, MS2 is to be turned off. Therefore, the gate-to-source voltage of MS2, , must be smaller than the threshold voltage which is modied by the source voltage , i.e., (6) Since (5) must always be true, the requirement of (6) can never be met. Therefore, MS2 cannot be completely turned off, and reverse charge sharing between node 2 and node 1 can occur. In such cases, the operation of the charge pump becomes complicated. The voltage uctuations at the pumping nodes are different and smaller than that predicted by (1). As a result, the overall voltage pumping gain is reduced. Note that the maximum voltage pumping gain between node 1 and

A ve-stage NCP-1 has been fabricated using a standard 0.8- m CMOS technology. This prototype is similar to the circuit shown in Fig. 2, except that MD5 and MDO are merged into one device, the pumping capacitor C5 is connected to the source node of MDO, and the output voltage is smoothed by an RC low-pass lter [3]. The threshold voltage of the nMOSTs is 0.7 V. The gate geometric size is 150 m by 0.8 m for all devices. All pumping capacitors are 20 pF. The circuit is used in a 1.2-V switched-capacitor system for driving MOST analog switches. Fig. 3 shows the measured output voltages of the prototype at different output current loadings and clock frequencies, while a 1.2-V supply is applied. The prototype can maintain a 3.5-V output while providing 30 A of output current. For comparison, the output voltage of a ve-stage Dickson charge pump operating under the identical condition is less than 2 V. III. CHARGE PUMP (NCP-2) USING DYNAMIC CTSs If the reverse charge sharing phenomenon inherent in the NCP-1 circuit can be eliminated, better pumping performance can be obtained. In other charge pump designs [9][11], each CTS is accompanied by an auxiliary pass transistor so that the CTSs can be turned off completely in the designated period. However, the CTSs in those charge pumps are difcult to turn on in the low-voltage environment. Techniques such as putting CTSs in individual wells to eliminate the body effect and applying boosted clocks to drive the CTSs have been used [11]. The four-phase clock scheme has also been used to precharge the CTSs so that they become easier to turn on [9],

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[11]. However, additional concern is that the auxiliary pass transistors must be turned on during the precharging phase. Fig. 4 shows a new charge pump (NCP-2) that can assign the control inputs for the CTSs dynamically by adding pass transistors MNs and MPs to the NCP-1 circuit [14]. The CTSs in NCP-2 can be turned off completely when required and still can be turned on easily by the backward control as in the NCP-1 case. The expression for the single-stage voltage pumping gain is the same as (4). The operation of the dynamically controlled CTSs is exis high and is low, both the plained as follows. When , and the voltage at voltages at node 1 and node 2 are above. If node 3 is and (8)

is the threshold voltage of pMOSTs, then MP2 where is turned on, causing MS2 being turned on by the voltage at node 3. In this period, MN2 is always off since its gate-tosource voltage is zero. is low and is high, the On the other hand, when voltage at node 1 is , both the voltages at node 2 and node above. If 3 are (9) then MN2 can be turned on and MS2 can be turned off completely. In this period, MP2 is also off, disengaging MS2 from the control of node 3. Unlike the NCP-1 case, the two necessary conditions of (8) and (9) can be satised simultaneously. Note that, for each pMOST in Fig. 4, each individual well is connected to the devices drain node. During goes from high to low, it the short period of transition when is possible for the charges at the CTSs gate node to be injected into the well. However, the supply of the charges is limited since the CTSs gate is a oating node at this very moment. With proper layout precaution, latch-up can be prevented. Fig. 5 shows the simulation results that compare the output voltages of various charge pumps at different supply voltage and output current loading. All charge pumps have four pumping stages. All coupling capacitors are 15 pF. The voltage smoothing capacitor at the output is 30 pF. The frequency for the NCP-2 of the pumping clocks is 5 MHz. The is less than that predicted by (1) due to additional parasitic capacitors and switching delay. Nevertheless, the NCP-2 still exhibits the best charge pumping performance among the three circuits. For the NCP-1 charge pump, the effect of the reverse charge sharing become more apparent as the supply voltage increases. In case of 2.5-V supply voltage and low output current loading, the NCP-1 performs no better than the Dickson charge pump. However, the NCP-1 shows a smaller equivalent output resistance than the other two circuits, since the reverse charge sharing phenomenon can make the voltage variation due to the pumping gain less sensitive to the changes in output current loading. A four-stage NCP-2 has been fabricated in a 0.8- m CMOS Flash technology. Fig. 6 shows the measured output voltages at different supply voltage and output current loading. This prototype is designed for 3-V operation. The output can

Fig. 5. Simulated output voltages of various four-stage charge pumps.

Fig. 6. Measured output voltage of a four-stage NCP-2 chip.

Fig. 7. Diode-congured output stage.

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 4, APRIL 1998

Fig. 8. Diode-congured output stage driven by an enhanced clock.

reach above 9.5 V with 10 A current loading. Under the same condition, the output voltage is 7.3 V for the Dickson charge pump and is 5.8 V for the NCP-1. Also shown in this plot are the measurement results under 2.75-V and 2.5-V supply voltage. The measured output voltages are lower than those predicted by simulation. This is due to the degrading and clock drivers as the supply performance of the voltage decreases. IV. CHARGE PUMP OUTPUT STAGES In NCP-1 and NCP-2 circuits, CTS cannot be used in the output stage since no adequate waveform is available for switching control. The diode-congured circuit shown in Fig. 7 is used instead. The charges are simply pushed through . The capacitor the MOST diode, MDO, to the output, is used to smooth the voltage uctuation at the output. In order to generate a uctuating voltage waveform to control MS4, an MD5 MOST diode is added, whose output, node , is ac-coupled to the clock through C5. The voltage , which is larger uctuation at node is dened to be , due to the absence of output current than the nominal loading. The condition to turn on MS4 becomes (10) This requirement severely limits the minimum operating supply voltage and the maximum achievable output voltage. The limitation can be mitigated by increasing the value of in (10). As shown in Fig. 8, this can be accomplished , by driving the output stage with a new enhanced clock, , but has a larger voltage which inherits the timing of amplitude. A high-voltage clock generator is required to clock. Since the loading of is relatively generate the small, the driving capability of this clock generator need not be large. An example of the high-voltage clock generator is shown
Fig. 9. A high-voltage clock generator.

in Fig. 9 [4], [15]. Using the cross-coupled bootstrapping, the voltage amplitude of the input clock can be doubled. In Fig. 9, is generated by a separate but similar the high voltage bootstrapping circuit [4]. Fig. 10 shows the simulation results that compare the output voltages of various charge pumps. The circuit parameters are identical to those used in the simulations for Fig. 5. The condition is 2 V supply voltage and 10 A output current loading. The NCP-3 is a charge pump similar to NCP-2 but instead applying the output stage shown in Fig. 8 which is driven by the high-voltage clock generator shown in Fig. 9. The output voltages are shown against different numbers of . If is low and the output voltage is also pumping stages low, both NCP-3 and NCP-2 have similar voltage pumping increases, the output of NCP-2 is limited to gain. But as 9.7 V due to the constraint imposed by its output stage. In the is enhanced twofold, and the output NCP-3 case, the voltage can easily exceed 16 V using 12 pumping stages. Unlike the NCP-2 charge pump, the output voltage of the NCP-1 shown in Fig. 10 is not saturated at large . This is

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[3] [4] [5] [6] [7] [8]

[9]

Fig. 10.

Io = 10 A.

Simulated output voltages of various charge pumps.

VDD

= 2 V,
[10] [11] [12] [13]

because its output-stage constraint has not been reached in this and less switching simulation exercise, due to its larger delay. V. CONCLUSION Charge pumps utilizing CTSs to direct charge ow can provide better voltage pumping gain than those using MOST diodes. Using the internal boosted voltage to backward control the CTS of the previous stage yields charge pumps that are suitable for low-voltage operation. The resulting charge pumps (NCP-1) can operate under a supply voltage below 1.2 V and still offer good pumping performance. The reverse charge sharing phenomenon inherent in the NCP-1 circuits can be eliminated by applying dynamic control to the CTSs. The NCP-2 charge pumps use two additional MOSTs per stage to implement the dynamic CTSs. The performance improvement of the NCP-2 over the NCP-1 is more signicant at higher supply voltages. The limitation imposed by the diode-congured output stages in NCP-1 and NCP-2 can be mitigated by pumping the output stage with clock of enhanced voltage amplitude. The NCP-3 is a charge pump based on NCP-2 and uses a voltage doubler to enhance the clock amplitude twofold for driving the output stage. A 12-stage NCP-3 circuit can generate a boosted output of 16 V from a 2-V supply, while the output of the NCP-2 can reach as high as 9.7 V only. In conclusion, circuit techniques are available to generate high voltage efciently from a power supply below 2 V. REFERENCES
[1] T. Tanzawa, T. Tanaka, K. Takeuchi, and H. Nakamura, Circuit technologies for a single-1.8 V ash memory, in Symp. VLSI Circuits Dig. Tech. Papers, June 1997, pp. 6364. [2] T. Kawahara, T. Kobayashi, Y. Jyouno, S. Saeki, N. Miyamoto, T. Adachi, M. Kato, A. Sato, J. Yugami, H. Kume, and K. Kimura, Bitline clamped sensing multiplex and accurate high voltage generator for

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quarter-micron ash memories, IEEE J. Solid-State Circuits, vol. 31, pp. 15901600, Nov. 1996. J.-T. Wu, Y.-H. Chang, and K.-L. Chang, 1.2 V CMOS switchedcapacitor circuits, in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1996, pp. 388389. T. B. Cho and P. R. Gray, A 10 b, 20 Msample/s, 35 mW pipeline A/D converter, IEEE J. Solid-State Circuits, vol. 30, pp. 166172, Mar. 1995. J. F. Dickson, On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique, IEEE J. SolidState Circuits, vol. 11, pp. 374378, June 1976. J. S. Witters, G. Groeseneken, and H. E. Maes, Analysis and modeling of on-chip high-voltage generator circuit for use in EEPROM circuits, IEEE J. Solid-State Circuits, vol. 24, pp. 13721380, Oct. 1989. T. Tanzawa and T. Tanaka, A dynamic analysis of the Dickson charge pump circuit, IEEE J. Solid-State Circuits, vol. 32, pp. 12311240, Aug. 1997. K.-H. Choi, J.-M. Park, J.-K. Kim, T.-S. Jung, and K.-D. Suh, Floatingwell charge pump circuits for sub-2.0 V single power supply Flash memories, in Symp. VLSI Circuits Dig. Tech. Papers, June 1997, pp. 6162. A. Umezawa, S. Atsume, M. Kuriyama, H. Banba, K. Imamiya, K. Naruke, S. Yamada, E. Obi, M. Oshikiri, T. Suzuki, and S. Tanaka, A 5-V-only operation 0.6-m Flash EEPROM with row decoder scheme in triple-well structure, IEEE J. Solid-State Circuits, vol. 27, pp. 15401546, Nov. 1992. K. D. Tedrow, J. J. Javanifard, and C. Galindo, Method and apparatus for a two phase bootstrap charge pump, U.S. Patent 5 432 469, July 1995. K. Sawada, Y. Sugawara, and S. Masui, An on-chip high-voltage generator circuit for EEPROMs with a power supply voltage below 2 V, in Symp. VLSI Circuits Dig. Tech. Papers, June 1995, pp. 7576. E. Lingstaedt and P. Miller, MOSFET multiplying circuit, U.S. Patent 5 029 063, July 1991. J. Tsujimoto, Charge pump circuit having a boosted output signal, U.S. Patent 4 935 644, June 1990. J.-T. Wu and K.-L. Chang, Low supply voltage CMOS charge pumps, in Symp. VLSI Circuits Dig. Tech. Papers, June 1997, pp. 8182. Y. Nakagome, H. Tanaka, K. Takeuchi, E. Kume, Y. Watanabe, T. Kaga, Y. Kawamoto, F. Murai, R. Izawa, D. Hisamoto, T. Kisu, T. Nishida, E. Takeda, and K. Itoh, An experimental 1.5-V 64-Mb DRAM, IEEE J. Solid-State Circuits, vol. 26, pp. 465472, Apr. 1991.

Jieh-Tsorng Wu (S83M87) was born in Taipei, Taiwan, on August 31, 1958. He received the B.S. degree in electronics engineering from National Chiao-Tung University, Taiwan, in 1980 and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1983 and 1988, respectively. From 1980 to 1982 he served in the Chinese Army as a Radar Technical Ofcer. From 1982 to 1988, at Stanford University, he focussed his research on high-speed analog-to-digital conversion in CMOS VLSI. From 1988 to 1992 he was a Member of Technical Staff at Hewlett-Packard Microwave Semiconductor Division, San Jose, CA, and was responsible for several linear and digital gigahertz IC designs. Since 1992 he has been an Associate Professor at National Chiao-Tung University, HsinChu, Taiwan. His research interests include integrated circuits and systems for high-speed networks and wireless communications. Dr. Wu is a member of Phi Tau Phi.

Kuen-Long Chang was born in Taipei, Taiwan, on October 8, 1966. He received the B.S. degree in electronics engineering from National Taiwan University of Science and Technology, Taiwan, in 1992 and the M.S. degree in electronics engineering from National Chiao-Tung University, Taiwan, in 1995. Since 1995 he has been with Macronix International Co., Ltd., Hsin-Chu, Taiwan. He is currently working on Flash memory design.