Capacitance of

Forward Biased Diode

When a diode changes from reverse biased (with little current through it)
to forward biased (with significant current across it) the charge being
stored near and across the junction changes

Part of the change in charges is due to the change in the width of the
depletion region and therefore the amount of immobile charge stored in it
( - Cj )

An additional change in the charge storage is necessary to account for the

excess of minority carriers close to the depletion region edges required for
the diffusion current to exists. This component is modeled by another
capacitance, called the diffusion capacitance ( - Cd)

As a diode is turned off (changes from forward biased to reverse biased)

for a short period of time a current will flow in the negative direction until
the minority charge is removed

Charge of Forward Biased Diode

Direction of positive current
immobile charge

electron
diffusion

- - - - - -

hole
diffusion

In the P region we have a lot of holes

that will diffuse toward the N region

+
+
+

+
+
+

+
+
+

+
+
+

In the N region we have a lot of electrons

that will diffuse toward the P region

Depletion Region

Total Capacitance of
Forward Biased Diode

It is the sum of the diffusion capacitance Cd and the depletion

capacitance Cj
C total -::C d +C

For a forward biased diode the junction capacitance is roughly

approximated by:
C j 2 C j0
C j 2 C j0

for V D 0.75

The approximation is not critical since the diffusion capacitance is

typically much larger than than the depletion capacitance
Cd

Cj

Diffusion Capacitance

To find the diffusion capacitance we first find the minority charge

close the depletion edges Qd and then differentiate it with respect
to the voltage applied Vd.
Small signal
diffusion capacitance

dQ
C d= dV
d
d

V D = TT

The diffusion capacitance of a forward biased diode

is proportional to the diode current

I d (@ V D )
VT

excess of minority
charge (holes)
stored in the N region

Diffusion Charge
Q d =Q p +Q
n

Q p q AA n p p x ' dx ' "' q A

0

excess of minority
charge (electrons)
stored in the P region

Lp

np

dx '

Vd
VT

q AA n p0 O e

1l e

-x'
Lp

dx ' '

Vd
VT

cJJ

-x'
Lp

' q A n p0 e -1)J e

n
=q A
e
ND

Vd
V

)[

n p ( x ' )=n p ( x ' =0 )

e
x'
np0

dx ' =

2
i

Vd

q A n i Ln V
Q n :::
e -1
NA

L pe

-x'
Lp

- x ' oo
Lp
0

Vd

q A n2i L p V
=
e -1
ND
T

)
pn( =0)

p n ()= p n
(=0)e

np(x'=0)
Vd
VT

0
-xp

n p0 e
0

p n0 e

Vd
VT

Ln

0
pn0
xn

Diffusion Charge

The excess hole charge stored in the N region is given by:

Q p = A q [ pn ( x n )- p n0 ]
L p==A q L p V IV
p
n0
1
2
2
e
Lp
Lp
Ip
AJ p
:::I p I p
Dp
Dp
d

Jp
p n0 O
e

qD p
L p p n0
Vd VT

Vd V

1\

Lp
1 l) J p
qDp

pn x n

p n0

V d /V T

Lp

Dp

Similarly, the excess electron charge stored in the P region is:

Q n= I n
Tn

Total Diffusion Charge

Thus, the total excess minority carrier charge is:

Q d =Q p +Q n = I p T p + I n
Tn

Since the diode current is I d =I p + I

n as:
to express the excess charge
Q d =TTI
d

it is more convenient

(where TT is called mean transit time )

Diffusion Capacitance
dQ d

] [

d V

1
rd

[ 1
dI d
dV d

VD

= d -rT I d
dV
D
d

Vd
VT

d I ss e 1 ll
dV d

Cd

VD

[ ]

d VD

1 [ 1

Id
VT
T

=T T dI d
dV

Vd
VT

VD

VD

I se
VT

VD

=-rT
r
d

I d+ I s
VT

] [ ]
Id
R;
VT

VD

VD

Transition Time

The general expression for ,;T is quite cumbersome:

TT =C dr
d

where

1
rd

C d=

dI d
dV d

dQ
dVd
d

with

with

2
i

Vd
VT

2
i

q A Dn n
q A Dp n
I d ==
+
e -1 )
Ln N A
Lp N D

Qd =

2
i

()

q A n L p q A n Ln
e
N
N
i
D
A

Vd
VT

-1

Transition Time

In practice, since usually diodes are single sided (i.e. one side will be
much more heavily doped than the other side) the minority charge
storage in the heavily doped side can be ignored
Vd
VT

2
i

q A n Lp
Q p ==
ND

-1

Qn
==

q A n2i Ln
NA

Vd
VT

-1

Assuming the P side is more heavily doped than the N side:

NA

ND

Qp

Qn

Qd Q

Id Ip

Lp
Dp

NOTE:
Holes (Qp) are minority
carriers on the N side
Electrons (Qn) are minority
carriers on the P side

Single Sided Diodes

One side of the diode is more heavily doped than the other

Many of the junctions encountered in integrated circuits are onesided junctions with the lightly doped side being the substrate or
the well.

Foe single sided diodes the depletion region will extend mostly on
the lightly doped side.

The depletion capacitance is almost independent of the doping

concentration on the heavily doped side

Single Sided Diodes

The PN junctions inside CMOS ICs are single-sided

NMOS transistors have parasitic diodes with the N side more heavily
doped than the P side: N D > N A

PMOS transistors have parasitic diodes with the P side more heavily
doped than the N side: N A N D

NOTE: in general within an MOS transistor, it is undesirable to

have a forward biased junction, it usually means there is a
problem.

Schottky Diodes

A different type of diode, can be realized by contacting a metal to a

lightly doped semiconductor region.

The use of a lightly doped semiconductor, causes a depletion region

to form at the interface between the aluminum anode and the n+
silicon region

Schottky Diodes

The voltage drop of a forward biased Schottky diode is smaller. The

value depends on the metal used. For aluminum is approx 0.5 V

When the diode is forward biased there is no minority charge storage

in the lightly doped n+ region. Thus Cd = 0

The absence of diffusion capacitance makes the diode much faster.

Diodes realized in CMOS technology

t--t:+--o
Side
View

n-well
p-substrate

p-substrate

,-,

Top
View

()

Figure 14.54 Diode re lized in C 10. techno] gy.

NOTE:
For the case of Fig 14.54(a) the anode is inevitably grounded

Diode SPICE model

Parameter

SPICE

Description

Is

IS

Saturation Current

Rs

RS

Ohmic Series Resistance of the p-n regions and the contacts

Emission Coefficient

q)o

VJ, PB, PHI

Built-in Voltage

CJo

CJO, CJ

Zero Bias Junction Capacitance

M.J

MJ, M

Grading Coefficient

1r

TT

Transit Time

VK

BV

Reverse Breakdown Knee Voltage

IK

IBV

Reverse Breakdown Knee Current

Diode SPICE Modeling

[ ( )

I d = I s exp

Vd
- 1 +GMINV d
n VT
Convergence Aid

BV +V d
T

BV
VT

]
=- IS (BV/VT)

I d =-I s +GMINV
d

MOS physical structure

p-dunnel

U11JlStstor

ta

n- ell

p ubslmlc

Phy ical .tntcture fan n-channel. nd p-ch:mn

Metal(AI)

Gate

Bulk or substrate

Fig. 1.6 A cross section of o typical n<honnel transistor.

n n-\ ell

Thermal Equilibrium

Absence of any stimulus to the device

The populations of electrons and holes are each in equilibrium

and, therefore must have zero current densities
0 q n0
n

0 q n0

Dn 0
E0 qD
n
dx
dp0
E 0 -q D
p
dx

n0

d 0
dx

dn 0
Dn
dx

D n dn 0
n n0

dn0
VT
n0

n ( x
cp 0 ( x )-cp0 ( x R )= V T ln 0
n)0 ( x R
)

xR

VT

xR

dn0
n0

Thermal Equilibrium
n ( x
cp 0 ( x )-cp0 ( x R )= V T ln 0
) (x )
0

By convention
the reference for the potential
n
is chosen to be the point where the carrier
concentration is the intrinsic concentration
n0 ( x
)

cp 0 ( x R )
=0

when n 0 ( x R )
=n i

cp 0 ( x )

n0 ( x )=n
i e

NOTE:
for N type silicon since n0 > ni the electrostatic potential at equilibrium is positive

Thermal Equilibrium
A similar derivation for the hole concentration leads to the following
result:

cp 0 ( x )=-V T ln

( )
p0 ( x )
ni

p0 ( x )=ni e

VT

NOTE:
for P type silicon since p0 > ni the electrostatic potential at equilibrium is negative

MOS Capacitor in Thermal

Equilibrium At equilibrium the p-

substrate and the n+

source and drain
form a pn junction.
Therefore a depletion
region exists between
the n+ source and drain
and the p- substrate

Since source and drain are separated by back-toback junctions, the resistance between the source
and the drain is very high (> 1012 ohm)

gate

source/drain/bulk

Figure. Using the MOSFET as a capacitor

The gate and the substrate of the MOS

transistor form a parallel plate capacitor
with the SiO2 as dielectric

MOS structure in
Thermal Equilibrium
VGB = 0

n+

( )

N
equilibrium potential in
cp p=-V T ln A
ni
the silicon (bulk=substrate)

N A 1017 cm-3

N D v331019 cm-3

n i 1010 cm-3

equilibrium potential in
the polysilicon (gate)

n+

mV

550 mV

E0

cpn + = V T ln

420 mV

( )
ND
ni

970

MOS in Thermal Equilibrium

VGB = 0

n+

970 mV

E0

From the sign of the potential drop across the MOS structure it
follows that the electric field points from gate to bulk.

Therefore, a positive charge must be present on the polysilicon gate

and there must be a balancing negative charge in the p-type silicon
substrate (the oxide will be considered a charge-free perfect
insulator)

Charge on the MOS in TE

Since the gate is highly conductive n+ polysilicon the gate charge QG0 can be
thought as a sheet charge located at the bottom surface of the polysilicon gate
The charge on the p-type silicon substrate QB0 is formed by the immobile
negatively charged acceptor ions (to a depletion depth of Xd0 ) left behind by
the mobile holes repelled by the positive charge on the gate.
VGB = 0
0
0

M O

Charge on the MOS in TE

,lc char

c,

n \llh
-d Jll t1 n
I ul char 'C 8

i ure
Qualitative picture of charge distribu ion in an MOS capacitor
3.21
p- ype
subs rate in thermal equilibrium.

000 =-0Bo=qN A X do [units:Cicm

ih

Potential across the MOS in TE

Surface Potential
Potential at the SiO2-silicon
interface (x=0)

Voltage drop
across the oxide

Built in Voltage across

the MOS structure

BUILT-IN - cpn+ -cp p

Voltage drop across

the depletion region
In the silicon

= V ox , 0 +V
0

B,

Potential across the MOS in TE

The equilibrium potential of a given material is commonly

referred as its Fermi potential
cp n+

( )

ND
== cpF-gate= V T ln
ni

cp p := cpF-bulk =-V T ln

( )
NA
ni

The Built in voltage across the MOS structure is often

expressed in term of the work function between the gate
material and the bulk silicon
-cp MS = cp F-gate-cpF-bulk =cp n+ -cp p := BUILT-IN = V T ln

( )
NDNA
2

ni

NOTE: This term is referred as the metal-to-silicon work function even though the
gate terminal is something other than metal (i.e. polysilicon)

MOS in TE: fixing KVL

VGB = 0

mn+

V ox , 0 V B0

pm

V ox , 0 V B0

mn+

=( cp n+-cp p ):=cp BUILTIN

pm

MOS in TE

NOTE:
for the case of TE the
gate and the bulk metal
contacts are at the same
potential

n+

mn+

pm

MOS in TE: Quantitativ Analysis

The total excess charge in the region
-tox x Xd0 is zero (neutrality of charge)
The electric field is confined in the region
-tox < x < Xd0

E ox
+

E (0 )

In the oxide (-tox < x < 0) the charge density is zero thus the
field is constant (Eox):
p 0

Gauss ' s Law :

dE
=
dx E

Boundary condition at the oxide/silicon interface (0- x 0+):

+
+
0E
=E
0E
(0
)=
-t
(0
E
ox
ox
s

Eox
s

+
E ox -t E ox = E (0
)

Es
ox

::3

MOS in TE: Quantitative Analysis

E ox
Within the same material the
electric field will not jump !

In the charged region of the silicon oxide/silicon interface (0+s x < Xd0) the charge density is
constant:

dE

qNA
dx
Es
0

E E X do

X do

dE
E (0+ )

E E X d0 O)- s E 0

-q N A
x
dx
Es 0+

q N A X d0

E ox =E (0- ) = E (0+ )

Eox

+ ='q N A
E
0
X d0

Es

qN A
X d0
Eox

MOS in TE: Quantitative Analysis

E ox
Within the same material the
electric field will not jump !

Just for the sake of double-checking the correctness of the

previous result let's also apply the boundary condition at the
interface between gate and oxide and see if we get the same
result
EGE (-t
ox )

ox

)+OG =

ox

E (-t

E (-t ) = =
Eox
Eox
+
ox

=E ox

q N A X d0
=
Eox

MOS Potential in TE
E ox

E 0 (x ) =
s0

dx

MOS in TE: Potential in the oxide

M

s0

d cp0 ( x ) = -E 0 ( x )
dx

-t ox < x<0 :
x
0

E ox dx

n+

q N A X d0
ox

-t ox

dx

q N A X d0
ox

-t ox

Potential in the oxide

for

t ox
0:

o x ""

qNAX
n+
d0 ox

o x t ox
""

t ox

MOS in TE: Potential in the oxide

M O

S
s0

Potential in the oxide

0

for -t ox < x<0 :

cp 0 ( x ) = cp n+

q N A X d0
( x +t ox )
Eox

Surface Potential (Potential at the oxide/silicon interface)

s0

q N A X d0

n+

t ox

q N A X d0
n+

ox

with

Cox:::

ox

Eox
t ox

Voltage drop across the oxide

V ox , 0

t ox

n+

s0

q N A X d0
Cox

QG0
Cox

with :
G0

B0

NOTE: VOX,0 is proportional to the charge stored on each side of the oxide

q N A X do

MOS in TE: potential in the depletion

region in the silicon substrate
M O

dE 0 x
x:::

0<:x<: X
d0

p( x )

depletion region

:
x

-qN A
-q N A x
p( x
+
E 0 ( x )-E 0 (0 ) I
dx=
I dE 0 ( x ) ) E
Es
Es
0+
s
E (0+ )
=
=I
qN A x
q N A X d0 qN A x
qN A
+
( X do - x
E 0 ( x )= E 0 ( 0
=
=
Es
Es
Es
Es )
)0

q N A X d0
E 0 (0+ )=
Es

dx

MOS in TE: potential in the depletion

region in the silicon substrate
M O

Electric Field in the Depletion region

for 0z. x z. X d0 :
qN A
( X d0 - x
E 0 (x =
Es
)
)

0<:x<: X
d0

0 (0 )

d cp0 ( x ) = -E 0 ( x )
dx

charged region

:
x

d 0 ( x )=f -E 0 ( x
0

qN A
( X do -x )
Es dx
0
2
qN A x
qN A
x
dx
x dx J J
X do xf
Es 0
2
Es

x
qN A
X do f
0 O x XJ 0 O 0
Es
0
XJJ
2
qN A
x
cp 0 ( x )=0 (0
X do xEs
2
)-

cp 0 ( x )-0 (0 )=

MOS in TE: potential in the depletion

region in the silicon substrate
M O

S
Surface Potential
s0

q N A X d0

ox

n+

charged region

0 x

X d0 :

2
qN A
x
X do xEs
2

Potential in the depletion region in the substrate

for

q N A X d0
!C ox

X d0 :
0

n+

2
qN A
x
Es X do x - 2

MOS in TE: potential in the depletion

region in the silicon substrate
M O

Potential in the depletion region in the substrate

for
0

0< x< X d0 :
q N A X d0

x
n+

ox

qN A
s

X do x-

charged region

cp 0 ( X d0 )=cp p =
cp n+ Voltage drop across
the MOS structure

q N A X d0
ox

cp n+ -cp p =

qN A 2
X do
2 Es
q N A X d0
ox

qN A 2
+
X do
2 Es

Since this is the voltage

drop across the oxide

=V ox , 0

This must be the

voltage drop across
the charged region of
the silicon substrate

=V B 0

x
2

MOS in TE:
Width of the Depletion region
M O

Voltage drop across the MOS structure

n+

q N A X d0

V ox , 0 V B0

ox

qN A 2
X do
2 Es

Voltage drop across the oxide

V ox , 0 =

depletion region

q N A X d0 = oG
B
=
(Cox (C ox
ox

Voltage drop across the charged

region of the silicon substrate

qNA 2
X do
2 s

2
do

q N A X d0
ox

qNA 2 s
X d0
qN A
ox

V B0

- < n+ -< p )
0

2 s
qNA

n+

2
do

s
ox

X d0

qNA 2
X do
2 s
2 s
qNA

n+

MOS in TE:
Width of the Depletion region
X

2
2
( n+ -cp p )=0
E s X d0 - qEN
s A

2
do

-b ,/ b2 - 4ac
x=
2a

ax + bx + c = 0

ox

NOTE: Xd0 can be only positive

X do = 2

ox

ox

2
s

2
ox

2
s

2
ox

8s

q NA

qNA

n+

Es
n+

p
ox

Depletion Width:

X do =

s
ox

( .J

2 2ox
1+
q NA Es

n+

-cp p ) -1

qN

2
ox
2
s

n+

MOS under Bias

\1 Jl

Figure 3.30 MOS capacitor on a p-type substrate for one-din1ensional analysis

o charge distribution p( ), electnc ield E( L and potential ( ) or he c se of an

applied bias \

(FLATBAND) -ACCUMULATION - DEPLETION - (THRESHOLD) INVERSION

Flatband

We apply a gate to bulk voltage that is opposite to the built-in

potential. This special voltage bias is called flat-band voltage
V FB :::-cpBUILT_IN=-(cf n+.0-cp p.0 ) Flat-band Voltage

V GB

NOTICE:
For an MOS structure with
n+ poly-silicon gate and
p-type substrate this
voltage is negative

mn+

pm

V MOS

mn+

V MOS

V GB =-BUILT-IN +V MOS

cf> pm

V GB =V FB +V
MOS

The bulk metal contact is considered fixed

n+
n+,0 V GB
n+

n+,0

V GB

n+,0

p,0

if V GB V FB

V GB

p=p,0

V FB V GB

V MOS 0

Flatband

In flat-band condition (VGB=VFB) there is no internal voltage drop

across the MOS capacitor.
n+,0+V GB
The bulk metal contact
is considered fixed
<p = - 420 mV (<n+,o = 550 mV)
Thermal Equilibrium

Applying VGB = VFB shifts the gate metal contact

lower by 970 mV (=VFB)

Flatband
Since in flat-band condition
(VGB=VFB) there is no internal voltage
drop across the MOS capacitor, as a
result the electric field is zero and the
gate charge density is zero
Q G (V GB =V FB )=0