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Characterization
TJ Ta TJ Ttab
JA Jtab
Pd Pd
TJ JA Pd Ta TJ Jtab Pd Ttab
Ty
Tx
Tx Ty
xy
qtotal
?? Ty
Tx
… all we
know is total
heat input a reference number only
• Basic idea:
– “thermal resistance” is an intrinsic property of a package
• Flaws in idea:
– there is no isothermal “surface”, so you can’t define a
“case” temperature
• Plastic body (especially) has big gradients
– different leads are at different temperatures
– multiple, parallel thermal paths out of package
25°C/W
( JL)
100°C/W
What’s TL? Not 75°C !!
( JA)
metal can --
fair approximation of axial leaded device --
“isothermal” surface only two leads, heat
path fairly well defined
10% convection
wire/clip case
silicon
die attach
flag/leadframe
10%
20% 60%
circuit board
mold optional
compound/ “case”
case
wire/clip
die
silicon
attach silicon
die attach
pads/
balls
flag/leadframe
optional
20% 40% underfill
20%
application board 20% application board
10%
silicon
pads/
balls
underfill 90%
application board
Tj 800
700
TJ Tamb
JA
R1 (path down R3 (path through
600 Q total
500
to board) case top) 400 1
constant at 20 constant at 80 300
200 1 1
package
environment TL TC 100 R1 R 2 R3 R 4
0 board
psi-JL 40
15 TJ TC
30 JT
T J TL
10
R1 Q total
JL
Q total R1 R 2 20
5 1 R3
R3 R 4 10
R3 R 4
0 0 1
1 10
board
rstnc. [C/W] 100 1000 1 10
board
R1 R 2
rstnc. [C/W] 100 1000
Ta
sense
current T
Vf 25°C
0.5 V Vf 0.7 V
(1 mA typical)
10K
DUT
OR 10.7V
DUT
If V f-0.7V, then
I-1mA
10K 10K
heating heating
power power
supply supply
10.7V 10.7V
DUT OR DUT
0.18 V
0.82 V
0.64 W 0.90 W
0.70 W
0.05 V 0.15 V 0.85 V
0.95 V
Semiconductor Device Thermal Characterization
29 and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology
Which raises an interesting question:
+(1.00 V) 3A
Power
Output = 3 W
supply
-(0 V)
0.45 V 0.55 V
1.3 W 1.3 W
0.3 W
0.02 V 0.98 V
“constant” current
10K
• Heating is through Vce
• Choose a base current that switch
permits adequate heating
bias resistor
TSP=Vce
close close
switch switch to
to heat measure
V-gate
+ + TSP=Vds +
V-gate heating
for for supply
heating measure
- - -
close -
switch
to heat
TSP
supply
close close +
switch switch to
to heat measure TSP =
+ body +
V-gate
diode heating
for
supply
heating
- -
10K 10K
heating heating
power power
supply supply
10.7V 10.7V
DUT DUT
current
voltage
transient method
1 ma
power-off cooling
power-off cooling
power-off cooling
power-off cooling
Vf high-
current
high-
current
high- high-
current current
heating heating
calibrate forward voltage heating heating
Temperature
convert cooling
T volts to
25°C
temperature measured
temperatures
.5V .7V
Vf Time
current
1 ma
Time
power-off cooling
power-off cooling
power-off cooling
power-off cooling
high- high- high- high-
current current current current
heating heating heating heating
Temperature
current
transient method
voltage
Vf
1 ma calibrate forward voltage
high- @ 1mA sense current
power-off
current cooling
heating
Temperature
125°C
convert cooling
volts to T
temperature
steady state reached
Temperature
25°C
flag
edge of board
T j max Tambient
power
JA
Tj-max
steady-state max power
junction temperature
Tamb time
Semiconductor Device Thermal Characterization
49 and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology
Some initial uncertainty
power-off
cooling
heating period transient cooling period
(data taken)
Time
HEATING COOLING
starting
ambient ?
temperature
heating limited by limited to
power tester steady-state
temperature of closer to closer to
fastest data ambient Tj-max
error all points error limited to
control similar error first few points
Semiconductor Device Thermal Characterization
51 and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology
Still air vs.. moving air
80 little package
package resistance
70
60
theta-JA [C/W]
50
medium-
40
sized
package
30
20
board resistance
10 big package
0
0.1 1 10
air speed [m/s]
• Min-pad board
300
from old PPD database
250 SOT-23
TSOP-6
1" pad thetaJA (C/W)
SOT-23
200
SOD-123
SOD-123
TSOP-6(AL42)
SOT-23
150
SO-8 Micro 8
TSOP-6 SOD-123
100
SMA & Pow ermite
SMB
Dpak SMC overall linear fit is:
D2pak & TO220
50 SO-8
SOT-223 1" value = [0.51*(min-pad value) - 7]
Top Can
Top Can
0
0 100 200 300 400 500 600 700
min pad thetaJA (C/W)
T1
1 1
Q
R1
(T j T1 ) R2
(
T j T2 )
R1
This has the form of a two-variable linear equation:
heat in, Q Tj y m1 x1 m2 x2 b
R2 where: 1
m1 x1 (T j T1 )
R1
T2 b 0
1
m2 x2 (T j T2 )
R2
heat down, Q2
ambient 120. 00 Tj Ta
Ta
100. 00
Rja
80.0 0 Tc coldplate
Tjc ( ¡C)
Tj 60.0 0
Rjb
60.0 0
Tj
40.0 0 Incr easing Power, Chuck H eld
Rjc Cold
Tc 20.0 0 No P ower, Chuck T emper ature
Incr eased
0.00
coldplate -10. 00 0.00 10.0 0 20.0 0 30.0 0 40.0 0 50.0 0 60.0 0
-20. 00 Tjb (¡C)
perfectly uniform
temperature
chamber at 100°C perfectly uniform
ambient at 25°C
• Question #2:
– if the purpose of the TC scanner is to measure an
EMF, theoretically how much current has to flow in the
wire to make the correct measurement?
• Question #3:
– what do the two wires in the TC actually do, and why
do they have to be made of different materials?
100°C ΔV=0.0025V
25°C
Different materials have different Seebeck
coefficients, i.e., V/°C. So if you have two
different materials, the same temperature
gradient appearing in along both wires will
100°C
result in two different EMF’s. 25°C
ΔV=0.0037V
25°C
ΔV=0.0025V
Provides the common electrical point that
relates the EMF’s in the two wires to
each other, hence the net difference Net
ΔV=0.0012V
100°C
appears at the “open” end of the circuit.
• Question #5:
– if you really wanted to “calibrate” this thermocouple,
where would you need to apply the test conditions?
Everywhere along
TC junction
its length!
B D
A C
4
q AT
Semiconductor Device Thermal Characterization
70 and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology
Infrared Theory
Aobj (Tobj )
4 4
q obj Tencl
1
So the worse something emits, the
better it reflects, and vice-versa.
(the room)
The “target”
(the detector
itself)
(you)
(the room)
Moral:
isothermal
enclosure, high
emissivity, opaque
IR camera
to infrared
DUT
T
I 2 I1
Linear Superposition
Tnet A TA B TA C TA D
TA 2 qB 3 qC 1.2 qD
T a(T , q1 ) q1 b(T , q2 ) q2
n1 n2
T a q1 b q2
Tref5
Tj6 Tj5
Tj3 Tj2
Tref3
Tref1
Tj4 Tj1
TB
T j1 J 1A 12 1n q1
Tj2 21 J 2A 2n q2
Ta
T jn n1 n2 JnA qn
board
self-heating terms interactions
Semiconductor Device Thermal Characterization
93 and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology
power
junction
input
temperature theta matrix assembled vector
vector from simplified subsystems
T j1 JB1 BA1 12 1n q1
Tj2 21 JB 2 BA2 2n q2
Ta
T jn n1 n2 JBn BAn qn
device
resistance board
resistance
Semiconductor Device Thermal Characterization
94 and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology
visualizing theta and psi
heat in here
measurements
here are s
J1A
measurements
J1B here are s
(idle heat
source “x”)
(idle heat
BA source “y”)
xA
yA
thermal ground
Semiconductor Device Thermal Characterization
95 and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology
theta matrix doesn’t have to be square
junction one column for
temperature power input
each heat source
vector vector
T j1 JA1 12 13
Tj2 12 JA 2 23 q1
TxA x1 x2 x3 q2 one row
for each
TL1 A L1 1 L1 2 L1 3 q3
heat
TBA B1 B2 B3 source
(why is this
one row for each temperature
and not ?)
location of interest
Semiconductor Device Thermal Characterization
96 and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology
Electrical reciprocity
+
+
+
?V
-
VV
0.3
+ -
5V
-
I 0.3
2 AV
-
same
response response
here here
response same
here response
here
(s) (r)
C
airflow
A
D
J1 75 65 55 60 22 10
J2 65 71 60 55 25 11
J3 55 60 65 61 21 15
J4 60 55 61 73 18 11
rows are the 22 25 21 18 125 14
J5
response
locations J6 10 11 15 11 14 180
R1 73 65 55 59 22 10
R3 55 60 63 61 21 15
R5 20 24 14 19 95 15
B 65 63 62 63 21 12
Tamb=25
Tref5=47.0
Tj6=36.0 Tj5=49.2
Device 1
Tj3=85.5 Tj2=96.5
heated, 1.1 W
Tref3=85.5
Tref1=105.3
Tj4=91.0 Tj1=107.5
TB=96.5
j1A 75
Tj1 Tamb 107.5 25
j1A 75 j2A 65
q1 1.1
j3A 55
Tj2 Tamb 96.5 25
j2 A 65 j4A 60
q1 1.1
j5A 22
10
j6A
r1A 73
TB Tamb 96.5 25 r3A 55
BA 65
q1 1 .1 20
r5A
BA 65
j2A 71
Tamb=25
j3A 60
Tref5=53.8 j4A 55
Tj6=38.2 Tj5=55.0
j5A 25
j6A 11
r1A 65
Tj3=97.0 Tj2=110.2
r3A 60
Tref3=97.0
r5A 24
Tref1=103.0
Tj4=91.0 BA 63
Tj1=103.0
TB=100.6
Semiconductor Device Thermal Characterization
104 and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology
Device 3 heated, 1.3 W
j1A 55
Tamb=25
j2A 60
Tref5=43.2 65
j3A
Tj6=44.5 Tj5=52.3
j4A 61
j5A 21
j6A 15
Tj3=109.5 Tj2=103.0
r1A 55
Tref3=106.9
r3A 63
Tref1=96.5
Tj4=104.3 Tj1=96.5 r5A 14
BA 62
TB=105.6
j5A 18
j6A 11
Tj3=92.1 Tj2=85.5
r1A 59
Tref3=92.1
r3A 61
Tref1=89.9
Tj4=105.3 Tj1=91.0 r5A 19
BA 63
TB=94.3
j5A 125
j6A 14
Tj3=39.7 Tj2=42.5
r1A 22
Tref3=39.7
r3A 21
Tref1=40.4
Tj4=37.6 Tj1=40.4 r5A 95
BA 21
TB=39.7
j5A 14
j6A 180
Tj3=32.5 Tj2=30.5
r1A 10
Tref3=32.5
r3A 15
Tref1=30.0
Tj4=30.5 Tj1=30.0 r5A 15
BA 12
TB=31.0
Tamb=25
Actual power
Tref5=106.3 in application
Tj6=139.1 Tj5=124.7
Qj1 .4
Q j2 .4
Q j3 .4
Tj3=134.9 Tj2=140.1
Q j4 .4
Tref3=134.1
Q j5 .5
Tref1=138.8
Tj4=135.8 Tj1=140.0 Q j6 .2
TB=139.1
Isolated
device 1
Tj1 J1A q1 Ta J1A
the “system”
theta-JA
1
J1A
J1A
1
the isolated-device
n
theta-JA
1n qn TJ1 junction temperature
Ta 2 Ta’
( j1B B1a )Q 1
effective
Ta
ambient
when Q1 is
j1B Q1 B1a Q1 Ta not zero,
zero, both
both of
of these
these willwill
be
be non-zero
zero
Tj1B TB1a Ta
temperature temperature rise,
rise, board to J1 ambient to board
Semiconductor Device Thermal Characterization
117 and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology
Predicting the temperature
of high power components
• The device and system are equally
important to get right
= 37.5 + 94.6 + 25
power increasing
power
q1=0.5 W
note the “embedded” decreasing
theta-JA looks like power
264 C/W
1 1
=94.6 C =37.5 C
n
1n qn
(θJ1Aq1) junction temperature
25 C 157 C
2
TJ1
= 26.3 + 3.6 + 25
power
=26.3 C junction
25 C 54 C temperature
TJ6
100 100
80 80
60 60
40 40
20 20
0 0
J1 J2 J3 J4 J5 J6 R1 R3 R5 B J1 J2 J3 J4 J5 J6 R1 R3 R5 B
result location result location
J1 at 0.4 W J2 at 0.4 W J3 at 0.4 W J1 at 0.4 W J2 at 0.4 W J3 at 0.4 W
J4 at 0.4 W J5 at 0.5 W J6 at 0.2 W J4 at 0.4 W J5 at 0.5 W J6 at 0.2 W
180
normalized response [C/W], each source
J1 at 1 W
160 J2 at 1 W
J3 at 1 W
140
J4 at 1 W
120 J5 at 1 W
J6 at 1 W
100
80
60
40
20
0
J1 J2 J3 J4 J5 J6 R1 R3 R5 B
response location
• Utilizing symmetry
dT T
q k A k A
dx L
if we define
T
R
q
then
L
R
k A
q h A T
if we define
T
R
q
then
1
R
hA
so if and if
L 1
R and C ρc p (L A ) R and C ρc p (L A )
k A h A
then then
c pL2 L2 c pL
k h
• conduction resistance…………..……… R L
k A
• convection resistance…………...……… R 1
h A
• thermal capacitance……………...…….. C c pV
tens of seconds
mainly environmental
a second or so
convection and radiation effects
junction temperature
mainly local
application board
conduction effects
typical heating curve
for device on FR-4
board in still-air
mainly package time
materials/conduction effects
then and
2R
4R
Semiconductor Device Thermal Characterization
138 and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology
Cylindrical and spherical conduction (through
radial thickness) resistance formulas
ro 1 1
ln
ri ri ro
Half-cylinder R R Hemisphere
k L 2 k
[solid angle]
[included angle]
1 1
r
ln o ri ro
Full cylinder ri R Full sphere
R 4 k
2 k L
• L – cylinder length
where • ri – inner radius
• ro – outer radius
q
q h A T A
h T
So never mind the package resistance, the board
can only transfer a certain amount of heat to the air:
*Special thanks to Dave Billings for the idea behind this slide
1000 1.0qW
mm
A
2
h
1E-5 mmW2 °C T
100°C
PROBLEM:
No problem!
4 SOT23’s on a 1000 mm2
board, effective JA=400°C/W
SOT23
SOT23’s on a 1000 mm2
4 SOT723’s
board, JA=400°C/W,
T=100°C, power
power == 11 W
W total,
total,
0.25 W each
each
Decrease size
(but
andnot
reduce
power How many SOT723’s can you
power
dissipation)
dissipation put in that same 1000 mm2?
• Duty-cycle curves
– Normalized and non-normalized
• Linear superposition applied to time domain
2.5
R(t), Thermal Resistance [°C/W]
1.5 d=0.5
1
0.2 0.1
0.05
0.5
Single pulse
0
0.00001 0.0001 0.001 0.01 0.1 1 10
t, time (s)
10
R(t)JL [°C/W]
0.1
0.0001 0.001 0.01 0.1 1 time [s] 10 100 1000
t t t t
r (t , d ) d (1 d)*r t r (t ) r R(t , d ) d R (1 d) R t R(t ) R
d d d d
lim R(t , d ) d R
t 0
lim R(t , d ) R
t
JL=27.4°C/W
r(t)JL [normalized]
0.1
normalized transient thermal response
for axial lead rectifier
Junction-to-Lead, 1/4" lead length
0.01
0.0001 0.001 0.01 0.1 1 time [s] 10 100 1000
10
R(t)-1"
R(t)JL [°C/W]
R(t)-3/8"
R(t)-1/32"
1
0.1
0.0001 0.001 0.01 0.1 time [s] 1 10 100
10
the short-
time
response 0.1
0.0001 0.001 0.01 0.1 time [s] 1 10 100
when you
“normalize”!
1
r(t)JL [normalized]
JL-1/32"=20.0°C/W
JL-3/8"=34.9°C/W
0.1 JL-1"=54.9°C/W
0.001
0.0001 0.001 0.01 0.1 time [s] 1 10 100
R(t)JL [°C/W]
2% duty cycle
5% duty cycle
1
10% duty cycle
20% duty cycle
Same short- 50% duty cycle
time 0% 0.1
0.0001 0.001 0.01 0.1 time [s] 1 10 100
(single-pulse)
100 square-wave duty cycles
for 1" lead length
10
Different single pulse
1% duty cycle
everything
R(t)JL [°C/W]
2% duty cycle
between !! 1
5% duty cycle
10% duty cycle
20% duty cycle
50% duty cycle
0.1
0.0001 0.001 0.01 0.1 time [s] 1 10 100
a t t t
plus a equals
t t t
a
Q1 Q1
Q2
t a Q2 c
is made up of
a b c b -Q2 t
-Q1
R(t) R(t)
results in this
T3
t5-3 0.0022 s T1
t5-4 0.0002 s
Item Value unit
T2
T3 [
P1 R(t5 ) R(t5 t1 )]
[ ]
t0 0.0000 s
t6 0.0003 s
t0 t1 t2 1 t3 2 3 t4 t5 4
P2 R(t5 t 2 ) R(t5 t3 )
t4 0.0012 s
t, Time (ms)
P3 R(t5 t 4 )
P2 40 W
P3 70 W R(t)-3/8"
R(t)-1/32"
1 t1 0.0001 s
t3 0.0013 s
t3-1 0.0012 s
t3-2 0.0010 s
0.1 t5 0.0035 s
0.0001 0.001 t5-1
0.01 0.0034 s0.1 time [s] 1 10 100
t5-2 0.0032 s
t5-3 0.0022 s
t5-4 0.0002 s
t2 t1
R(t ) a t n
t1 t
R(t1 ) R(t 2 )
a n n
t1 t2 t
n n
10
interpolate
R(t)-1"
R(t)JL [°C/W]
1
R(t3) 0.82 R(t)-1/32"
R(t3-1) 0.79
R(t3-2) 0.72
R(t5) 1.36
0.1
0.0001 0.001 0.01 0.1 time [s] 1
R(t5-1) 1.34
10 100
R(t5-2) 1.30
R(t5-3) 1.08
R(t5-4) 0.32
100
T1 P1 R(t1 ) 80 0.22 17 .6 C
P(PK) Peak Power (Watts)
80 P1 P3
60
T3
T1
T2
T3 P1[ R(t5 ) R(t5 t1 )]
P2[ R(t5 t 2 ) R(t5 t3 )] P3 R(t5 t 4 )
t0 t1 t2
80 (1.36 1.34 ) 40 (1.30 1.08) 70 0.32
1 t3 2 3 t4 t5 4
t, Time (ms)
1.6 8.8 22 .4 32 .8 C
power
18
25.2W
time
802
last of 20 pulses ends 7600
Tavg
Power shifted to
average zero
(1-d) · Q
Q
Qavg= d · Q
0 0
-d·Q
time
power 7600 15200
25.2W
“average” Tj based
on global avg power
20 pulses
time
802
last of 20 pulses ends 7600
P P
t
is made up of
a a t
Q Q
t results in this t
a a
Q Q
t results in this
t
Temperature (°C)
Power input (W)
Thermal RC networks
35.3008 1.46E+00
39.637 9.20E-01
33.1212 4.16E+00
9.7581 1.14E+01
Ta Ta
1
1
R1 C1 R1 sC1
1
sC1 R1
R1 R2
R1C1 s 1 R2 C2 s 1
1 R2
R2 C2 R2 sC2 R2 C2 s 1
C1 1 1
R1 R1 R1
sC1 sC1
C2 1 R2
R2
R2 sC2 R2 C2 s 1
1
R2 1 1 R1 R2 C2 s R1 R2
R1 sC1
R1C1 R2 C2 s
2
R1C1 R2 C1 R2 C2 s 1
R2 C2 s 1 sC1 R1
R2
R2 C2 s 1
11.7747 6.03E-01
21.0538 4.13E-01
environment
35.3008 1.46E+00
39.637 9.20E-01
33.1212 4.16E+00
9.7581 1.14E+01
Ta
Ta
Ref: L. Weinberg, Network Analysis and Synthesis, McGraw Hill Book Company, Inc., 1962
t
p 2p
p – period of waveform
R(t ) Ri 1 e i
i 1
Q t – arbitrary time of interest t a jp
Fi (t ) Ri 1 e i
j 1
m t
R(t ) Ri 1 e i
i 1
p 2p
t′ – measured from edge
of power step
b – pulse turns off
a – pulse turns on m t b
R(t ) Ri 1 e i
i 1
t b jp
0 t a b t p Fi (t ) Ri 1 e i
a t b j 1
1 j 1
Utilizing the identities zj and z
j 0 1 z j 1 z 1
0 t a a t b b t p
b t p a t p b t p a t b t a t
e i
e i
e i
e i
e i
e i
Fi (t ) Ri p
Fi (t ) Ri 1 p
Fi (t ) Ri p
1 e i
1 e i
1 e i
R(t ) R1 1 e 1
R2 1 e 2
t t2 t t2
R1 1 1 2
R2 1 1 2
1 21 2 2 2
t t2 t t2
R1 2
R1 2
1 21 1 21
R1 R2 R1 R2 t2 So for small t:
R(t ) t 2 2
1 2 1 2
2 R(t ) (const) t
1.0E-1
1.0E-2
1 rung
L2
– within the silicon timescale , if surface heating is a good
model, you have to “extend” the RC network into that region
100
q2 50
0
1E-4 1E-3 1E-2 1E-1 1E+0 1E+1 1E+2 1E+3
heating time [s]
R(t) (C/W)
-0.2
10
-0.4
-0.6
1
Simlation data -0.8
R-C model
Fit Error -1
0.1 -1.2
Simulation data
1E- 1E- 1E- 0.001 0.01 0.1 1 10 100 1000
06 05 04
Time (sec)
After optimization
Q1 (amps)
+
Tj1 Tj2
-
Tpos2 Tpos1
time
Tneg2 Tneg1
Q2 (amps)
time
C7
R7
time
100 0.8
Semiconductor Device Thermal Characterization
201 and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology
80
Results from a 2-input Excel Foster model
Tj1
180.0 1.40
Tj2
160.0 q1_pow er
1.20
q2_pow er
140.0
1.00
120.0
temperature [C]
power [W]
100.0 0.80
80.0 0.60
60.0
0.40
40.0
0.20
20.0
0.0 0.00
0 1 2 3 4 5 6
tim e [s]
A cell for
keeping
track of the
overall time
=IF(Master_Time>Row_Time,Master_time-Row_time,0)
progression
of ALL
blocks.
=SUM(D1:D1_by_D4) +T_ambient
Note!
Time in this column
can be independent of
the time values in the
power input section
Apply a
Data > Table option
Temperature (C)
1.2 T_D2
Power (W)
2.5
1
2 T_D3
0.8
0.6 1.5 T_D4
0.4 1
0.2 0.5
0 0
0 0.05 0.1 0.15 0.2 0.25 0 0.05 0.1
Time (Sec) Time (Sec) 0.15 0.2 0.25 0.3
1.4 D2 3
Temperature (C)
1.2 Last
Power (W)
2.5
1
0.8 power 2
0.6 1.5
0.4 input 1
0.2 0.5
0 0
0 0.05 0.1 0.15 0.2 0.25 0 0.05 0.1
Time (Sec) Time (Sec) 0.15 0.2 0.25 0.3
1.4 D3 3
Temperature (C)
1.2
Power (W)
2.5
1
0.8 2
0.6 1.5
0.4 1
0.2 0.5
0 0
0 0.05 0.1 0.15 0.2 0.25 0 0.05 0.1
Time (Sec) Time (Sec) 0.15 0.2 0.25 0.3
1.4 D4 3
Temperature (C)
1.2
Power (W)
1 2.5
0.8 2
0.6 1.5
0.4 1
0.2 0.5
0 0
0 0.05 0.1 0.15 0.2 0.25 0 0.05 0.1
Time (Sec) Time (Sec) 0.15 0.2 0.25 0.3
Thermal Runaway
TJ Tx
Q … solving for power
Jx
power
tendency
to cool
Q
tendency
to heat device line
junction temperature
Tx TJ
device 1.6
operating
Device Power Dissipation [W]
curve
1.2
10°C/W NO
0.8
system operating
point!
0.4
25°C/W
system
40°C/W 0.0
20 40 60 80 100
system Junction Temperature [C]
50°C/W 50°C/W
100°C/W 0.2°C/W
Case A Case B
100 °C
+ 15 junction 100 °C
+ 5.02junction
50°C/W 50°C/W
75 °C
+ 10 lead 75 °C
+ 0.02lead
100°C/W 0.2°C/W
Case B
device
line
Case A
common nominal
operating point
0.5 W
junction temperature
Tx TJ Ty TR2 TR1
a
device mathematical
power “power law”
y ax
Q V I
an “exponential”
power law (base is e)
y ex
Eliminating q: kz ez
ez
at point of tangency,
slope equals height k=ez
k=ez
k=ez
k=ez
T Tx
z
z0 zTz 1 z zT
1 0 0 1 z0 zT zT
1
zT z0 1
ez nominal
“operating” system line A
points
k>e
(2 intersections)
k<e
(no intersections)
at point of
tangency, slope
k=e equals height
TR1 ln TR2 Tx
Jx1Q o
“operating” kz
points
unstable kzu e zu
stable
1 kzs e zs
zs zu
Tstable Tx z stable
Tunstable Tx z unstable
Tmax Tref
I0 It max e Itref e Q0 VRIo
† MBRS140T3
*Special acknowledgements to Dave Billings and Geoff Garcia for their contributions to this project
200
180
Heatsink (tab) temperature [degC]
160 DUT T1
140 DUT T2
DUT T3
120 DUT T4
DUT T5
100
DUT T6
80 DUT T7
DUT T8
60
DUT T9
40 DUT T10
20
0
0 2000 4000 6000 8000 10000 12000
test time [s]
Semiconductor Device Thermal Characterization
231 and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology
HTRB data - sockets without heatsinks
HTRB DUT power vs.. test time
3
2.5
DUT W1
DUT W2
2 DUT W3
DUT Power [W]
DUT W4
DUT W5
1.5
DUT W6
DUT W7
1 DUT W8
DUT W9
DUT W10
0.5
0
0 2000 4000 6000 8000 10000 12000
test time [s]
TJ THS Pd J HS
640 V MT2
-
40 kΩ
• At room temp, if IDRM is 5 uA, then Pd is about zero (≈3mW),
and TJ should thus equal chamber set point.
• At 85°C, IDRM is about 0.1-0.2mA, thus Pd is on the order of
0.1W, so depending on theta-JA, TJ could be several
degrees hotter than chamber set point (note, however, that
TJ will still be well within 1°C of heatsink temperature, THS)
• HOWEVER, at 125°C, if IDRM is 2mA, then Pd will be in
HTRB test circuit
excess of 1W. Depending on theta-JA, TJ could be 30-60°C
above chamber set point (though still within a couple of
degrees of heatsink temperature, if known).
1E-3
DUT I1
DUT I2
1E-4
DUT I3
DUT I4
DUT I5
1E-5 DUT I6
DUT I7
DUT I8
DUT I9
1E-6 current
1E-7
20 40 60 80 100 120 140 160
estimated junction temperature [°C]
1E+0
1E-1 DUT W1
DUT W2
DUT W3
DUT W4
1E-2 DUT W5
DUT W6
DUT W7
DUT W8
1E-3
DUT W9
power
1E-4
20 40 60 80 100 120 140 160
estimated junction temperature [°C]
2.5
DUT W1
2 DUT W2
DUT W3
1.5 DUT W4
Pd [W]
DUT W5
DUT W6
1
DUT W7 37°C/W
system
DUT W8 4°C/W
0.5 system
DUT W9 10°C/
W
0 system
1E-3
DUT I1
DUT I2
1E-4
DUT I3
DUT I4
DUT I5
DUT I6
1E-5
DUT I7
DUT I8
DUT I9
1E-6
1E-7
20 40 60 80 100 120 140 160
estimated junction temperature [°C]
real
runaway
device 1.6
margin
operating what you
Device Power Dissipation [W]
curve thought
1.2
was your
margin
0.8
system with
“background
25°C/W 0.4 heating” of
system other
ij Qi devices
0.0 i j
20 40 60 80 100
Junction Temperature [C]