Predictive Technology Model for Nano-CMOS
Design Exploration
Yu Cao
Department of Electrical Engineering
Arizona State University
Tempe, AZ 85287-8706, USA
Email: ycao@asu.edu
Abstract- Predictive MOSFET model is critical for early circuit
design research. In this work, a new generation of Predictive
Technology Model (PTM) is developed, covering emerging
physical effects and alternative structures. Based on physical
models and early stage silicon data, PTM of bulk and double-gate
devices are successfully generated from 130nm to 32nm
technology nodes, with effective channel length down to 13nm. By
tuning only ten primary parameters, PTM can be easily
customized to cover a wide range of process uncertainties. The
accuracy of PTM predictions is comprehensively verified with
published silicon data: the error of the current is below 10% for
both NMOS and PMOS. Furthermore, the new PTM correctly
captures process sensitivities in the nanometer regime. PTM is
available on line at http://www.eas.asu.edu/-ptm.
Keywords - technology scaling, predictive modeling, early
design exploration, FinFET, process variations
I. INTRODUCTION
CMOS will arguably be the technology of choice for IC
design toward the 10nm regime, provided that the complex
challenges arising in the nanoscale can be overcome [1].
Examples of these emerging challenges include leakage,
process variations, and reliability degradation [1]. In this
situation, advanced circuit design research must start
concurrently with future technologies, in order to identify key
design needs and develop design solutions up front. For early
circuit design, it is critical to have predictive technology
models that are reasonably accurate and correctly capture
emerging technological issues in the nanometer regime [2].
An initial effort in this area was Berkeley Predictive
Technology Model (BPTM) [2]. Based on BSIM4 [3], BPTM
empirically extracted model parameters from early stage
silicon data. Although BPTM provides reasonable model files
for technology nodes from 1 80nm to 45nm, its empirical
nature constrains the physicality of predictions. First, the
overall trend of transistor performance is not smooth through
the scaling [4]. Secondly, increasingly significant physical
correlations among parameters are not sufficiently considered.
For instance, the scaling of the threshold voltage (Vtho) not
only requires the change of channel doping (N,h), but also
impacts other physical parameters, such as mobility (j0),
saturation velocity (Vsat), etc. Insufficient modeling of these
correlations further limits the accuracy of prediction for the
sensitivities to process variations.
1-4244-0391-X/06/$20.00 ©2006 IEEE
Wei Zhao
Department of Electrical Engineering
Arizona State University
Tempe, AZ 85287, USA
Email: wei.zhao@asu.edu
In this work, a new generation of Predictive Technology
Model (PTM) is developed that overcomes these limitations
(Sec. II). New physical models are employed to correctly
capture key correlations among model parameters. In addition,
new sub-circuit is constructed to model alternative device
structures, particularly the double-gate device (FinFET).
Predictive model files are obtained for 130nm to 32nm nodes.
They are comprehensively verified with published data (Sec.
III). The new PTM supports the prediction of both nominal
and variational transistor performance with a guaranteed level
of confidence. Sec. III summarizes the results and illustrates
the impact of process variations on future nanoscale CMOS.
II. NEW PREDICTIVE METHODOLOGY
The key to a physical and efficient prediction is an
appropriate categorization of models parameters [2, 4-7]. For a
short-channel bulk or SOI transistor, compact models, such as
BSIM, are ready to serve as the prediction basis. Although
there are more than 100 parameters in a modem transistor
model, only about ten of them are critical to determine the
major behavior of a MOSFET during technology scaling. The
performance of a transistor is less sensitive to other secondary
parameters [2, 4-5]. Thus, the challenge for PTM of a bulk or
SOI device is to predict the primary parameters. This is
achieved through both physical understandings and early stage
silicon data (Sec. 2.1).
At the end of the roadmap, other alternative structures, such
as FinFET, may emerge as the technology of choice. Currently
compact models for them are not available. In this case, a sub-
circuit model is proposed for FinFET that enables circuit
simulations (Sec. 2.2). It consists of two SOI devices with
additional models to capture the uniqueness of the double-gate
structure. Then model parameters are predicted using the
similar method as that for a bulk device (Sec. 2.1).
2.1. Prediction of Primary Parameters
In this work, BSIM4 is used as the model format for PTM
of a bulk device. The primary parameters are listed in Table 1,
including effective channel length (Leff), equivalent oxide
thickness (Toxe), supply voltage (Vdd), Vtho, parasitic resistance
(Rdsw), Nch, the DIBL effect (Etao), o0, Vsat, and the body effect
(KI). Although some parameters are specific for BSIM, this
predictive methodology is general enough to be extended to
other model formats.
 TABLE 1. PRIMARY PARAMETERS IN PTM 5x1 0
' * PTM
Technology specifications Toxe, Leff, Vdd VthO, Rdsw 32nm', 18 ---------------ITRS
4xl 0
Process parameters NCh, Etao Intel
3xl 0 18845nm * IBM
TI
Physical parameters Ro, Vsat, K1 65n,m,,, Fujitsu
E
2x10 18_ Onrr.9Onm, TSMC
The first group of parameters is related to the process l3XfOnm
specifications, including Leff, Toxe, Vdd, Vtho, and Rdsw. Their z1 '30n nm
nominal values are determined by literature survey, including lxi 0 18 --. @ i 250nm-
the ITRS [1]. As long as their values are decided, the basic
0
characteristics of a new technology are specified. Figs. 1 and 2 10 30 50 70 90 110 130
show the scaling trend of Toxe, Vdd, and Vtho, from 13Onm to
32nm nodes. Each dot represents an early stage silicon data Liff (nm)
Figure 4. The prediction of channel doping.
from industrial publications [8-17]. The threshold voltage 0U2
almost remains the same, because of the concern of the
leakage control. As shown in Fig. 3, the scaling of RdSW is also 0.018- 45nm
quite slow in recent nodes due to the process limit. 0.015- 0~~
4 Ar
0.012- m 18nm
4.0- / * PTM
A25Cnm, W 0.009-
3.5- 0 13nm *1 Intel
O9nm * IBM
3.0- 0.006-
2.5- 0.003- 32nm Fujitsu
-C 2.0- / 80nm * PTM v TSMC
nnn)
0.1.uuu
/ *~ ~ 1 Intel f
.UUU

I- 1.5- 45n d 13 nm * IBM 10 30 50 70 90 110 130

9nm
1.0-
32nm
Lff (nm)
Fujitsu Figure 5. The scaling of the DIBL effect.
0.5-
v TSMC
0.0 -1
V.V
The technology specifications have a strong impact on
10 30 50 70 90 110 1 0
other process details. In particular, channel doping, N,h, can be
L.ff (nm) estimated when the expected threshold voltage is given. Based
Figure 1. The scaling of gate oxide thickness.
2.0 on the Vth model [3], Fig. 4 illustrates the trend of N,h scaling.
* 0 The values of N,h are reversed from published Vtho data [8-17].
1.6- 180nm 250nm Similarly, the trend of EtaO, which is a parameter determining
lOm
g130nm, C the Drain-Induced-Barrier-Lowering (DIBL), is extracted from
> 1.2-
90nm
9nm v Vdd
-0-- PTM
*Intel the Vth values (Fig. 5). A smaller value of EtaO leads to a
,4It/ 65n6n IBM stronger DIBL effect. These trends reflect the state-of-the-art
- 0.8- 32nm
*
TI of technology advances.
Vth Fujitsu
v TSMC The amount of channel doping, N,h, further determines
other important electrical characteristics of a transistor,
0.4-
Xt_~~~ 0 -o

especially the low field carrier mobility (j0), saturation

U.U velocity (Vsat), and the body effect (KI). As N,h increases, t0
10 30 50 70 90 110 13 0 degrades [18-19]; Vsat also depends on N,h and Leff due to the
Lff (nm) effect of velocity overshoot [20]. These correlations become
Figure 2. The scaling of Vdd and Vth. much stronger than before when transistors scale into the
500 nanometer regime. Correct modeling of them is critical for
accurate predictions of future technology, as well as the
400-
250nm
sensitivities to process variations. To account for these effects,
the following formulas are adopted in PTM [18-20]:
300-
E 180>// @PTM NMOS: po0= strain 1150 exp(- 5.34 1 -10 ) (1) Nh

130nm ITRS
ux
3 200- .9
.Onm
----------

* Intel PMOS: po0= strain 317 exp(- 1.25 10- 9+X) (2)
a
45nm ---

0 ~~~IBM (3)
5nm
V,al = Val +±O. 1 3 p F-cefkT/q (Vdd /L2ef )
ml
32nm 65nm *

100- TI
Fujitsu In Eqs. (1) and (2), a strain factor is also included to model the
v TSMC
.. impact of strained silicon on mobility enhancement. Fig. 6
10 30 50 70 90 110 130 verifies Eq. (3) with experimental data. The phenomenon of
Lff (nm) velocity overshoot has become pronounced in the nanoscale
Figure 3. The scaling of S/D parasitic resistance. and will eventually be limited by the thermal velocity [21].
 240000- 0.4 -

220000- PTM
0.3 - Symbol: DESSIS
200000- : ~ ~~~~~~~~
' tq. (-, * T.= 1Onm
180000 - t32nm * Intel 0.2 - A T = 20nm
\ IBM * T. = 30nm
160000 - 45nm
I
TI
_
G1)
0.1 - r T = 40nm
140000 - 4 Fujitsu 0)
i65nm v TSMC U-1
Toxe=2nm
120000- X,90nm 0.0 -
Lg,te=1 oonm
100000 - 250nm-
" N,h=le cm-'
-0.1 -
80000 - --8Onm 4-
bUUUU -0.2 -
0 20 40 60 80 100 120 140 -1.2 -0.8 -0.4 0.0 0.4
Liff (nm) Back gate voltage VGb (V)
Figure 6. The prediction of the saturation velocity. Figure 8. The coupling between Vthf and VGb in a FinFET.
Combining these steps together, the primary model the body effect in a bulk device; instead of the body contact,
parameters, (e.g., Leff, Toxe, EtaO, Vtho, Rdsw and subsequently VGb affects Vthf through the capacitance partition between the
estimated ones) can be extrapolated toward future technology gate oxide capacitance (Coxb and Coxf) and the silicon body
generations. Furthermore, their values can be adjusted in order capacitance (Csi) in a FinFET device:
to cover a range of process uncertainties, e.g., from one
company's to another one's, or due to process variations. The aV,hf /IVGb = (Ci Coxb)/lCox (4)
rest of model parameters are secondary ones. They have little This effect is significant in a FinFET device, since a thin
impact on transistor performance. Thus, for early predictions, silicon body thickness (Tsi), i.e., a relatively large Csi, is
it is reasonable to leave them unchanged from previous preferred to suppress the short-channel effect [22-23, 25]. This
generations. Finally, the parameters for CV characteristics are physical relationship is incorporated in the sub-circuit model.
scaled based on analytical models [3]. They are functions of It accurately predicts the electrical behavior, as compared to
the geometry and doping. TCAD simulations (Fig. 8) [25]. Based on this equivalent
2.2. PTMforFinFET circuit model, PTM for a FinFET device is developed,
FinFET, a vertical double-gate structure, is regarded as a
following the predictive methodology in Sec. 2.1.
promising alternative device for the nanoscale design [1, 22]. III. EVALUATION OF PTM
Fig. 7 (left) shows a three dimensional view of a FinFET.
Extensive research has been conducted to develop the 3.1. Verification ofPredictions
fabrication process and understand the underlying physics [22- The new generation of PTM has provided model files for
23]. Yet a compact model for FinFET, such as the BSIM 130nm to 32nm technology generations. Table 2 summarizes
model for a bulk CMOS, is not available for the purposes of the major characteristics of PTM predictions, for both bulk
circuit simulation and technology prediction. Currently early and FinFET devices (NMOS only). The full model files are
design research with FinFET has to resort to the TCAD available on line at http://www.eas.asu.edu/ptm.
simulators, which is computationally expensive and limits the
design flexibility. To overcome these barriers, an equivalent To verify the accuracy and flexibility of PTM, more than
sub-circuit model for a FinFET device is proposed (Fig. 7). thirty sets of IV data at room temperature are collected from
This circuit model consists of two fully depleted SOI devices publications. Using the published values for technology
for the front and back transistors, respectively. BSIM SOI is specifications (i.e., Leff, Toxe, Vtho, RdSw, and Vdd), process and
used as the model for each device, such that this sub-circuit is physical parameters (Table 1) are calculated to generate
compatible with standard circuit simulators (e.g., SPICE) [24]. corresponding PTM model files. Then predicted I-V
characteristics are compared to published data for the
The unique property of a FinFET device from a traditional verification. Figs. 9 illustrates an example at 45nm [11] node.
SOI transistor is the electrical coupling between the front and
back transistors. Specifically, the threshold voltage of the front TABLE II. SUMMARY OF PTM
transistor (Vthf) is governed by not only the process conditions,
but also the back gate voltage VGb. Such an effect is similar to Tech. node (nm) f 130 j 90 [ 65 45 32 132 (FinFET)
Back gate Gb Gb Leff (nm) 50 35 25 18 13 13
Tox (nm) 1.5 1.2 1.0 0.9 0.8 0.8
Vdd (V) 1.3 1.2 1.1 1.0 0.9 0.9
X * ff }DS
Vth (V) 0.20 0.20 0.20 0.20 0.20 0.20
Rd,w (Q/tm) 180 170 160 155 150 400
Front gate Gf Gf Ion (WA/tm) 970 1100 1175 1190 1200 1400
Ioff (nA/ptm) 30 50 70 120 300 240
Figure 7. The sub-circuit model of a FinFET.
 E~ 1000'-

~~~~~~8Onm 150

-0 800 0ioo

250~~~~~~~~~~~~n'r50
600

500
10 30 7'0 9'0 110 130

Vds(V) Liff (nm)

-r-
0.01 NMOS: Le,ff = 25nm Figure 10. The prediction of the active and leakage current.

PMOS: Leff=35nm IV 5- 4

4-
3

3-
.03 .P04T02.M
1
E-4
~ ~ ~ ~ >2

9.TepeitoEo-5cre
Elln

eal6h
moE-

le-hn7o
Edito
10 30 50 70 90 110 130

Liff (nm)
Figure 1. The prediction of the speed and energy.

wieiague ofThproessicondionnoVuvs, Laf aslowtashlnnmog4] leakage (loff) is shown in Fig. 0. As Ion increases at a
current

TE xcellent pgre dictbtio seroen the iedp pu l se tabiit

and a
constant rate during the scaling, 'off goes up exponentially and
becomes a grand design challenge. As compared to BPTM, the
new PTM yields a smooth prediction over various technology

preetM acsolidhbasise vrforcarlyodsigOexplloration Itro

poroies generations, as a result of physical consideration of primary
parameters. Furthermore, Fig. 11I shows the scaling of two
deignIpersctionstie nnsmaller While Figs4. tuingstnlt then important performance metrics: CVdd/lon, which represents the
sciali gorra parameters,P
M c nb froml
cu t hmied techologya intrinsic delay, and CVdd2, which is the switching energy per
pierspetie, ofis 10-11s furdtherstransLaesf design4 transistor. Both metrics exhibit a smooth and constant scaling
rate toward 32nm node. Note that these results do not include

the impact of alternative materials, such as the strained silicon,

metal gate, etc. PTM plans to extend the effort to these effects
dspac e. s te nscalnefm current- (ilust a the
in the next release. Overall, these predictions match the

expectations by ITRS [1].

TABLE III. COMPREHENSIVE VERIFICATIONS OF PTM PREDICTIONS

Data source I [2131~41516 ~7I~8I9 [10111112113114 [15116117

Leff (nm) 21 17 30 32 32 35 42 42 49 49 60 80 63 70 112 126 112
Toxe (nm) 1.85 1.85 1.9 2.05 1.85 2.05 2.4 2.15 2.15 2.35 3.6 4.3 3.3 3.4 4 4.3 5.0
Vdd (V) 1 1 1 1.2 1 1.2 1.2 1.4 1.3 1.2 1.5 1.8 1.2 1.5 1.5 1.8 1.8
Vth (V) 0.28 0.36 0.30 0.29 0.25 0.26 0.26 0.26 0.23 0.26 0.32 0.42 0.35 0.40 0.36 0.37 0.38
Rd, (Q/~tm) 280 250 220 200 185 175 160 150 200 195 260 290 330 225 330 310 480
lo. (~.iA~tm) 1940 8451820110901100511160 1000 J1120 ]~1155 [930182017801586] 750 615 J690 ]~605
10. (Prediction) j950 [855 J845111871104511210 1995 1120511145 [970 J8551775 555 ]755 [570 16901580
loff (nA/.tm) 1150 80 50 T80 1601130 70 10 T130 [100 230 0.6 5 1 1 06
loff (Prediction) 1120 20140150 11301100 301 101140 [60 13010.61 4 1 [ 1 {0.
Error of Io. (0%) ] I[I1319 f4]4 [11~81-1 [4] 4I 11511 [7 014

Liff (nm)
Figure 12. The impact of variations on the active current.
Besides the arising concern in leakage, process variation is
another important physical factor that results in design
challenges [1]. Similar or larger amount of process variations
are expected at future technology nodes [1]. Worse more, the
sensitivity of transistor performance on process variations will
become more significant as CMOS technology scales into the
nanometer regime, particularly because of the phenomenon of
velocity overshoot (Eq. (3)) and the scaling of Vdd. Fig. 12
illustrates the importance of these effects during technology
scaling, assuming a constant amount of variation in Leff or N,h.
Without considering DIBL and velocity overshoot, Ion is
relative insensitive to Leff variation because of velocity
saturation in a nanoscale transistor. Due to DIBL, -20% Leff
variation will result in approximate 18% higher Ion. An
additional amount of 26% Ion variation can be observed if
velocity overshoot is included (Fig. 12). Similar results are
observed from the random fluctuation of N,h. Therefore, not
only the amount of variations matters to a nanoscale design,
but also the sensitivity to variations. It is critical to include
these physical models in prediction, in order to provide correct
guidance to robust design explorations.
IV. CONCLUSION
A new generation of PTM is developed for 130nm to 32nm
technology nodes, for both bulk and FinFET devices. The new
predictive methodology has sufficient physicality and
scalability over a wide range of process and design conditions.
Excellent predictions have been verified for both nominal and
variational characteristics. The new PTM demonstrates a
significant design benefit from technology scaling. PTM
facilitates early design research and supports joint technology-
design exploration for optimal nanoscale integration. Model
files are available at http://www.eas.asu.edu/-ptm.
ACKNOWLEDGMENT
The authors would like to thank the device group at the
University of California, Berkeley for valuable discussions to
this project. This research is jointly supported by the Center
for Circuit and System Solutions (C2S2) and the Materials,
Structures and Devices Center (MSD) in the MARCO Focus
Center Research Program.
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