Verilog Code

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SIMULATION LAB
EXPERIMENT: 1
AIM:
LOGIC GATES
To design all the logic gates using dataflow modeling style and verify the
functionalities along with their synthesis and simulation reports.

TOOLS USED: Xilinx 9.2i Hardware Tool.
DESCRIPTION OF THE MODULE:
NOT GATE: Not is a unary operator. It is also called as an Inverter .The output is the
complement of the input.
AND GATE: The output of the AND gate is logic one only when all the inputs are equal
to logic one .An N-input and gate has N inputs and 1 output.
OR GATE: Or gate output is logic one if any one of the inputs to the gate is logic one.
N-input or gate has N inputs and 1output.
NAND GATE: NAND gate output is logic 1 when any one of the input is logic 0.An Ninput NAND gate has N inputs and one output. NAND gate is identical to and gate
connected to an inverter.
NOR GATE: NOR gate is nothing but a combination of OR gate and INVERTER .NOR
gate output is logic one only when all the inputs are equal to logic zero. An N- input
NOR gate is having N inputs and one output.
XOR GATE: The output of XOR gate is logic zero when all the inputs are same.
XNOR GATE: The output of XNOR gate is logic one only when both the inputs are at
logic one. XNOR gate is nothing but the XOR gate followed by an INVERTER.
TRUTH TABLE:
a b Y[0] Y[1]
Y[2] Y[3]
(not) (and) (or)
Y[4]
Y[5]
Y[6]
(nand) (nor) (xor) (xnor)
0 0
0 1
1 0
1 1
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VERILOG CODE:
LOGIC GATES USING DATAFLOW MODELING STYLE
`resetall
`timescale 1ns / 1ps
module logicgate_df(a, b, y);
input a,b;
// input declarations
output [0:6]y;
//output declarations
wire a,b;
//input as wires
assign y[0] = ~a;
//not gate
assign y[1] = a&b;
//and gate
assign y[2] = a|b;
//or gate
assign y[3] = ~(a&b);
//nand gate
assign y[4] = ~(a|b);
//nor gate
assign y[5] = a^b;
//xor gate
assign y[6] = ~(a^b);
//xnor gate
endmodule
LOGIC GATES TEST BENCH
`resetall
`timescale 1ns/1ps
module logicgate_df_tb_v;
// Inputs
reg a;
reg b;
// Outputs
wire [0:6] y;
// Instantiate the Unit Under Test (UUT)
logicgate_df uut (
.a(a),
.b(b),
.y(y)
);
initial
begin
a = 0; b = 0;
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#10 a = 0; b = 1;
#10 a = 1; b = 0;
#10 a = 1; b = 1;
end
initial
begin
#50 $finish;
end
endmodule
SYNTHESIS RESULTS:
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SIMULATION RESULTS:
CONCLUSION:
Basic logic gates NOT, AND, OR, NOR, NAND, XOR, XNOR are designed in dataflow,
behavioral models and outputs are verified using test bench.
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EXPERIMENT: 2
ADDERS
2.1. HALF ADDER
AIM: To design a half adder along with a verilog code in the dataflow model and verify
its functionality and check its simulation report.
TOOLS USED:
Xilinx 9.2i Hardware Tool

A combinational circuit that performs the addition of two bits is called half adder.The
half adder operation needs two binary inputs (augends and addend bits)and two binary
outputs (sum and carry). The sum can range from 0 to 2 which require two bits to
express. The lower order bit may be named as half sum and the higher order bit may be
named as carry.
BLOCK DIAGRAM:
TRUTH TABLE:
a
carry
Sum
a, b are inputs and carry, sum are outputs

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VERILOG CODE:
HALF ADDER USING DATAFLOW MODELING STYLE
`resetall
`timescale 1ns/1ps
module halfadder(a, b, sum, carry);
input a;
input b;
output sum;
output carry;
wire a,b;
assign sum= a^b;
assign carry=a&b;
endmodule
HALF ADDER TEST BENCH
`resetall
`timescale 1ns/1ps
module halfadder_bh_tb_v;
// Inputs
reg a;
reg b;
// Outputs
wire sum;
wire carry;
halfadder_beh uut (
.a(a),
.b(b),
.sum(sum),
.carry(carry)
);
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initial begin
// Initialize Inputs
a = 0;
b = 0;
#20 a=0; b=1;
#20 a=1; b=0;
#20 a=1; b=1;
end
initial
begin
#100 $finish;
end
endmodule
SYNTHESIS RESULTS:
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SIMULATION RESULTS:
CONCLUSION:
HALF ADDER is designed in behavioral and dataflow styles and output is verified
through a test bench.
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2.2 FULL ADDER
AIM: To design a FULL ADDER along with a verilog code in behavioral and dataflow
the two models and verify its functionality and check its simulation report.
TOOLS USED: Xilinx 9.2i Hardware Tool
The FULL ADDER is a combinational circuit that performs the arithmetic sum of three
input bits. It consists of three inputs and two outputs. A FULL ADDER can also be
implemented using two HALF ADDERS and one OR gate.
BLOCK DIAGRAM:
TRUTH TABLE:
A
Sum
Carry
Where a, b, cin are the inputs and sum, carry are outputs
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VERILOG CODE:
FULL ADDER USING DATAFLOW MODELING STYLE
`resetall
`timescale 1ns/1ps
module fulladder_dt(a, b, c, sum, carry);
input a;
input b;
input c;
output sum;
output carry;
wire a,b;
assign sum=a^b^c;
assign carry=(a&b)|(b&c)|(c&a);
endmodule
FULL ADDER TEST BENCH

`resetall
`timescale 1ns/1ps
module fulladder_beh_tb_v;
// Inputs
reg a;
reg b;
reg c;
// Outputs
wire sum;
wire carry;
fulladder_beh uut (
.a(a),
.b(b),
.c(c),
.sum(sum),
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.carry(carry)
);
initial begin
a=0; b=0;c =0;
#20 a=0; b=0; c=1;
#20 a=0; b=1; c=0;
#20 a=0; b=1; c=1;
#20 a=1; b=0; c=0;
#20 a=1; b=0; c=1;
#20 a=1; b=1; c=0;
#20 a=1; b=1; c=1;
end
initial
begin
#220 $finish;
end
endmodule
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SYNTHESIS RESULTS:
SIMULATION RESULTS:
CONCLUSION:
FULL ADDER is designed in behavioral and dataflow styles and output is verified
through a test bench.
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4-BIT BINARY PARALLEL ADDER
AIM: To design a 4-BIT BINARY PARALLEL ADDER in the behavioral model and
verify its functionality and check its simulation report.
TOOLS USED:Xilinx 9.2i Hardware Tool
DESCRIPTION OF THE MODULE: 4 bit binary parallel adder adds four bit binary
numbers. The binary parallel adder is a digital function that produces the arithmetic sum
of two binary numbers in parallel. It consists of full adders connected in cascade, with the
output carry of one full adder connected to the input carry of the next full adder.
BLOCK DIAGRAM:
A[3]
Co
B[3]
A[2]
B[2]
A[1]
B[1]
A[0] B[0] Ci
FULL
ADDER
FULL
ADDER
FULL
ADDER
FULL
ADDER
S[3]
S[2]
S[1]
S[0]
S[3]
S[2]
S[1]
13
S[0]
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TRUTH TABLE:
S
Co
1
1
0001
0011
0
0
0100
0101
0110
0111
0100 0100
1000
1001
0101 0101
1010
1011
0110 0110
1100
1101
0111 0111
1110
1111
1000 1000
0000
0001
1001 1001
0010
0011
1010 1010
0100
0101
1011 1011
0110
0111
1100 1100
1000
1001
1101 1101
1010
1011
1110 1110
1100
1101
1111 1111
1110
1111
Co Ci
Ci
0000 0000
0000
0001 0001
0010
0010 0010
0011 0011
Where a,b,cin are the inputs and sum,carry are outputs

VERILOG CODE:
4-BIT BINARY PARALLEL ADDER USING BEHAVIORAL MODELING

`resetall
`timescale 1ns/1ps
module bit4pladbh(a,b,ci,s,co) ;
input [0:3]a;
input [0:3]b;
input ci;
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output [0:3]s;
output co;
wire [0:3]a;
wire [0:3]b;
wire ci;
reg [0:3]s;
reg co;
always@(a or b or ci)
begin
if(ci==1'b0)
begin
case({a,b})
8'b00000000: begin s=4'b0000; co=1'b0;end
8'b00010001: begin s=4'b0010; co=1'b0;end
8'b00100010: begin s=4'b0100; co=1'b0;end
8'b00110011: begin s=4'b0110; co=1'b0;end
8'b01000100: begin s=4'b1000; co=1'b0;end
8'b01010101: begin s=4'b1010; co=1'b0;end
8'b01100110: begin s=4'b1100; co=1'b0;end
8'b01110111: begin s=4'b1110; co=1'b0;end
8'b10001000: begin s=4'b0000; co=1'b1;end
8'b10011001: begin s=4'b0010; co=1'b1;end
8'b10101010: begin s=4'b0100; co=1'b1;end
8'b10111011: begin s=4'b0110; co=1'b1;end
8'b11001100: begin s=4'b1000; co=1'b1;end
8'b11011101: begin s=4'b1010; co=1'b1;end
8'b11101110: begin s=4'b1100; co=1'b1;end
8'b11111111: begin s=4'b1110; co=1'b1;end
endcase
end
else
begin
case({a,b})
8'b00000000: begin s=4'b0001; co=1'b0;end
8'b00010001: begin s=4'b0011; co=1'b0;end
8'b00100010: begin s=4'b0101; co=1'b0;end
8'b00110011: begin s=4'b0111; co=1'b0;end
8'b01000100: begin s=4'b1001; co=1'b0;end
8'b01010101: begin s=4'b1011; co=1'b0;end
8'b01100110: begin s=4'b1101; co=1'b0;end
8'b01110111: begin s=4'b1111; co=1'b0;end
8'b10001000: begin s=4'b0001; co=1'b1;end
8'b10011001: begin s=4'b0011; co=1'b1;end
8'b10101010: begin s=4'b0101; co=1'b1;end
8'b10111011: begin s=4'b0111; co=1'b1;end
8'b11001100: begin s=4'b1001; co=1'b1;end
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8'b11011101: begin s=4'b1011; co=1'b1;end

8'b11101110: begin s=4'b1101; co=1'b1;end
8'b11111111: begin s=4'b1111; co=1'b1;end
endcase
end
end
endmodule
BIT 4 BINARY PARALLEL ADDER TEST BENCH
`resetall
`timescale 1ns/1ps
module bit4plabh_tb_v;
// Inputs
reg [0:3] a;
reg [0:3] b;
reg ci;
// Outputs
wire [0:3] s;
wire co;
bit4pladbh uut (
.a(a),
.b(b),
.ci(ci),
.s(s),
.co(co)
);
initial
begin
#5
#5
#5
#5
#5
#5
#5
#5
#5
#5
#5
a = 4'b0000;
a = 4'b0001;
a = 4'b0010;
a = 4'b0011;
a = 4'b0100;
a = 4'b0101;
a = 4'b0110;
a = 4'b0111;
a = 4'b1000;
a = 4'b1001;
a = 4'b1010;
a = 4'b1011;
b=4'b0000;
b=4'b0001;
b=4'b0010;
b=4'b0011;
b=4'b0100;
b=4'b0101;
b=4'b0110;
b=4'b0111;
b=4'b1000;
b=4'b1001;
b=4'b1010;
b=4'b1011;
ci=1'b0;
ci=1'b0;
ci=1'b0;
ci=1'b0;
ci=1'b0;
ci=1'b0;
ci=1'b0;
ci=1'b0;
ci=1'b0;
ci=1'b0;
ci=1'b0;
ci=1'b0;
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#5
a = 4'b1100;
#5
a = 4'b1101;
#5
a = 4'b1110;
#5
a = 4'b1111;
#5
a = 4'b0000;
#5
a = 4'b0001;
#5
a = 4'b0010;
#5
a = 4'b0011;
#5
a = 4'b0100;
#5
a = 4'b0101;
#5
a = 4'b0110;
#5
a = 4'b0111;
#5
a = 4'b1000;
#5
a = 4'b1001;
#5
a = 4'b1010;
#5
a = 4'b1011;
#5
a = 4'b1100;
#5
a = 4'b1101;
#5
a = 4'b1110;
#5
a = 4'b1111;
end
initial
begin
#200 $finish;
end
SIMULATION LAB
b=4'b1100;
b=4'b1101;
b=4'b1110;
b=4'b1111;
b=4'b0000;
b=4'b0001;
b=4'b0010;
b=4'b0011;
b=4'b0100;
b=4'b0101;
b=4'b0110;
b=4'b0111;
b=4'b1000;
b=4'b1001;
b=4'b1010;
b=4'b1011;
b=4'b1100;
b=4'b1101;
b=4'b1110;
b=4'b1111;
ci=1'b0;
ci=1'b0;
ci=1'b0;
ci=1'b0;
ci=1'b1;
ci=1'b1;
ci=1'b1;
ci=1'b1;
ci=1'b1;
ci=1'b1;
ci=1'b1;
ci=1'b1;
ci=1'b1;
ci=1'b1;
ci=1'b1;
ci=1'b1;
ci=1'b1;
ci=1'b0;
ci=1'b1;
ci=1'b1;
endmodule
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SYNTHESIS RESULTS:
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SIMULATION RESULTS:
CONCLUSION:
4 BIT BINARY PARALLEL ADDER is designed in behavioral style and output is

verified through a test bench.
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EXPERIMENT: 4
DECODERS
4.1---- 2 TO 4 LINE DECODER

AIM: To design a 2x4 decoder and to write its verilog code in dataflow, behavioral
models, verify the functionality and its output in the simulation report
A decoder is a combinational circuit that converts binary information from n input lines
to a maximum of
unique output lines. The purpose of decoder is to generate
( or
less) minterms of n input variables. A 2 to 4 decoder generates all the minterms of two
input variables. Exactly one of the output lines will be one for each combination of values
of input variables.
BLOCK DIAGRAM
TRUTH TABLE:
a b D0 D1 D2 D3
0 0 1
0 1 0
1 0 0
1 1 0
Here a,b are two inputs and D0,D1,D2,D3 denote the outputs of the decoder which
implies minterms of two input variables.
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VERILOG CODE:
2X4 DECODER USING DATA FLOW MODELING STYLE
`resetall
`timescale 1ns/1ps
module decoder24df(a, b, y);
input a;
input b;
output [0:3] y;
wire a,b;
assign y[0]=(~a) & (~b);
assign y[1]=(~a)& (b);
assign y[2]=(a) & (~b);
assign y[3]= a & b;
endmodule
2 TO 4 LINE DECODER TEST BENCH:
`resetall
`timescale 1ns/1ps
module decoder24_tb_v;
// Inputs
reg a;
reg b;
// Outputs
wire [0:3] y;
decoder24df uut (
.a(a),
.b(b),
.y(y)
);
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initial begin
a=0;b=0;
#10 a=0; b=1;
#10 a=1; b=0;
#10 a=1; b=1;
end
initial
begin
#60 $finish;
end
endmodule
SYNTHESIS RESULTS:
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SIMULATION RESULTS:
CONCLUSION: 2 to 4 decoder has been designed using behavioral, dataflow models

are verified using Test Bench.
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4.2-----3X8 LINE DECODER

AIM: To design a 3*8 decoder and to write its verilog code in dataflow, behavioral
models, verify the functionality and its out put in the simulation report
A Decoder is a multiple-input ,multiple output logic circuits and converts the coded
input into coded outputs ,the input and output codes are different. The input has fewer
bits than the output code. In 3 to 8 decoder 3 inputs are decoded into 8 outputs.
BLOCK DIAGRAM:
TRUTH TABLE:
a b c D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
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Here a,b,c are the inputs and D0 to D7 are the outputs.
3TO8 LINE DECODER USING DATA FLOW MODELING STYLE

`resetall
`timescale 1ns/1ps
module dec38data (a,b,c,dout);
input a,b,c;
output [0:7]dout;
assign dout[0]=(~a)&(~b)&(~c);
assign dout[1]=(~a)&(~b)&c;
assign dout[2]=(~a)&b&(~c);
assign dout[3]=(~a)&b&c;
assign dout[4]=a&(~b)&(~c);
assign dout[5]=a&(~b)&c;
assign dout[6]=a&b&(~c);
assign dout[7]=a&b&c;
endmodule
3 TO 8 DECODER USING BEHAVIORAL MODELING STYLE

`resetall
`timescale 1ns/1ps
module decoder38beh(a, b, c, y);
input a;
input b;
input c;
output [0:7] y;
reg [0:7]y;
//
wire a,b,c;
always@(a or b or c)
begin
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case({a,b,c})
3'b000:begin y=8'b10000000; end
3'b001:begin y=8'b01000000; end
3'b010:begin y=8'b00100000; end
3'b011:begin y=8'b00010000; end
3'b100:begin y=8'b00001000; end
3'b101:begin y=8'b00000100; end
3'b110:begin y=8'b00000010; end
3'b111:begin y=8'b00000001; end
default :begin y=8'b00000000; end
endcase
end
endmodule
3 TO 8 LINE DECODER TEST BENCH
`resetall
`timescale 1ns/1ps
module decoder38beh_tb_v;
// Inputs
reg a;
reg b;
reg c;
// Outputs
wire [0:7] y;
decoder38beh uut (
.a(a),
.b(b),
.c(c),
.y(y)
);
initial
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begin
a =0;b=0;c=0;
#10 a=0; b=0; c=1;
#10 a=0; b=1; c=0;
#10 a=0; b=1; c=1;
#10 a=1; b=0; c=0;
#10 a=1; b=0; c=1;
#10 a=1; b=1; c=0;
#10 a=1; b=1; c=1;
end
initial
begin
#100 $finish;
end
endmodule
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SYNTHESIS RESULTS:
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SIMULATION RESULTS:
CONCLUSION:3 to 8 line decoder has been designed using different modeling styles
and is verified using the Test Bench.
EXPERIMENT: 5
ENCODERS
5.1------4: 2 LINE ENCODER
AIM: To design a 4:2 line encoder using behavioral and data flow modeling styles and
verified using the test bench
TOOLS USED:
Xilinx 9.2i Hardware Tool.

An encoder is a digital circuit that performs the inverse operation of the decoder. It has
inputs and n outputs.
BLOCK DIAGRAM:
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TRUTH TABLE:
din[0] din[0] din[0] din[0] a b

1
0 0
0 1
1 0
1 1
Here din[0],din[1],din[2],din[3] are the inputs and the a,b are the outputs.
VERILOG CODE:
4 TO 2 LINE ENCODER USING BEHAVIORAL MODEL
`resetall
`timescale 1ns/1ps
module encoder42beh(din, a, b);
input [0:3] din;
output a;
output b;
reg a;
reg b;
always@(din)
begin
case({din})
4'b1000:begin a=1'b0; b=1'b0; end
4'b0100:begin a=1'b0; b=1'b1; end
4'b0010:begin a=1'b1; b=1'b0; end
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4'b0001:begin a=1'b1; b=1'b1; end

endcase
end
endmodule
4TO2 LINE ENCODER USING DATAFLOW MODELING STYLE:

`resetall
`timescale 1ns/1ps
module encoder42data(din,a,b) ;
input [0:3]din;
output a,b;
assign a=(din[2])|(din[3]);
assign b=(din[1])|(din[3]);
endmodule
4TO 2 LINE ENCODER TEST BENCH

`resetall
`timescale 1ns/1ps
module encoder42beh_tb_v;
// Inputs
reg [0:3] din;
// Outputs
wire a;
wire b;
encoder42beh uut (
.din(din),
.a(a),
.b(b)
);
initial
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begin
din=4'b1000;
#10 din=4'b0100;
#10 din=4'b0010;
#10 din=4'b0001;
end
initial
begin
#50 $finish;
end
endmodule
SYNTHESIS RESULTS:
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SIMULATION RESULTS:
CONCLUSION:
A 2 to 4 line encoder has been designed using different modeling styles and is verified
using test bench.
5.2---8 : 3 LINE ENCODER
AIM: To design a 8 : 3 line encoder using behavioral and data flow modeling styles and
verified using the test bench.
TOOLS USED:

An encoder is a digital circuit that performs the inverse operation of the decoder. It has
inputs and n outputs.
BLOCK DIAGRAM:
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TRUTH TABLE:
din0 din1 din2 din3 din4 din5 din6 din7 a b c

1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Where din0 to din7 are inputs and a,b,c are outputs.

VERILOG CODE:
8 TO 3 ENCODER USING DATAFLOW MODELING STYLE
`resetall
`timescale 1ns/1ps
module encoder83df(din, a, b, c);
input [0:7] din;
output a;
output b;
output c;
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assign a=din[4] | din[5] | din[6] | din[7];

assign b=din[2] | din[3] | din[6] | din[7];
assign c=din[2] | din[4] | din[6] | din[7];
endmodule
8 TO 3 ENCODER USING BEHAVIORAL MODELING STYLE

`resetall
`timescale 1ns/1ps
module encodr83bh (din,a,b,c);
input [0:7]din;
output a,b,c;
reg a,b,c;
always@(din)
begin
case(din)
8'b10000000:begin a=1'b0;b=1'b0,c=1'b0;end
8'b01000000:begin a=1'b0;b=1'b0;c=1'b1;end
default
:begin a=1'bz;b=1'bz;c= 1'b1;end
endcase
end
endmodule
8 TO 3 LINE ENCODER TEST BENCH:
`resetall
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`timescale 1ns/1ps
module encoder83df_tb_v;
// Inputs
reg [0:7] din;
// Outputs
wire a;
wire b;
wire c;
encoder83df uut (
.din(din),
.a(a),
.b(b),
.c(c)
);
initial
begin
din=8'b10000000;
#10 din=8'b01000000;
#10 din=8'b00100000;
#10 din=8'b00010000;
#10 din=8'b00001000;
#10 din=8'b00000100;
#10 din=8'b00000010;
#10 din=8'b00000001;
end
initial
begin
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#100 $finish;
end
endmodule
SYNTHESIS RESULTS:
SIMULATION RESULTS:
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CONCLUSION:
8 to 3 line encoder has been designed using behavioral and data flow modeling styles
and verified using the test bench.
EXPERIMENT: 6
MULTIPLEXER
6.1---4:1 MULTIPLEXER
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AIM: To design a 4:1 multiplexer using behavioral, dataflow models and verify its
functionality using the test bench.
A multiplexer has a group of data inputs and a group of control inputs. It is also called as
data selector. The control inputs are used to select one of the data inputs and connect it to
the output terminal. A 4:1 mutliplexer has four inputs ,2 selection line and 1 output.
BLOCK DIAGRAM:
TRUTH TABLE:
S1 S0 Y
0
din[0]
din[1]
din[2]
din[3]
VERILOG CODE:
4:1 MUX USING DATA FLOW MODELING STYLE:
`resetall
`timescale 1ns/1ps
module mux41data (din,s,y);
input [0:3] din;
input[0:1]s;
output out;
assign out=din[s];
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endmodule
4:1 MUX USING BEHAVIORAL MODELING STYLE:
`resetall
`timescale 1ns/1ps
module mux42beh(din, s0, s1, y);
input [0:3] din;
input s0;
input s1;
output y;
reg y;
wire s0,s1;
always@(s0 or s1)
begin
case({s0,s1})
2'b00:y=din[0];
2'b01:y=din[1];
2'b10:y=din[2];
2'b11:y=din[3];
default:y=1'b1;
endcase
end
endmodule
4:1 MUX TEST BENCH:
`resetall
`timescale 1ns/1ps
module mux42beh_tb_v;
// Inputs
reg [0:3] din;
reg s0;
reg s1;
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// Outputs
wire y;
mux42beh uut (
.din(din),
.s0(s0),
.s1(s1),
.y(y)
);
initial
begin
din=4'b0011;
s0=1'b0; s1=1'b0;
#5 s0=1'b0; s1=1'b1;
#5 s0=1'b1; s1=1'b0;
#5 s0=1'b1; s1=1'b1;
end
initial
begin
#50 $finish;
end
endmodule
SYNTHESIS RESULTS:
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SIMULATION RESULTS:
CONCLUSION: A 4:1 multiplexer is designed using behavioral, dataflow models are

verified using test bench.
6.2---8:1 MULTIPLEXER
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AIM: To design a 8:1 multiplexer using behavioral ,dataflow models and verify its
functionality using the test bench.
TOOLS USED:

A multiplexer has a group of data inputs and a group of control inputs. It is also called as
data selector. The control inputs are used to select one of the data inputs and connect it to
the output terminal. A 8:1 mux has eight inputs ,3 selection lines and 1 output.
BLOCK DIAGRAM:
TRUTH TABLE:
S0
S1
S2
Y[0]
Y[1]
Y[2]
Y[3]
Y[4]
Y[5]
Y[6]
Y[7]
Where S0,S1,S2 are inputs and Y is output
VERILOG CODE:
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8:1 MUX USING DATA FLOW MODEL

`resetall
`timescale 1ns/1ps
module mux81data1(s,din,y) ;
input [0:2]s;
input [0:7]din;
output y;
wire [0:7]t;
assign t[0]=(~s[0])&(~s[1])&(~s[2]&i[0]);
assign t[1]=(~s[0])&(~s[1])&(s[2]&i[1]);
assign t[2]=(~s[0])&(s[1])&(~s[2]&i[2]);
assign t[3]=(~s[0])&(s[1])&(s[2]&i[3]);
assign t[4]=(s[0])&(~s[1])&(~s[2]&i[4]);
assign t[5]=(s[0])&(~s[1])&(s[2]&i[5]);
assign t[6]=(s[0])&(s[1])&(~s[2]&i[6]);
assign t[7]=(s[0])&(s[1])&(s[2]&i[7]);
assign y=t[0]|t[1]|t[2]|t[3]|t[4]|t[5]|t[6]|t[7];
endmodule
8:1 MUX USING BEHAVIORAL MODELING STYLE:

`resetall
`timescale 1ns/1ps
module mux81bh(i,s,o) ;
input [0:7]i;
input [0:2]s;
output o;
wire [0:7]i;
wire [0:2]s;
wire [0:7]y;
reg o;
always@(s)
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begin
case(s)
3'b000: o=i[0];
3'b001: o=i[1];
3'b010: o=i[2];
3'b011: o=i[3];
3'b100: o=i[4];
3'b101: o=i[5];
3'b110: o=i[6];
3'b111: o=i[7];
endcase
end
endmodule
8:1 MUX TEST BENCH:
`resetall
`timescale 1ns/1ps
module mux81df_tb_v;
// Inputs
reg [0:7] din;
reg [0:2] s;
// Outputs
wire y;
mux81df uut (
.din(din),
.y(y),
.s(s)
);
initial
begin
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din=8'b01010101;
s=3'b000;
#10 s=3'b001;
#10 s=3'b010;
#10 s=3'b011;
#10 s=3'b100;
#10 s=3'b101;
#10 s=3'b110;
#10 s=3'b111;
end
initial
begin
#100 $finish;
end
endmodule
SYNTHESIS RESULTS:
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SIMULATION RESULTS:
CONCLUSION: A 8:1 multiplexer is designed using behavioral, dataflow models are

EXPERIMENT: 7
DEMULTIPLEXER
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7.1. 1:4 DEMULTIPLEXER
AIM: To design a 1X4 DEMULTIPLEXER and verify its functionality and check its
simulation report.
The demultiplexer is the exact opposite to the multiplexer. In this, the data form one line
can be sent onto any one of many lines. The block diagram of multiplexer is given below
and the associated truth table.1:4 demultiplexer has one input and 4 output lines.
BLOCK DIAGRAM:
Z0
A
DEMULTIPLEXER
Z1
Z2
Z3
S0
S1
TRUTH TABLE:
S1
S0
Z0
Z1
Z2
Z3
VERILOG CODE FOR 1:4 DEMULTIPLEXER:

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`resetall
`timescale 1ns/1ps
module demux14bh(din,s,y) ;
input [0:1]s;
input din;
output [0:3]y;
wire [0:1]s;
wire din;
reg [0:3]y;
always @(s or din)
begin
case(s)
2'b00: begin y[0]=din;y[1]=4'b0;y[2]=4'b0;y[3]=4'b0;end
2'b11: begin y[3]=din;y[1]=4'b0;y[2]=4'b0;y[0]=4'b0 ;end
endcase
end
endmodule
TEST BENCH FOR 1:4 DEMULTIPLEXER:
`resetall
`timescale 1ns/1ps
module demux14bh_tb;
// Inputs
reg din;
reg [0:1] s;
// Outputs
wire [0:3] y;

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demux14bh uut (
.din(din),
.s(s),
.y(y)
);
initial begin
din = 1;
s=2'b00;
#10 s=2'b01;
#10 s=2'b10;
#10 s=2'b11;
end
initial
begin
#50 $finish;
end
endmodule
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SYNTHESIS RESULTS:
SIMULATION RESULTS:
CONCLUSION:
A 1:4 demultiplexer is designed and is verified using test bench.
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7.2--- 1:8 DEMULTIPLEXER
AIM: To design a 1:8 DEMULTIPLEXER and verify its functionality and check its
simulation report.
The demultiplexer is the exact opposite to the multiplexer. In this, the data form one line
can be sent onto any one of many lines. The block diagram of multiplexer is given below
and the associated truth table.1:8 demultiplexer has one input and 8 output lines.
BLOCK DIAGRAM:
Y0
Y1
Y2
Y3
DEMULTIPLEXER
1x8
Y4
Y5
Y6
Y7
S0
S1
S2
TRUTH TABLE:
S0
0
0
0
0
1
1
S1
0
0
1
1
0
0
S2
0
1
0
1
0
1
Y[0]
A
0
0
0
0
0
Y[1]
0
A
0
0
0
0
Y[2]
0
0
A
0
0
0
52
Y[3]
0
0
0
A
0
0
Y[4]
0
0
0
0
A
0
Y[5]
0
0
0
0
0
A
Y[6]
0
0
0
0
0
0
Y[7]
0
0
0
0
0
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1 1 0 0
0
0
1 1 1 0
0
0
VERILOG CODE FOR 1:8 DEMUX:
`resetall
0
0
`timescale 1ns/1ps
module demux18beh(din, s, y);
input din;
input [0:2] s;
output [0:7] y;
//
reg din;
// reg [0:2] s;
wire din;
wire [0:2] s;
reg [0:7]y;
always@(s)
begin
case (s)
3'b000:y=8'b10000000;
3'b001:y=8'b01000000;
3'b010:y=8'b00100000;
3'b011:y=8'b00010000;
3'b100:y=8'b00001000;
3'b101:y=8'b00000100;
3'b110:y=8'b00000010;
3'b111:y=8'b00000001;
default:y=8'b11111111;
endcase
end
endmodule
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0
0
0
0
A
0
0
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TEST BENCH FOR 1:8 DEMULTIPLEXER:

`resetall
`timescale 1ns/1ps
module demux18beh_tb_v;
reg din;
reg [0:2] s;
// Outputs
wire [0:7] y;
demux18beh uut (
.din(din),
.s(s),
.y(y)
);
initial
begin
din=1;
s=3'b000;
#5 s=3'b001;
#5 s=3'b010;
#5 s=3'b011;
#5 s=3'b100;
#5 s=3'b101;
#5 s=3'b110;
#5 s=3'b111;
end
initial
begin
#80 $finish;
end
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endmodule
SYNTHESIS RESULTS:
SIMULATION RESULTS:
CONCLUSION:
A 1:8 demultiplexer is designed and is verified using test bench.
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EXPERIMENT: 8
COMPARATORS
4- BIT COMPARATOR
AIM: To design a four bit comparator using behavioral model and verify using the
functionality using test bench.
TOOLS USED:
Xilinx 9.2i.Hardware Tool.

Comparator is a circuit which compares two n-bit binary numbers and determines if they
are equal or which one is larger if they are not equal.
BLOCK DIAGRAM:
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TRUTH TABLE:
altb aeqb agtb
0000 1111
0001 1110
0010 1101
0011 1100
0100 1011
0101 1010
0110 1001
0111 0111
1000 1000
1001 0110
1010 0101
1011 0100
1100 0011
1101 0010
1110 0001
1111 0000
Where aeqb denotes a equals b and altb denotes a less than b and agtb denotes a greater
than b
VERILOG CODE:
`resetall
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`timescale 1ns/1ps
module comparator1(a, b, altb, aeqb, agtb);
input [0:3] a;
input [0:3] b;
output altb;
output aeqb;
output agtb;
//wire a[0:3];
//wire b[0:3];
reg altb,aeqb,agtb;
always@(a or b)
begin
if(a<b)
begin
altb=1'b1;
{aeqb,agtb}=1'b0;
end
else if(a==b)
begin
aeqb=1'b1;
{altb,agtb}=1'b0;
end
else
begin
agtb=1'b1;
{aeqb,altb}=1'b0;
end
end
endmodule
4 BIT COMPARATOR TEST BENCH
`resetall
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`timescale 1ns/1ps
module comparator_tv_v;
// Inputs
reg [0:3] a;
reg [0:3] b;
// Outputs
wire altb;
wire aeqb;
wire agtb;
comparator1 uut (
.a(a),
.b(b),
.altb(altb),
.aeqb(aeqb),
.agtb(agtb)
);
initial
begin
a=4'b0101; b=4'b0101;
#10 a=4'b0100; b=4'b0110;
#10 a=4'b1010; b=4'b0011;
end
initial
begin
#30 $finish;
end
endmodule
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SYNTHESIS RESULTS:
SIMULATION RESULTS:
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CONCLUSION: A 4- bit comparator is designed and its functionality is verified using

the test bench
\
EXPERIMENT: 9
ARITHMETIC AND LOGIC UNIT
AIM: To design all the logic ALU using the behavioral modeling style and verify the
functionalities along with their synthesis and simulation reports.
Arithmetic logic unit is used to perform all the arithmetic operations like
Addition, Subtraction, division, multiplication etc and logical operations like AND, OR,
NOR, NAND, XOR, XNOR etc.
VERILOG CODE:
`resetall
`timescale 1ns/1ps
module alu4(a, b, s, y);
input [3:0] a;
input [3:0] b;
input [1:0] s;
output [3:0] y;
wire [3:0]a;
wire [3:0]b;
wire [3:0]s;
reg [3:0]y;
always@(s)
begin
case(s)
2'b00:y=b;
2'b01:y=a+b;
2'b10:y=a|b;
2'b11:y={b[2:0],1'b0};
endcase
end
endmodule
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TEST BENCH FOR ALU:

`resetall
`timescale 1ns/1ps
module alu_tb_v;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg [3:0] s;
// Outputs
wire [3:0] y;
alu4 uut (
.a(a),
.b(b),
.s(s),
.y(y)
);
initial
begin
a=4'b0000;
b=4'b0001;
s=2'b00;
#10 s=2'b01;
#10 s=2'b10;
#10 s=2'b11;
end
initial
begin
#100 $finish;
end
endmodule
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SYNTHESIS RESULTS:
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SIMULATION RESULTS:
CONCLUSION:
ARITHEMETIC AND LOGIC UNIT is designed in behavioral model and output is
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D-FLIP FLOP
EXPERIMENT: 10
AIM: To design a D-flip flop with synchronous reset in behavioral model and testing the
functionality using test bench
The flip flop circuit can maintain a binary state indefinitely (as long as the power is
delivered to the circuit) until directed by an input signal to switch states. The major
difference among the various types of the flip flops are in the number of inputs they
possess and in the manner in which the inputs affect the binary states. A D- flip flop has
one input D ,the input D is sampled during the occurrence of the clock pulse. In D-flip
flop with synchronous reset, the output depends only on the clock..
BLOCK DIAGRAM:
TRUTH TABLE:
Clk Q D Q(n+1)
1
0 0
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0 1
1 0
1 1
VERILOG CODE:
`resetall
`timescale 1ns/1ps
module dff1(data, clk, reset, q);
input data;
input clk;
input reset;
output q;
wire data,clk,reset;
reg q;
always @ ( posedge clk )
if (reset)
begin
q <= 1'b0;
end
else
begin
q <= data;
end
endmodule
TEST BENCH:
`resetall
`timescale 1ns/1ps
module dff1_tb_v;
// Inputs
reg data;
reg clk;
reg reset;
// Outputs
wire q;
dff1 uut (
.data(data),
.clk(clk),
.reset(reset),
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.q(q)
);
initial
clk = 1'b1;
always
#5 clk = ~clk;
initial
begin
data=1; reset=1;
#5 data=0; reset=0;
#5 data=1; reset=0;
#10 data=1; reset=0;
end
initial
begin
#50 $finish;
end
endmodule
SYNTHESIS RESULTS:
SIMULATION RESULTS:
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CONCLUSION:
A D- Flip flop with synchronous reset is designed in behavioral model and tested using
test bench.
EXPERIMENT:11
SHIFT REGISTERS
11.1 LEFT SHIFT REGISTER USING ASYNCHRONOUS RESET

AIM: To design a 4-bit left shift register using asynchronous reset in behavioral model
and testing the functionality using test bench.
The Shift registers are a type of sequential circuits mainly used for the storage of the data,
a shift register is a group of flip flops connected in a chain so that the output of one flip
flop is connected as the input to the next flip flop. All the flip flops are driven by a global
clock, left shift register is shift register in which the data keeps shifting towards the left
for each positive edge of the clk
BLOCK DIAGRAM:
Qa
Da
A
Qb
Db
Qc
Dc
C
Qd
Db
Ser
D
clk
TRUTH TABLE:
Clk Reset Q
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0000 0
0001 1
0011 1
0111 1
1111 1
VERILOG CODE:
4-BIT LEFT SHIFT REGISTER WITH ASYNCHRONOUS RESET USING

BEHAVIORAL MODEL
`resetall
`timescale 1ns/1ps
module leftshiftreg(clk, reset, sr, q);
input clk;
input reset;
input sr;
output [3:0] q;
wire reset,sr,clk;
reg [3:0] q;
always@(posedge clk)
begin
if(reset)
q=4'b0000;
else
q={q[2:0],sr};
end
endmodule
4-BIT LEFT SHIFT REGISTER TEST BENCH
`resetall
`timescale 1ns/1ps
module leftshiftreg_tb_v;
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// Inputs
reg clk;
reg reset;
reg sr;
// Outputs
wire [0:3] q;
leftshiftreg uut (
.clk(clk),
.reset(reset),
.sr(sr),
.q(q)
);
initial
clk=1'b1;
always
#5 clk=~clk;
initial
begin
reset=1'b1;
#3 reset=1'b0;
#6 reset=1'b0;
end
initial
begin
sr=1'b0;
#10 sr=1'b1;
#10 sr=1'b1;
#10 sr=1'b1;
#10 sr=1'b1;
#10 sr=1'b1;
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#10 sr=1'b1;
end
initial
begin
#100 $finish;
end
endmodule
SYNTHESIS RESULTS:
SIMULATION RESULTS:
CONCLUSION:
A 4-bit shift register using asynchronous reset is designed in behavioral model and tested
using test bench.
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EXPERIMENT:12
UNIVERSAL SHIFT REGISTER
AIM: To design UNIVERSAL SHIFT REGISTER and verify the functionalities along
with their synthesis and simulation reports.
TOOLS USED:
DESCRIPTION OF THE MODULE: The UNIVERSAL SHIFT REGISTER(USR)

performs hold value, shift left, shift right and load value functions. This register can be
used as a serial in-serial out, parallel in parallel out, serial in-parallel out, parallel in
serial out shift register.
BLOCK DIAGRAM:
clock
reset
leftsh
rightsf
Universal
Shift register
pin
VERILOG CODE USING BEHAVIORAL MODELING:

`resetall
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`timescale 1ns/1ps
module universalshiftreg(clk, reset, leftsh, rightsf, sel, pin, q);
input clk;
input reset;
input leftsh;
input rightsf;
input [0:1]sel;
input [0:3] pin;
output [0:3] q;
wire clk,sel,leftsh,rightsf,reset;
wire [0:3] pin;
reg [3:0] q;
always@(posedge clk )
begin
if (reset)
q=4'b0000;
else
begin
case(sel)
2'b00:q=4'b0000;
2'b01:
q={q[2:0],leftsh};
2'b10:
q={rightsf,q[3:1]};
2'b11:
q=pin;
endcase
end
end
endmodule
USR TEST BENCH:
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`resetall
`timescale 1ns/1ps
module universalshift_tb_v;
// Inputs
reg clk;
reg reset;
reg leftsh;
reg rightsf;
reg [0:1] sel;
reg [0:3] pin;
// Outputs
wire [3:0] q;
universalshiftreg uut (
.clk(clk),
.reset(reset),
.leftsh(leftsh),
.rightsf(rightsf),
.sel(sel),
.pin(pin),
.q(q)
);
initial
clk=1'b1;
always
#5 clk=~clk;
initial
begin
reset=1'b1;
#5 reset=1'b0;
end
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initial
begin
leftsh=1'b1;
#5 rightsf=1'b1;
#10 pin=4'b1010;
end
initial
begin
sel=2'b00;
#5 sel=2'b01;
#5 sel=2'b10;
#5 sel=2'b11;
end
initial
#50 $finish;
endmodule
SYNTHESIS RESULTS:
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SIMULATION RESULTS:
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CONCLUSION: UNIVERSAL SHIFT REGISTER is designed in Behavioral model and

tested using test bench.
EXPERIMENT:13
COUNTERS
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12.1 UP COUNTER
AIM: To design UP COUNTER and verify functionality along with its synthesis and
simulation reports.
DESCRIPTION OF THE MODULE: A sequential circuit that goes through a
prescribed sequence of states upon the application of input pulses is called counter. If a
counter counts from lower value to higher value then it is known as UP COUNTER.
BLOCK DIAGRAM:
q
clock
Up counter
reset
enable
TRUTH TABLE:
Clock Reset Enable
0000
0001
0010
0011
0100
0101
0110
0111
1000
10
1001
VERILOG CODE USING BEHAVIORAL MODELING:

`resetall
78
10M11D5716
SIMULATION LAB
`timescale 1ns/1ps
module upcounter(clk, reset, enable, q);
input clk;
input reset;
input enable;
output [0:3] q;
wire clk,reset,enable;
reg [0:3] q;
begin
if(reset==1'b1)
q=4'b0000;
else if(enable==1'b1)
begin
q=q+4'b0001;
end
end
endmodule
UPCOUNTER TEST BENCH:
`resetall
`timescale 1ns/1ps
module upcounter_tb_v;
// Inputs
reg clk;
reg reset;
reg enable;
// Outputs
wire [0:3] q;
upcounter uut (
.clk(clk),
79
10M11D5716
SIMULATION LAB
reset(reset),
.enable(enable),
.q(q)
);
initial
clk=1'b1;
always #5 clk=~clk;
initial
begin
enable=1'b1;
reset=1'b1;
#5 reset=1'b0;
end
initial
begin
#160 $finish;
end
endmodule
SYNTHESIS RESULTS:
80
10M11D5716
SIMULATION LAB
SIMULATION RESULTS:
CONCLUSION: UP COUNTER is designed using behavioral modeling style and is

13.2 DOWN COUNTER

81
10M11D5716
SIMULATION LAB
AIM: To design DOWN COUNTER and verify functionality along with its synthesis and
simulation reports.
TOOLS USED:
DESCRIPTION OF THE MODULE: A sequential circuit that goes through a

prescribed sequence of states upon the application of input pulses is called counter.
DOWN COUNTER counts from higher value to lower value.
BLOCK DIAGRAM:
clock
q
Down counter
reset
enable
TRUTH TABLE:
clock reset enable
1111
1110
1101
1100
1011
1010
1001
1000
0111
10
0110
VERILOG CODE:
82
10M11D5716
SIMULATION LAB
`resetall
`timescale 1ns/1ps
module downcounter(clk, enable, reset, q);
input clk;
input enable;
input reset;
output [0:3] q;
wire enable,clk,reset;
reg [3:0]q;
begin
if(reset)
q=4'b1111;
else if(enable==1'b1)
q=q-4'b0001;
end
endmodule
DOWN COUNTER TEST BENCH:
`resetall
`timescale 1ns/1ps
module downcounter_tb_v;
// Inputs
reg clk;
reg enable;
reg reset;
// Outputs
wire [3:0] q;
downcounter uut (
.clk(clk),
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10M11D5716
SIMULATION LAB
.enable(enable),
.reset(reset),
.q(q)
);
initial
clk=1'b1;
always #5 clk=~clk;
initial
begin
enable=1'b1;
reset=1'b1;
#5 reset=1'b0;
end
initial
begin
#300 $finish;
end
endmodule
SYNTHESIS RESULTS:
84
10M11D5716
SIMULATION LAB
SIMULATION RESULTS:
CONCLUSION: DOWN COUNTER is designed using behavioral modeling style and is

85

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10M11D5716

functionalities along with their synthesis and simulation reports.

(not) (and) (or)

(nand) (nor) (xor) (xnor)

assign y[0] = ~a;

assign y[1] = a&b;

assign y[2] = a|b;

assign y[3] = ~(a&b);

assign y[4] = ~(a|b);

assign y[5] = a^b;

assign y[6] = ~(a^b);

Xilinx 9.2i Hardware Tool

DESCRIPTION OF THE MODULE:

a, b are inputs and carry, sum are outputs

2.2 FULL ADDER

FULL ADDER TEST BENCH

4-BIT BINARY PARALLEL ADDER

Where a,b,cin are the inputs and sum,carry are outputs

4-BIT BINARY PARALLEL ADDER USING BEHAVIORAL MODELING

8'b11011101: begin s=4'b1011; co=1'b1;end

4 BIT BINARY PARALLEL ADDER is designed in behavioral style and output is

4.1---- 2 TO 4 LINE DECODER

unique output lines. The purpose of decoder is to generate

CONCLUSION: 2 to 4 decoder has been designed using behavioral, dataflow models

4.2-----3X8 LINE DECODER

Here a,b,c are the inputs and D0 to D7 are the outputs.

3TO8 LINE DECODER USING DATA FLOW MODELING STYLE

3 TO 8 DECODER USING BEHAVIORAL MODELING STYLE

Xilinx 9.2i Hardware Tool.

DESCRIPTION OF THE MODULE:

din[0] din[0] din[0] din[0] a b

4'b0001:begin a=1'b1; b=1'b1; end

4TO2 LINE ENCODER USING DATAFLOW MODELING STYLE:

4TO 2 LINE ENCODER TEST BENCH

Xilinx 9.2i Hardware Tool

DESCRIPTION OF THE MODULE:

din0 din1 din2 din3 din4 din5 din6 din7 a b c

Where din0 to din7 are inputs and a,b,c are outputs.

assign a=din[4] | din[5] | din[6] | din[7];

8 TO 3 ENCODER USING BEHAVIORAL MODELING STYLE

:begin a=1'bz;b=1'bz;c= 1'b1;end

8 TO 3 LINE ENCODER TEST BENCH:

4:1 MUX USING BEHAVIORAL MODELING STYLE:

CONCLUSION: A 4:1 multiplexer is designed using behavioral, dataflow models are

Xilinx 9.2i Hardware Tool

DESCRIPTION OF THE MODULE:

Where S0,S1,S2 are inputs and Y is output

8:1 MUX USING DATA FLOW MODEL

8:1 MUX USING BEHAVIORAL MODELING STYLE:

CONCLUSION: A 8:1 multiplexer is designed using behavioral, dataflow models are

7.1. 1:4 DEMULTIPLEXER

VERILOG CODE FOR 1:4 DEMULTIPLEXER:

// Instantiate the Unit Under Test (UUT)

7.2--- 1:8 DEMULTIPLEXER

TEST BENCH FOR 1:8 DEMULTIPLEXER:

Xilinx 9.2i.Hardware Tool.

DESCRIPTION OF THE MODULE:

altb aeqb agtb

CONCLUSION: A 4- bit comparator is designed and its functionality is verified using

ARITHMETIC AND LOGIC UNIT

TEST BENCH FOR ALU:

11.1 LEFT SHIFT REGISTER USING ASYNCHRONOUS RESET

4-BIT LEFT SHIFT REGISTER WITH ASYNCHRONOUS RESET USING