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Even Parity Bit Generator
Even Parity Bit Generator
The aim of this project is to design a 3-bit even parity generator that can detect a one-bit
error in a message and draw the CMOS layout in L-Edit, which can then be simulated
using PSPICE.
Abstract:
An even parity bit generator generates an output of 0 if the number of 1s in the input
sequence is even and 1 if the number of 1s in the input sequence is odd. The checker
circuit gives an output of 0 if there is no error in the parity bit generated. Thus it basically
checks to see if the parity bit generator is error free or not.
Schematic:
The design procedure is made simple by writing the truth table for the circuit.
Truth table:
Message
Checker bit
X Y Z
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
The circuit can now be derived by drawing the K-map for the output.
P X Y Z X Y Z XYZ X Y Z X Y Z
This function can be implemented using exclusive-or gates. The schematic of the parity
generator circuit is shown in Figure 1.
Similarly
the
checker
circuit
can
be
designed
using
XOR
gates,
where
Figure 3: Combined schematic of both parity bit generator and checker circuit
The final layout consists of four XOR gates, which can be designed, in L-EDIT using the
CMOS technology. The basic building blocks in CMOS technology are MOSFETs. A
MOSFET is a metal oxide semiconductor field effect transistor. The advantages of
MOSFET over BJTs are, they are smaller in size and the drain and source terminals are
interchangeable. This provides the designers with area minimization on the chip.
Software used:
1. L-EDIT student version for drawing the layouts.
2. PSPICE for simulating the layouts.
Figure 4: nMOSFET
Figure 5 shows that nMOSFET is constructed
rules.
A p-channel MOSFET follows the same basic order, except that the n-well must be
defined. The steps are:
1. Create an NWELL region for the pMOSFET.
2. Construct an ACTIVE box/polygon for the transistor.
3. Surround ACTIVE with PSELECT. The intersection of the two is pdiff.
4. Draw a POLY box over pdiff for the gate.
5. Provide an ACTIVE and NSELECT box within NWELL for the n-well contact
(to VDD)
Note that the n+ contact formed in step 5 is needed to bias the n-well to the power supply
voltage.
Figure 7 shows the layout of a pMOSFET. Design is constructed sequentially by
performing DRC at each stage.
Figure 7: pMOSFET
Figure 8 shows the DRC file for a pMOSFET. All design rules are obeyed.
Figure 9 shows the extraction definition file for the layout in Figure 7.
Procedure:
Any layout in L-Edit can be drawn using these two transistors. In this project, four XOR
gates are needed which can be built from the basic transistors. It is important to
understand the schematic of an XOR gate. A simple XOR gate can be built using two
inverters and two transmission gates.
CMOS Inverter:
The schematic of a CMOS inverter circuit is shown in Figure 10. It consists of a p-FET
and an n-FET connected back in the form of a complimentary pair. The gates of the two
transistors are connected to the input pulse and the inverted output pulse is obtained at the
point where the source of the p-FET is connected to the drain of the n-FET. When the
input pulse is at 0 level, the p-FET turns ON and the DC voltage V DD is observed at the
output. When the input is at HIGH level, the n-FET turns ON and the ground voltage 0 is
observed at the output.
VOUT
VIN
VSS
NMOS
Figure 11: Inverter layout
The .SPC file is extracted from this layout, which is shown in Figure 12. This file
indicates that there are two transistors in the layout i.e., M1 and M8. The line M1 11 3 10
PMOS indicates the nodes for the p-MOSFET in the order Drain Gate Source. By
observing the node numbers for both the transistors we can say that node 3 is the
common gate where the input pulse is to be given and node 10 is the common point
where output is obtained. Voltage VDD is given at node 11 and VSS is given at node 9. By
using this information a .CIR file can be created wherein the values for these voltages are
specified at corresponding nodes.
10
Transmission gate:
A transmission gate consists of a PMOS and an NMOS connected in a way that input is
transmitted in one condition and blocked in other condition. The schematic of a
transmission gate is shown in Figure 15.
S
Figure 16: L-Edit layout of transmission gate
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The extraction and simulation steps are the same for every layout and thus are repeated
for the transmission gate. The .cir file and the PSPICE simulation of the transmission gate
are shown in Figures 17 and 18 respectively.
12
13
B
A
A XOR B
14
15
16
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transmitter end and the receiver end. A parity bit is generated at the transmitting end and
is transmitted along with the message bits through the transmission channel. At the
receiving end the parity bit is again generated and is checked against the parity bit
generated at the transmitter. If both are the same then the message is error free else the
message is different from the transmitted message. Note that this method only helps in
detecting a one-bit error in message sequence but it does not correct the message. This is
one of the many error detection methods used in digital communications.
References:
1. Physical Design of CMOS Integrated circuits using L-Edit by John P.Uyemura.
2.Circuit Design for CMOS VLSI by John P.Uyemura.
3.http://users.ece.gatech.edu/~rdanse/ECE2030/slides/ECE2030_Chapter06_2pp.pdf
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