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Microprocessor Multiple Choice Ques
Microprocessor Multiple Choice Ques
control bus
control instructions
address decoder
CPU
5. In an 8085 microprocessor, the instruction CMP B has been executed while the contents
of accumulator is less than that of register B. As a result carry flag and zero flag will be
respectively
(A) set, reset (B) reset, set (C) reset, reset (D) set, set
6. To put the 8085 microprocessor in the wait state
(i) lower the-HOLD input
(ii) lower the READY input
(iii) raise the HOLD input
(iv) raise the READY input
7. Registers, which are partially visible to users and used to hold conditional, are known as
a. PC
b. Memory address registers
c. General purpose register
d. Flags
8. What type of control pins are needed in a microprocessor to regulate traffic on the bus, in
order to prevent two devices from trying to use it at the same time?
a. Bus control
b. Interrupts
c. Bus arbitration
d. Status
b.DTR
c.DSR
d. RTS
11. The number of memory cycles required to execute the following 8085 instructions
(i)
LDA 3000H
(ii)
LXI D, FOF1H
would be
d)Size of register
b) FFH
c) 92H
d) 11H
22. The contents of accumulator before CMA instruction is A5H. Its content after instruction
execution is
MS.R.RAJAKUMARI AP/IT, PMU,VALLAM
a) A5H
b) 5AH
c) AAH
d) 55H
23. In an 8085 based system, the maximum number of input output devices can be connected
using I/0 mapped I/O method is
a) 64
b) 512
c) 256
d) 65536
24.
25. What generation chip is the Pentium 4 for the Intel central processing units?
A.
B.
C.
D.
Seventh generation
Eighth generation
Ninth generation
Tenth Generation
26. The first processor to include Virtual memory in the Intel microprocessor family
was:
a.)
b.)
c.)
d.)
27.
a.
b.
c.
d.
80286
80386
80486
Pentium
Intel Itanium processors are designed for
Servers and personal computers
Servers only
Personal computers only
Calculators
28. In 8086 microprocessor one of the following instructions is executed before an arithmetic
operation
a. AAM b) AAD c) DAS d) DAA
29. In 8051,After reset the SP register is initialized to address________.
a. 8H b) 9H c) 7H d) 6H
30. Serial port interrupt is generated, if ____ bits are set
a) IE b) RI, IE c) IP, TI d) RI, TI
31. In 8051 which interrupt has highest priority?
a)IE1 b)TF0 c)IE0 d)TF1
32. When the 8051 is reset and the line is LOW, the program counter points to the first
program instruction in the:
A.
B.
C.
D.
33. In 8051 an external interrupt 1 vector address is of ________ and causes of interrupt if ____.
a) 000BH, a high to low transition on pin INT1
b) 001BH, a low to high transition on pin INT1
c) 0013H, a high to low transition on pin INT1
d) 0023H, a low to high transition on pin INT1
34. In a microprocessor, the service routine for a certain interrupt starts from a fixed location of
memory which cannot be externally set, but the interrupt can be delayed or rejected. Such an
interrupt is
(A) non-maskable and non-vectored
(B) maskable and non-vectored
(C) non-maskable and vectored
35.
For the 8085 assembly language program given below, the content of the
accumulator after the execution of the program is
3000
3002
3003
3004
3005
3006
MVI A, 45H
MOV B, A
STC
CMC
RAR
XRA B
36.
37. The TRAP is one of the interrupts available its INTEL 8085. Which one of the following
statements is true of TRAP?
(a) It is level triggered
(b) It is negative edge triggered
(c) It is positive edge triggered
(d) It is both positive edge triggered and level triggered
38. In a 16-bit microprocessor, words are stored in two consecutive memory locations. The
entire word can be read in one operation provided the first
(a) word is even
(b) word is odd
(c) memory location is odd
(d) memory address is even
39. The ESC instruction of 8086 may have two formats. In one of the formats, no memory
operand is used. Under this format, the number of external op-codes (for the coprocessor) which can be specified is?
a. 64
b. 128
c. 256
d. 512
40. DB, DW and DD directives are used to place data in particular location or to simply
allocate space without preassigning anything to space. The DW and DD directories are
used to generate
a.
offsets
b.
c.
d.