Ve270 Introduction to Logic Design

Homework 9
Assigned: July 26, 2016
Due: August 4, 2016, at the beginning of the class.
The homework should be submitted in hard copies.
1. How to implement on a 4-input 1-output LUT the following function:
F(a,b,c,d) = abd + bcd
Show the memory contents of the 4 input 1 output LUT. (10 points)
2. Given an SRAM block,

32
32

data
addr
rw

SRAM

en

If the memory is byte addressable (each byte has an address), how many bits in maximum
can the SRAM block have? (10 points)
3. Problem 5.43 (30 points)
4. What will be the signature generated by the following single input compressor (SIC) for the
bit stream 011010011101 coming through port p? Assume the initial outputs of D flip-flops
are all 0s. (15 points)

5. Model the SIC in problem 4 using Verilog HDL. Verify your solution to Problem 4. (25
points)
6. The following circuit is a finite state machine. Explain how to set the state of the circuit to
y2y1 = 10 in the circuit. (10 points)