Digital Electronics

Principles & Applications

Seventh Edition

Roger L. Tokheim
Chapter 7

Flip-Flops

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INTRODUCTION
Combinational vs. Sequential Logic Circuits
R-S Flip-flop
Clocked R-S Flip-flop
D Flip-flop
J-K Flip-flop
Latches (simple memory devices)
Triggering of flip-flops
Schmitt triggered device
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Logic Circuits
Logic circuits are classified into two groups:
Combinational Logic Circuits
Basic building
blocks include:
Sequential Logic Circuits
Basic building blocks
include FLIP-FLOPS:
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QUIZ
1. Basic building blocks for __________
combinational
(combinational, sequential) logic circuits
include logic gates (such as NOT, AND, and
OR).
2. Basic building blocks for sequential logic
circuits include various flip-flops. (True
or False)
3. A flip-flop is an example of a device used
in __________ (combinational,
sequential) logic circuits.

True

sequential

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R-S Flip-Flop
Symbols:

Set

Normal

FF
R

Reset

Truth Table:

Mode of Operation
Outputs

Complementary

Inputs
S

Prohibited

Set
Reset
Hold

0
1
1

1
0
1

Q
1

1
0
Q

0
1

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QUIZ
What is the mode of operation of the R-S flip-flop (set, reset or hold)?
What is the output at Q from the R-S flip-flop (active LOW inputs)?
L
H

H
H

H
L

?High
Mode of operation = Set?

?High
Mode of operation = Hold?

?Low
Mode of operation = Reset
?
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Clocked R-S Flip-Flop

Symbols:

Set

Clock

Mode of operation
Outputs
Clk
Q
Hold
change
Reset
0 1
Set

Normal

CLK

Reset

Truth Table:

FF

Complementary

Inputs

+ pulse

+ pulse
+ pulse

Q
no
0

1
1

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QUIZ
What is the mode of operation of the clocked R-S flip-flop (set, reset, hold)?
What is the output at Q from the clocked R-S flip-flop (active HIGH inputs)?
H
^
L

L
^
L

L
^
H

?High
Mode of operation = Set
?

?High
Mode of operation = Hold
?

?Low
Mode of operation =Reset
?
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D Flip-Flop
Symbol:
(with asynchronous PS & CLR)

Truth Table:

Mode of Operation
Outputs
CLR
CLK D

Inputs
PS
Q

Asynchronous set
0
1
X
X
1
0
Asynchronous reset
1
0
X
X
0
1
--------------------------------------------------------------------Prohibited
1
1
X
X
1
1
Set
1
1
^
1
1
0
Reset
1
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QUIZ

What is the mode of operation of the D flip-flop?

What is the output at Q from the D flip-flop?

L
H

? High

^
H

H
L
^
H

H
H
^
H

Mode of operation =Asynchronous

?
Set

? Low
Mode of operation = Reset
?

? High
Mode of operation = Set
?
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J-K Flip-Flop
Symbol:

Truth
Table:

Mode of Operation
Outputs

Inputs
PS

Clr

Clk

Q
Asynchronous set
1
0

Asynchronous reset
1
0
x
x
x
0
1
Prohibited
0
0
x
x
x
1
1
------------------------------------------------------------------------Hold
1
1
^
0
0
no change
Reset
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What is the mode of operation of the J-K flip-flop?

What is the output at Q from the J-K flip-flop?

QUIZ
L
L
^
H
H

?High
Mode of
operation =

?
Preset

H
H
^
H
H

Toggle
?

H
H
^
H
H

?
Reset

H
H
^
H
L

?Low
Mode of
operation =

H
L
^
H
H

?Low
Mode of
operation =

H
H
^
H
H

?High
Mode of
operation =

Toggle
?

?Low
Mode of
operation =

Toggle
?

? Low
Mode of
operation =

Clear
?

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Latch
A fundamental digital storage device
The act of storing data for a time, such
as to latch
An R-S flip-flop is an example of a latch
A D flip-flop can perform as a latch
In IC form (examples: 4-bit, 8-bit, 9bit, 10 bit)
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QUIZ
1. A fundamental digital storage device is
sometime called a(n) ___ (gate, latch).
2. The job of a latch can be performed
by a(n) ___ (gate, D-flip-flop).

latch
D-flip-flop

3. We say that to latch is the act of

storing data for a time. (True or False)

True

4. Latches are commonly imbedded in

more complex ICs and serve as
temporary memory devices. (True or
False)

True

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Triggering of Flip-Flops
Level-triggering is the transfer of data from input to
output of a flip-flop anytime the clock pulse is HIGH.
Edge-triggering is the transfer of data from input to
output of a flip-flop on the rising edge (L-to-H) or falling
edge (H-to-L) of the clock pulse. Edge triggering may be
either positive-edge (L-to-H) or negative-edge (H-to-L).
Master-slave triggering is an older technique using the
whole clock pulse but think of a master-slave flip-flop as
having negative-edge triggering.
Positive-edge triggering

Negative-edge triggering
H

time

Level triggering
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QUIZ
1.

2.

3.

If a flip-flop triggers on the L-to-H transition

of the clock pulse (see A) it is called a
__________ (level, positive-edge) triggered
device.
If a flip-flop triggers on the H-to-L transition
of the clock pulse (see B) it is called a
__________ (level, negative-edge) triggered
device.
If a flip-flop triggers while the clock pulse is
HIGH (see C) it is called a __________ (level,
positive-edge) triggered device.

positive-edge

negative-edge

level
C

H
L

time
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Schmitt Trigger Operation

Positive-going threshold
Negative-going threshold

Output
Input

Schmitt trigger device

squares up input
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QUIZ
1. The symbol at the lower right is that of a
__________ (magneto-optical, Schmitt trigger)
inverter.
2.

If the input signal to the Schmitt trigger inverter

is a sine wave the output will be a __________
(square-wave, triangular-wave).

3. A Schmitt-trigger device will digitize or

square up input signals with slow rise times
and slow fall times. (True or False)

Schmitt trigger

square wave

True

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REVIEW
Combinational vs. Sequential Logic Circuits
R-S Flip-flop
Clocked R-S Flip-flop
D Flip-flop
J-K Flip-flop
Latches (simple memory devices)
Triggering of flip-flops
Schmitt triggered device
2008 The McGraw-Hill Companies, Inc. All rights