Introduction to VHDL

Synopsys @ 2000

Contents
! VHDL Overview
! Main Design Units
! Data Types
! VHDL Objects
! Process Statements
! Data flow Statements
! Concurrent Statements
! Hierarchical Designs
! Test Bench
Synopsys @ 2000

VHDL Overview

Synopsys @ 2000

VHDL

V - Very High Speed Integrated Circuit

H - Hardware
D - Description
L - Language
Synopsys @ 2000

What is VHDL?
A Documentation language - interconnections, interface, hierarchy
A Simulation language - behavior, RTL, netlist
A Synthesis language - technology independent logic design
An extendable language

User package
Vendor package
Standard package
VHDL Language
(STD-1076)
Synopsys @ 2000

VHDL Language
VHDL has all the characteristics of a modern programming language
Data types - predefined and user defined
Variables, Signals, and Constants
Expressions - relational, logical, arithmetic,
Sequential statements:
If, Case, For loop
Subprograms
Concurrent statements:
Signal assignment,
concurrent processes, component instances
Packages
Configurations
Dynamic memory allocation
File input/output
Synopsys @ 2000

Why use VHDL

! Same language used at every stage of design
description, simulation & synthesis
! VHDL codes units are modular and
configurable - support for design reuse
! VHDL code units are technology independent
! VHDL source code are synthesizable
! Standard code - machine readable by different
CAE tools Verify Function
! Reduce design time & increases productivity

Synopsys @ 2000

ASIC DESIGN FLOW using VHDL

Design
Spec.

Architectural Definition

RTL
VHDL Source Code

Validate
Simulate Chip at
RTL level

Logic Synthesis

Verification
Simulate Chip at
Gate level
Synopsys @ 2000

Vendor
Netlist

Chip layout
&
Fabrication

Main Design Units

Synopsys @ 2000

VHDL - Main Elements

AND2.vhd

VHDL Design File

Library IEEE;
Use IEEE.Std_Logic_1164.All;

Library &
package declaration

entity AND2 is
port ( A, B : in std_logic;
C : out std_logic );
end AND2;

Entity declaration

Architecture RTL of AND2 is

begin
C <= A and B ;
end RTL;
Configuration CFG_AND2 of AND2 is
for RTL
end for;
end CFG_AND2;

Synopsys @ 2000

Architecture Specification

Configuration definition

Entity - Design Interface

! VHDL separates the interface specification
(entity) from the detailed implementation
! The entity specifies the external connections of
a new component
! Your architecture is not visible

A
C
B

Synopsys @ 2000

Entity Specification
keyword

entity name

entity AND2 is
port ( A, B : in std_logic;
C : out std_logic );
end AND2;

Port name,
direction &
data type

! Defines AND2 as a new component

! Defines the interface to the design
! VHDL is not case sensitive, but EDA tools might be Always have consistent naming convention
Synopsys @ 2000

Entity port declaration

! Syntax:
Port_Name : direction data_type ;
! Direction can be either : IN, OUT, INOUT, BUFFER
! Example:
Port (
Reset :
ClK :
Control :
DBUS :
);

Synopsys @ 2000

in bit;
in std_logic;
out std_logic
out std_logic_vector(7 downto 0)

Entity Exercise
Complete the entity description given below.
All ports are assumed to be of type std_logic.
Clr

Entity _______ is
Q

port (

DFF
Clk

Qn

Set

);
end ______ ;
Synopsys @ 2000

Architecture Specification
keyword

Architecture Name

Entity Name

Architecture RTL of AND2 is

Declaration
region

begin
C <= A and B ;
end RTL;

Describe the
behavior of the
design

! Architecture defines the behavior of the design

! There are many ways to describe a single design
! Each architecture must be associated with one entity

Synopsys @ 2000

Different Architecture Styles

Architecture DATFLOW of Mux is
begin
Z <= A when sel = 1 else B;
end DATFLOW;
Architecture BEHAV of Mux is
begin
Process
begin
wait on A,B,sel;
if (sel=1) then
Z <= A ;
else
Z <= B;
end if;
end Process;
end BEHAV;

Architecture STRUC of Mux is

signal Asel, Bsel, selbar : bit;
begin
U0: INV port map (sel, selbar) ;
U1: And2 port map (A, sel, Asel);
U2: And2 port map (B, selbar, Bsel);
U3: Or2 port map (Asel, Bsel, Z);
end STRUC;

Structural -- interconnection of components

Data flow -- implies structure and behavior
Behavioral -- implies behavior using sequential constructs
Synopsys @ 2000

Configuration
! Primary design unit like entity & architecture
! Binds component instances (architecture) to
entity
! Creates simulation objects
! Facilitates port re-mapping

Synopsys @ 2000

Configuration
keyword

Configuration Name

Entity Name

Configuration CFG_AND2 of AND2 is

for RTL
end for;
end CFG_AND2;

Architecture Name

! A configuration statements selects a unique architecture

of an entity
! When no explicit configuration exists, the latest compiled
architecture is used (called the null configuration)
Synopsys @ 2000

Configuration Examples
Entity XR2 is
port ()
end XR2 ;
Architecture fast of XR2 is

end fast;

Configuration ONE of XR2 is

for fast
end for ;
end ONE;

Architecture small of XR2 is

end small;

Configuration TWO of XR2 is

for small
end for ;
end TWO;

Synopsys @ 2000

Packages
! User defined or vendor provided
! Stores declaration of common data types,
constants, component declaration etc.
! Allows sharing of design units
! Package STANDARD included as default
! Packages are supplied in libraries
! Package STD_LOGIC supplied in IEEE library

Synopsys @ 2000

Package Example
keyword

Package Name

Package math is
CONSTANT MEAN_VALUE : INTEGER := 5 ;
end math;

Synopsys @ 2000

How to use a Package

In your VHDL source file, do this:

Example: using the package Std_logic_1164 from the library IEEE

Library Library Name ;

Use Library_name.package_name.all;
...

Library IEEE ;
Use IEEE.Std_logic_1164.all;
...

Synopsys @ 2000

IEEE Packages
! std_logic_1164
! std_logic_misc
! std_logic_components
! std_logic_textio
! std_logic_arith
! std_logic_unsigned
! std_logic_signed

Synopsys @ 2000

Libraries
Certain VHDL objects are kept in a library
! package - shared declarations
! architecture - shared designs
! entity - shared design interfaces
! configuration - shared design versions
VHDL expects:

your working library to be called Work

standard library called STD
which contains:
standard package
text input/output

Users can have other design libraries for:

! Synthesis
! ASIC vendor library
Synopsys @ 2000

Using Library IEEE & Synopsys

Library Synopsys
Use Synopsys.Distributions.All ;
Library IEEE;
Use IEEE.Std_logic_1164.all;
Use IEEE.Std_logic_unsigned.all;

Synopsys @ 2000

Data Types

Synopsys @ 2000

VHDL is strongly typed

! In VHDL information (objects) must be of a
type
! The type specifies the values the object may
have
! Users can also define their own data type and
operators
! Vendors provide extended data types for
simulation and synthesis

Synopsys @ 2000

Data Types
VHDL provides package STANDARD containing pre-defined types:

! Characters
! String - An array of characters
! Bit
! Bit_vector - An array of bits
! Boolean
! Integer
! Real
! Time
Synopsys @ 2000

Bit literal
! Bit can only be 0 or 1
! Bit_vector is an array of bits defined in double
quotes: 0011 01101111
! Defined in package Standard
! Base precedes sequence
Binary

Octal

Hex

X
Example:

Synopsys @ 2000

X7E

Boolean literal

! Predefined to be False or True

! Relation operator (= <= >= /=) produce boolean
result
! Boolean values can be tested in if statements
and assigned
! A boolean is NOT a bit and has NO relation to
bit

Synopsys @ 2000

Real Literal
! Represents floating point numbers
! NOT synthesizable
! Format is + or - number.number [E + or - number]
! Examples:
1.0
1

Illegal - Integer value, no decimal point

-1.0 E 10
5.3
6 E -10
Synopsys @ 2000

Illegal - no decimal point

Integer range
! Represents integer values with fixed points
! Operators such as +, -, * can be used
! Minimum/Maximum range depends on the
implementation but must cover the range 2,147,483,647 to +2,147,483,647
! Users can specify a range constraint
! Example: 123 15 - 21

Synopsys @ 2000

Range Constraint
! Simulator checks for valid type and range on
assignment
! Range constraint specifies a restricted range
! Example:
integer range 0 to 9
real range 1.0 to 1.1
! Used to qualify the intended usage of data

Synopsys @ 2000

Different Constraint Uses

! Model limit of existing component
twelve bit d_to_a
port (data : in integer range 0 to 4095 )
eight bit fifo
port (data_in : in integer range 0 to 255 ;
data_out : integer range 0 to 255 );
! Direct synthesis
signal a, b, c : integer range 0 to 15
synthesizes 4 bit logic
Synopsys @ 2000

Back to Bit_Vector
! VHDL has package Standard declarations including
BIT_VECTOR which is an array of bits
! Assignment examples to C of type bit_vector of 4-bits:
C := 1010

Constant bit_vector

C := S & T & M & W

4 1-BIT signal concatenated

C := (1, 0, 1 , 0)

4 BIT Aggregate

C := 3

Invalid

! Declaration of C will define subscript range (constraint)

Synopsys @ 2000

Declaring a Bit_Vector
! Declaration must provide constraint on size
variable C : Bit_Vector (0 to 3) ;
variable D : Bit_Vector (3 downto 0) ;
C := 1010;
C(0)

C(1)

C(2)

C(3)

D(1)

D(0)

D := C
1
D(3)

0
D(2)

Left most bit is always the Most Significant Bit (MSB)

Synopsys @ 2000

Slice of an Array
! A subscripted array reference can be used in
either side of a signal or variable assignment
statement
! Example:
Port (
A : in bit_vector (0 to 3);
C : out bit_vector (8 downto 1);

C (6 downto 4) <= A ( 0 to 2);

Synopsys @ 2000

Direction in declaration
and slice must be the same

Bit_Vector Example
Architecture
Begin
Process
variable data : bit_vector (0 to 31) ;
variable start : integer range 0 to 24 ;
variable data_out : bit_vector (0 to 7) ;

Begin
For I in 0 to 7 loop
data_out(I) <= data(I + start);
end loop;

end Process
Synopsys @ 2000

IEEE Std_logic data type

IEEE standard 1164 defines std_logic as:
U
X
0,1
Z
W
L,H
-

uninitialized
unknown
high impedance (tri-state)
weak unknown
weak 0,1
dont care

Package std_logic_1164 is in library IEEE

Recomendded:
Use std_logic instead of bit
Use std_logic_vector instead of bit_vector

Synopsys @ 2000

Array of Arrays

Syntax:
type Array_type_name is array (integer_range) of type_name;
Example
type mem_type is array (0 to 65535) of std_logic_vector (7 downto 0);
signal memory : mem_type

Synopsys @ 2000

Physical Time
Type TIME is defined in package Standard
Unit
fs
ps
ns
us
ms
sec
min
hr

femtoseconds
picoseconds
nanoseconds
microseconds
miliseconds
second
minute
hour

Example:

Synopsys @ 2000

number space units

24 hr
0.1 ns

Enumerated Types
! Defines legal values through an enumerated list
of character literals (X) or identifiers
! Examples
type instruction is (add, sub, lda);
type value4 is (X, 0, 1, Z);
! Uses symbolic codes instead of numeric values
! Provides for more abstract representation in
source design

Synopsys @ 2000

Enumerated Type Example

Architecture behave of mp is
type instruction is (add, lda, ldb);
begin
Process
variable ins : instruction;
variable a,b : integer;
begin
case ins is
when lda => a := data;
when ldb => b := data;
when add =>a:= a + b;
end case;
...

Synopsys @ 2000

Qualified Expression
! Example:
type months is (May, June, July);
type name is (April, June, Judy);
June is ambiguous type in some contexts
! To resolve ambiguity, use Qualified Expression
months(June)
name(June)

Synopsys @ 2000

Exercise - Identify the type

! 1
! 1.
! 1.0
! 1
! 1 ns
! 1
! true
! range 1 to 15

Synopsys @ 2000

VHDL Objects

Synopsys @ 2000

VHDL Objects
! Signal - global wires which use up simulator
time
! Constant - name specifies value
! Variable - local storage or wires

! VHDL Objects names are not case sensitive but EDA tools
may have their restriction on this.
! Do not use VHDL reserved words
! Make sure you have a consistent naming style

Synopsys @ 2000

Signals
! Can be scalar (single bit) or array and can be initialized.
Example:
signal identifier : data_type := initial_value

optional
signal reset : bit := 0 ;
signal internal_bus : std_logic_vector (7 downto 0) ;
signal dec_int : integer range 0 to 4 ;

Synopsys @ 2000

Signal (cont.)
! Represents global data storage or wires
! Declared in Architecture

! Assigned with

<=

(pronounced as gets)

! Assignment executes in simulated time

(schedule). Example
reset <= 1 ;
internal_bus <= 11110000 ;
dec_int <= 4 ;
Synopsys @ 2000

Signal Declaration
! Defined before the begin clause in an
Architecture
! Example
Architecture RTL of AN2 is
signal xyz : bit := 1 ;
signal abc : std_logic ;
Begin

end RTL ;
Synopsys @ 2000

Internal signals
defined within this
region

Constants
! Names constant values
constant identifier : data_type := value ;
! Scalar example:
constant pi : real := 3.1416 ;
! Array example:
constant mask : bit_vector(3 downto 0) := 0011 ;
! Generally defined in a VHDL package

Synopsys @ 2000

Variables
! Can be scalar or array and can be initialized
! Syntax:
variable identifier : type := initial_value
! Example:
variable xyz : bit ;
variable xyz : integer range 0 to 7 := 7 ;
variable dbus : std_logic_vector (3 downto 0) ;

Synopsys @ 2000

Variables (cont.)
! Local data inside a process (covered later)
! Assigned immediately, no simulated time
! Right hand side type must match left hand side
! Assigned with :=
! Example:
xyz := 0 ;
data := 3 ;
dbus := 1011 ;

Synopsys @ 2000

Variable Declaration
! Defined before the begin clause in an Process
! Example:

Architecture RTL of AN2 is

signal xyz : bit := 1 ;
Begin
Process
variable abc : std_logic ;
Begin

end process;
...
end RTL ;
Synopsys @ 2000

variables
defined within this
region

Signal & Variable Visibility

Signal
Visibility

Architecture RTL of AN2 is

signal xyz : bit := 1 ;
Begin
Process
variable abc : std_logic ;
Begin

...
end process;

...
end RTL ;

Synopsys @ 2000

Variable
Visibility

Operators
! Logical : and or nand nor xor
! relation:

= /= < <= > >=

! adding

+-&

! sign

+-

! multiplying operator
! misc.

low precedence

* / mod rem

** abs not

A+B*C

valid

A and B or C

not valid

high precedence

Operator of the same precedence must be parenthesized

Synopsys @ 2000

Type Conversion Exercise

Write a statement to convert a BIT object to a BOOLEAN object,
1 becomes true
Hint: Use the equality relation operator to produce a boolean
Variable BITTY : BIT ;
Variable BOOLY : BOOLEAN ;
BOOLY := ______________________ ;

Synopsys @ 2000

Process Statements

Synopsys @ 2000

Process Statements
! Defines a regions in Architectures where
sequential statements are executed
! Provides programming language-like capability
using temporary variables
! Used for behavioral descriptions
! In simulation all processes are started and
executed up to a wait statement
! Must contain either a wait statement or
sensitivity list
! Behaves as an infinite loop, except for the wait

Synopsys @ 2000

Process Example
Entity nand2 is
port (a,b : in bit ;
c: out bit );
end nand2 ;

Architecture behave of nand2 is

begin
P1: Process
variable temp : bit ;
begin
wait on a,b ;
temp := NOT (a and b);
If (temp = 1) then

sequential statements

end process P1;

end behave ;

Synopsys @ 2000

Parallel Process
Architecture RTL
Begin
A: Process
begin
if (true) then
wait

end Process A ;
B: Process
begin
if (true) then
wait

end Process B ;
end RTL;

Synopsys @ 2000

! VHDL permits concurrent process

operation to be simulated
! Each process starts at begin,
executes statements in sequence till
a wait statement suspends the
process.
! When process hits end Process; it
continues from begin
! The process labels (e.g. A, B) helps
during simulation
! The order the process is written is
not important

Process Statements:
Sequential Statements

Synopsys @ 2000

Sequential Statements
! Only valid inside a Process
! Statements include:
Assignment with logic/arithmetic operators
IF
CASE
LOOP
Wait

Synopsys @ 2000

If and ELSIF
If then
statements;
...
end if;

If then
statement 1;

else
statement 2;

end if;

If then
statement 1;

elsif then
statement 2;

elsif then
statement 3;

else
statement 3;
...
end if;

If statements imply priority

Synopsys @ 2000

If Statement Example
If enable = 1 then
Q <= D ;
end if;
If RESET = 1then
Q <= 0 ;
elsif CLKevent and CLK=1 then
Q <= D ;
end if;

Synopsys @ 2000

If SEL=00 then
DATA <= 0 ;
elsif SEL=01 then
DATA <= 1 ;
elsif SEL=10 then
DATA <= 2 ;
else
DATA <= 3;

Type Conversion Exercise

Write a statement to convert a BOOLEAN object to a BIT object,
true becomes 1 . Hint: Use If statement
Variable BITTY : BIT ;
Variable BOOLY : BOOLEAN ;
if _______________ then
________ := _______ ;
else
________ := _______ ;
end if;
Synopsys @ 2000

Case Statement
case expression is
when value_1 =>
s1; s2; sn;
when value_2 =>
s1; s2; sn;

No begin/end required
around these group of
statements

when others =>

s1; s2; sn;
end case;
Case statements imply parallel execution
Each case selection must be mutually exclusive
Synopsys @ 2000

Case Statement Example

Case SEL is
when 01 => DATA <= 1 ;
when 10 => DATA <= 2 ;
when 11 => DATA <= 3 ;
when others => DATA <= 0 ;
end case;
Variable INT : bit ;
case INT is
when 0 => DATA_OUT <= 0000 ;
when 1 => DATA_OUT <= 1111 ;
end case ;

Synopsys @ 2000

Case Statement Rules

! Selection between a number of actions
! Choices must cover all possible values of
expression, or have an OTHERS clause
! The OTHERS clause must be the last choice of
all the choices
! No overlap of case condition is allowed

Synopsys @ 2000

Loop Statement
! Optional label for each loop
! Can have more then one loop in a process
! Two types of loop: FOR LOOP & WHILE LOOP
! FOR LOOP iterates for fixed number of times
! WHILE LOOP iterates until a condition is
satisfied
! Nested loops are allowed
! Use NEXT to skip a single iteration
! Use EXIT to exit a loop before it completes
Synopsys @ 2000

For loop Example

Loop_label : For loop_index in discrete_loop_range loop
statemtents;
...
End Loop Loop_label ;
The loop index need not be declared
L1: For CSR in 1 to 10 loop
C := CSR * 2;
DATA_BUS(CSR) <= C ;
end loop L1;
Synopsys @ 2000

Next Example
Max: FOR IND in 0 to max_limits LOOP
next when ( VALUE(IND) < biggest ) ;
biggest := VALUE(IND) ;

Next skips to the next iteration of the loop

Synopsys @ 2000

Exit Example
Outside: For IND in 0 to max loop
Inside: For JND in 0 to max loop
Exit Outside when a(I) < 0 ;
power(IND, JND) := a(IND) ** JND
end loop Inside;
end loop Outside;

Exit exits the named loop

Synopsys @ 2000

While Loop Example

Loop_label: While (condition) loop
statements;

end loop Loop_label ;

L1: While (day <=5) loop

day := day + 1 ;
end loop L1;

Synopsys @ 2000

Wait Statements
! Suspends process execution
! Three types:
WAIT FOR

( not synthesizable )

WAIT UNTIL

( synthesizable partially )

WAIT ON

( not synthesizable )

! Process can have Wait statements or a sensitivity list

but not both

* covered later
Synopsys @ 2000

Wait Statement Examples

Wait on A,B ;
Suspends execution until an event occurs on either A or B
Wait until A >10;
Suspends execution until condition A > 10 is satisfies
Requires an event on A to evaluate expression
Wait for 10 NS ;
Suspends execution of process of 10 ns of simulated time

Synopsys @ 2000

Subprograms

! Single value returned -- Functions

! Multiple parameters modified -- Procedures
! Contains sequential statements
! Values are passed through parameters

Synopsys @ 2000

Procedures
! Considered a statement not an expression
(does not have a value)
! Can modify parameter so can return more then
one value
! In, Out, Inout parameter modes
! Parameters can be variables or signals
! Declared in package, process or architecture

Synopsys @ 2000

Procedure Syntax
Procedure procedure_name
( formal_parameter_list ) is

Procedure
Declaration

procedure_declaration ;
begin
sequential_statements ;
end procedure_name ;

Synopsys @ 2000

Procedure
Body

Procedure Example
Procedure vector_to_int
(Z : in bit_vector (0 to 7);
signal zero_flag : out boolean;
q : inout integer ) is
begin
q:= 0;
zero_flag <= true;
for i in 0 to 7 loop
q : q*2;
if (Z(i) = 1) then
q := q + 1;
zero_flag <= false;
end if;
end loop
end vector_to_int;

Synopsys @ 2000

Process
begin

vector_to_int
(my_vector,
test_flag,
result) ;
...

Function
! Returns only ONE value
! Contains sequential statements: if, case, loop
etc.
! Converts from one type to another
! Some built in function (refer to VHDL manuals)
! Some vendor or user defined
Function name (parameters) return TYPE is
variable declarations
begin
sequential statements ;
return () ;
end name;
Synopsys @ 2000

Function Example
Function func3 ( A, B : in real) return real is
begin
return A * B * 2.0 ;
end func3;
Function BigNum (A, B : in integer)
return std_logic is
begin
if (A >B) then
return 1 ;
else
return 0 ;
end BigNum ;

Architecture

begin
signal temp : std_logic ;
process

X <= 6;
Y <= 7;
temp <= BigNum (X, Y);
...

Synopsys @ 2000

Process Statements:
Communications

Synopsys @ 2000

Communication Between Processes

! Inside a Process, we can have variables
! Are the variables visible (can be used) outside
the process?

! What if we want to communicate between

processes?

Signals communicate between processes

Synopsys @ 2000

Process Signaling Model

Architecture
First: Process

Local
Variable

Last: Process
signal

Local
Variable

Signals used to communicate between processes

Signals used to synchronize processes

Synopsys @ 2000

Process Communication - Signals

Architecture first of sender is
signal First_Done : bit := 0 ;
begin
Want_First: process
begin
do my stuff
First_Done <= 1 ;
wait for 10 ns ;

end Want_First
Want_Last: Process
begin
wait until First_Done = 1 ;

Synopsys @ 2000

Signals - Confusing Syntax <=

One signal assignment of a boolean value

C <= A <= B ;

Better to write it this way:

C <= ( A <= B ) ;

Synopsys @ 2000

Signal Delay - Inertial Delay

! Model inertial delay
! The after clause specifies the amount of time
that has to pass before an assignment
becomes effective
! Example:

A <= B after 10 NS ;

! Used for simulation only

B
A

B
0 5

10

A
10
Synopsys @ 2000

20

Signal Delay - Propagation Delay

! Models propagation delay
! Used for simulation only
! Requires the transport clause
! Example:

B
0 5
A
10 15
Synopsys @ 2000

A <= transport B after 10 NS ;

Signal Assignment Example

Process
Begin
sys_clk <= NOT (sys_clk) after 50 NS ;
sys_clk2 <= 0, 1 after 20 NS, 0 after 30 NS;
wait for 100 NS ;

! Signal assignment scheduled in simulated time

! Not executed until wait statement is
encountered

Synopsys @ 2000

Simulation Time
Now

50

100

150

sys_clk

sys_clk2

Process runs now

Signals events scheduled relative to now
Process runs again 100ns from now
Synopsys @ 2000

200

Process Communication - Signals

All concurrent things evaluate

Then all signals propagate

Synopsys @ 2000

Data Flow Statements

Synopsys @ 2000

Concurrent Statements - Data flow

! Exist outside of a process but in an
architecture
! Concurrent signal assignment is a short hand
form for a single process statement -equivalent to a process containing one
statement, sensitive to changes on the right
hand side
! Used frequently in Data Flow style descriptions
! Good for describing combinational logic

Synopsys @ 2000

Concurrent Signal Assignment

Architecture DFLOW if EN1 is

begin
OUTPUT <= A (INDEX) ;
end EN1;

Synopsys @ 2000

Architecture BEH of EN1 is

begin
Process (A, INDEX)
begin
OUTPUT <= A (INDEX);
end Process;
end BEH;

Concurrent Assignment Statements

! Example
Architecture
begin
A <= B + C; -- statement 1
D <= E + F; -- statement 2

end ...
! Builds combinational circuitry
! If B or C changes then statement 1 is evaluated
! If E or F changes then statement 2 is evaluated

Synopsys @ 2000

Concurrent Signal Assignment

! Executes asynchronously, with NO defined
relative order
! Syntax
target <= expression ;
expression is logical, comparative, or
arithmetic operation
! VHDL offers other forms of concurrent signal
assignments:
Conditional - similar to if statements
Selected - similar to case statements
Synopsys @ 2000

Conditional Signal Assignment

Syntax:
target <= { expression when condition else} expression ;

Example:
Z <= A when (X > 3) else B;
R <= S when (Y > 4) else
T when (Y < 4) else
U;
Can have only one target per assignment
Synopsys @ 2000

Selected Signal Assignment

Syntax:
with expression select
target <= {expression when choices, }
Example:
with Mysig select
Z <= A when 15,
B when 22,
C when 28,
D when others;
Can have only one target per assignment
Synopsys @ 2000

Concurrent Signal Sensitivity

! Concurrent statements are sensitive to all
signals on the input side
! If a signal appears on both sides, the statement
is sensitive to changes in its own output
A <= A + B ; will be evaluated when B changes.
This will change A and the statement will be
evaluated again!
! Simulation Time will not be able to advance
because the statement keeps executing.
Simulator will appear to Hang!

Synopsys @ 2000

Concurrent Statements

Synopsys @ 2000

Concurrent Statements
! Process
each process from begin to end is one
concurrent statement
! Component Instance
! Data Flow statements

Synopsys @ 2000

Process and Signal Assignment

! All processes run until each executes a wait
statement
! All processes use OLD values of signals
! After all processes are waiting, signal
assignments schedule with zero delay occur
! This may wake processes
! Must contain either an explicit sensitivity list or
a wait statement(s)
! Can have a mix of variables and signal
assignments

Synopsys @ 2000

Signal Vs Variable Assignment

Signals

Variable

! Signals values are

scheduled

! Variable values are not

scheduled

! Can have delay

! Values updated
without delay

! Signals updated only

when
! all process are
suspended (waiting)

Synopsys @ 2000

! Variables updated
immediately within the
process

Sensitivity List Vs. Wait Statements

Process (clk)
begin
if clkevent and clk=1 then
Q <= D;
end if;
end process

Process
begin
if clk = 1 then
Q <= D;
end if;
wait on clk;
end process

A sensitivity list is same as a process with a wait at the end of the

process
Can have one or the other but not both
Synopsys @ 2000

Drivers
! Drivers are created by signal assignment
statements
! Drivers contain present and future values
! A driver is a contributor to a signal value
! Value of a signal is the resolution of all the
driver values
! Multiple concurrent assignments to the same
signal may be ERROR prone ...

Synopsys @ 2000

Multiple Assignment
Example:
Architecture concurrent
begin
C <= A ;
C <= B ;

Architecture concurrent
begin
Process (A,B)
begin
C <= A ;
C <= B ;
end process ;
end concurrent;

! This may be invalid as it wires both A, B to C

! VHDL supports multiple drivers of signal and
requires a resolution of the multiple
assignment with a resolution function (wiredor, wired-and, three-state)
! A common practice in PCB design, not in ASIC
design. Requires vendor support
Synopsys @ 2000

Bad Multiple Driver Example

Library IEEE;
use IEEE.std_logic_1164.all;
entity mux is
port (i0, i1, i2, i3, a, b : in std_logic ;
q : out std_logic );
end mux;
architecture BAD of mux is
begin
q <= i0 when a = 0 and b = 0 else 0 ;
q <= i1 when a = 1 and b = 0 else 0 ;
q <= i2 when a = 0 and b = 1 else 0 ;
q <= i3 when a = 1 and b = 1 else 0 ;
end bad;
Synopsys @ 2000

Making the mux Work

Library IEEE;
use IEEE.std_logic_1164.all;
entity mux is
port (i0, i1, i2, i3, a, b : in std_logic ;
q : out std_logic );
end mux;
architecture better of mux is
begin
q <= i0 when a = 0 and b = 0 else
q <= i1 when a = 1 and b = 0 else
q <= i2 when a = 0 and b = 1 else
q <= i3 when a = 1 and b = 1 else X ;
end better;
Synopsys @ 2000

Hierarchical Design

Synopsys @ 2000

Design Hierarchy
! A VHDL design consists of a hierarchy of
components compiled from behavioral, data
flow or structural level architecture
! All components used must exist as compiled
designs in a library
! A components declaration is required before a
components is instanced
! A design containing components requires a
configuration (simulator dependent)
Compare
XR2

Synopsys @ 2000

INV

Component Declaration
Architecture S of compare
signal I : bit;
component XR2
port (X,Y : in bit ;
Z : out bit );
end component;
component INV port (X : in bit;
Z : out bit);
end component;
begin
U1: XR2 port map (A,B,I) ;
U2: INV port map (I,C);
end S;

Component
Declaration

Use work.xyz_gates.all;
Architecture S of compare
signal I : bit;
begin
U1: XR2 port map (A,B,I) ;
U2: INV port map (I,C);
end S;

Component
Instantiation

Components must be declared before used (or in a package)

Synopsys @ 2000

Package - Component Declaration

Package xyz_gates is
component XR2
port (X,Y : in bit ;
Z : out bit );
end component;
component INV
port (X : in bit;
Z : out bit);
end component;
end package xyz_gates;

Synopsys @ 2000

Package of components provided by

ASIC or FPGA vendor
Package contains all available
components
There is no package body
Component functions are defined in
separate ENTITY/ARCHITECTURE
files or delivered as a compiled library

Gates in a Library
Entity NAND2 is
port (A,B : in std_logic; C : out std_logic);
end NAND2;
Architecture ARC1 of NAND2 is
begin
C <= NOT (A and B) after 1.1 ns ;
end ARC1;

! ASIC/FPGA vendor library describes

component behavior
! Components could have unit delay or
parametric delay
! ASIC/FPGA vendor components are compiled
and stored in specific libraries (software
dependent)
Synopsys @ 2000

Component Declarations
Architecture S of compare
signal I : bit;
component XR2
port (X,Y : in bit ;
Z : out bit );
end component;
component INV port (X : in bit;
Z : out bit);
end component;
begin
U1: XR2 port map (A,B,I) ;
U2: INV port map (I,C);
end S;

Entity XR2 is
port (X,Y : in std_logic; Z: out std_logic);
end NAND2;
Architecture ARC1 of XR2 is
begin
Z <= X xor Y;
end ARC1;

Component is mapped to entity by NAME

Component port is mapped to entity ports by NAME
Synopsys @ 2000

Component Instantiation
compare
A

Xr2
B

INV

Syntax:
instance_name : component_name ( port mapping) ;
Example:
U1: XR2 port map (A,B,I) ;
U2: INV port map (I,C);

Positional Association

U1: XR2 port map ( X => A ,Y => B, Z => I) ;

U2: INV port map ( X => I, Z => C);

Named Association

Synopsys @ 2000

Interconnection - Using Signals

External
signals

Entity compare is
port (A,B : in bit ;
C : out bit );
end compare;
Architecture S of compare
signal I : bit;
component XR2
port (X,Y : in bit ;
Z : out bit );
end component;
component INV port (X : in bit;
Z : out bit);
end component;
begin
U1: XR2 port map (A,B,I) ;
U2: INV port map (I,C);
end S;

Synopsys @ 2000

Internal signalrequired for

interconnections

Test Bench

Synopsys @ 2000

Simulation Environment
control
commands

OUTPUT

INPUT

Textual messages

models
test vectors

Simulator

Tabular output

libraries

Graphical waveform

Assembly/
Microcode

Visual drawings

Feedback
Synopsys @ 2000

Different Simulation Goals

! Identify requirements - capacity & performance
! Experiment with alternate functionality
! Experiment with alternate solutions
! Verify implementation
! Develop regression test sets for other
architectures

Synopsys @ 2000

Different Simulation Models

! Statistical Models
! Behavioral Models
! RTL Models (synthesizable)
! Component structural models (gate-level netlist)
! Bus functional models

Synopsys @ 2000

Test Bench Approach

! Test bench has no I/O ports
! Has one component instance UUT (the top
most design unit)
! Requires a configuration

Process
Stimulus
and
results
testing

Synopsys @ 2000

Component
Unit
Under
Test
(UUT)

Unit Under Test - UUT

! Compiled VHDL design with interface at top
level entity
! Test designer understands logical function
! Test designer exercises logical functions
! The tests are intended to test design function
and/or timing
! The test are not intended to be IC tester test
cases but many designers include them as part
of IC tests

Synopsys @ 2000

Types of Test Stimulus

! Interactive - using keyboard etc. (depends on
simulator)
! Behavioral -- a counter of complex loop
! Linear list of tests -- literal values in a test
! Test file -- values provided in a separate data
file, normally called test vectors. File may
contain stimulus and expected response

Synopsys @ 2000

Test Bench Elements

Test Bench Entity
Test Bench Architecture
Stimuli declarations
Begin

Entity testbench is
end tesbench
architecture test of testbench is
signal in_sig: std_logic_vector (3 downto 0);
signal out_sig : std_logic_vector (3 downto 0);
component TOP
(A : in std_logic_vector (3 downto 0);
B :out std_logic_vector (3 downto)) );
end component ;
begin

UUT Instantiation
UUT : TOP port map (in_sig, out_sig) ;

Stimulus definition

Synopsys @ 2000

Process
begin
in_sig <= 0000 ;
wait for 10 ns ;
in_sig <= 0001 ;
...

TextIO
! Predefined package in library STD, requires the
use of : use STD.TEXTIO.all;
! Is a procedure that allows reading and writing
of ASCII text files
! Text files are treated as a group of lines
! Requires the use of procedure read() and
readline()

Synopsys @ 2000

Readline then Read

Text File

readline

readline finds a record in a

file and returns line of text

17 true 1001 4.7 13 ns False

read

17
Synopsys @ 2000

read finds 17 in line of text

and returns integer range 17

TextIO Example
Use STD.TEXTIO.ALL;
.
.
.
Process
File infile : Text is in /path/test/example1.vec;
File outfile : Text is out /path/test/results.dat;
Variable out_line, my_line : line ;
Variable int_val : integer;
begin
while NOT (ENDFILE (infile)) loop
readline (infile, my_line) ;
read ( my_line, inv_val );
int_val := int_val ** 2 ;
write (out_line, int_val);
writeline (outfile, out_line) ;
end loop;
...
Synopsys @ 2000

Example1.vec
10
20
50
1_2_3
87

52

results.dat
100
400
2500
15129
7569

Sample Codes

Synopsys @ 2000

Inferring Tri-State logic

Library IEEE;
Use IEEE.std_logic_1164.all;

Library IEEE;
Use IEEE.std_logic_1164.all;

Entity TRI is
port (A, SEL : in std_logic ;
B : out std_logic );
end TRI;
Architecture RTL of TRI is
begin
B <= A when (SEL = 1) else Z ;
end RTL;

Entity TRI is
port (A, SEL : in std_logic ;
B : out std_logic );
end TRI;
Architecture RTL of TRI is
begin
Process (A, SEL)
begin
if (SEL = 1) then
B <= A ;
else
B <= Z ;
end if ;
end process;
end RTL;

SEL
Synopsys @ 2000

Signal Attribute
Syntax:
Signal_name event
returns true if an event occurred in the current simulation
time step
Example:
If clkevent and clk = 1 -- wait for rising edge of clk
if clkevent and clk = 0 -- wait for falling edge of clk

Synopsys @ 2000

Inferring D-Type Latch

Library IEEE;
Use IEEE.std_logic_1164.all;
Entity DLatch is
port (D, EN : in std_logic ;
Q : out std_logic );
end DLatch;
Architecture RTL of DLatch is
begin
Process (EN, D)
begin
If (EN = 1) then
Q <= D ;
end if;
end process ;
end RTL;

Synopsys @ 2000

Inferring D Flip-Flop
Library IEEE;
Use IEEE.std_logic_1164.all;
Entity DFF is
port (D, CLK : in std_logic;
Q: out std_logic );
end DFF;

Synopsys @ 2000

Architecture RTL of DFF is

begin
process (CLK)
Begin
If CLKevent and CLK=1 then
Q <= D ;
end if;
end process;
end RTL;

Inferring D Flip-Flop with Asyn. Reset

Library IEEE;
Use IEEE.std_logic_1164.all;
Entity DFF is
port (D, CLK, RESET: in std_logic;
Q: out std_logic );
end DFF;

Synopsys @ 2000

Architecture RTL of DFF is

begin
process (CLK, RESET)
Begin
If (RESET = 1) then
Q <= 0 ;
elsif CLKevent and CLK=1 then
Q <= D ;
end if;
end process;
end RTL;

Inferring D Flip-Flop with Syn. Reset

Library IEEE;
Use IEEE.std_logic_1164.all;
Entity DFF is
port (D, CLK, RESET: in std_logic;
Q: out std_logic );
end DFF;

Synopsys @ 2000

Architecture RTL of DFF is

begin
process (CLK)
Begin
If CLKevent and CLK=1 then
If (RESET = 1) then
Q <= 0 ;
else
Q <= D ;
end if;
end if;
end process;
end RTL;

Inferring D Flip-Flop with Asyn.

Set/Reset
Library IEEE;
Use IEEE.std_logic_1164.all;
Entity DFF is
port (D, CLK, RESET,SET: in std_logic;
Q: out std_logic );
end DFF;

Synopsys @ 2000

Architecture RTL of DFF is

begin
process (CLK, RESET, SET)
Begin
If (RESET = 1) then
Q <= 0 ;
elsif (SET = 1) then
Q <= 1 ;
elsif CLKevent and CLK=1 then
Q <= D ;
end if;
end process;
end RTL;

Inferring D Flip-Flop with Syn.

Set/Reset
Library IEEE;
Use IEEE.std_logic_1164.all;
Entity DFF is
port (D, CLK, RESET,SET: in std_logic;
Q: out std_logic );
end DFF;

Synopsys @ 2000

Architecture RTL of DFF is

begin
process (CLK)
Begin
If CLKevent and CLK=1 then
If (RESET = 1) then
Q <= 0 ;
elsif (SET = 1) then
Q <= 1 ;
else
Q <= D ;
end if;
end if;
end process;
end RTL;

State Machine

Library IEEE;
Use IEEE.std_logic_1164.all;
entity SM is
port (rst, clk : in std_logic ;
a,b,c : in std_logic ;
q : out std_logic );
end SM;

Synopsys @ 2000

State Machine -2
Architecture RTL of SM is
type state_type is ( S1, S2, S3, S4) ;
signal current_state, next_state : state_type ;
begin
P1: process (rst, clk)
begin
if rst = 1 then
current_state <= S1 ;
elsif clkevent and clk=1 then
current_state <= next_state;
end if;
end process P1;

Synopsys @ 2000

P2: Process (a,b,c,

current_state, next_state)
begin
case current_state is
when S1 =>
q <= 0 ;
next_state <= S2;
when S2 =>
q <= a ;
next_state <= S3;
when S3 =>
q <= b ;
next_state <= S4;
when S4 =>
q <= c ;
next_state <= S2;
end case;
end process P2;
end RTL;

VHDL Summary
! A complete design is an interconnection of
component designs
! Each component design has a compiled entity
and architecture
! All communications occurs through ports
declared in the entity specification while
matching signal types, sizes and directions
! An architecture may be modeled at the
behavioral, data flow or structural level
! Packages contains commonly used
declarations
! A library contains reusable VHDL design units
Synopsys @ 2000