EXPERIMENT

14

Design of JFET
Bias Circuits

OBJECTIVES
1. To design a self-bias JFET circuit for specified bias conditions
2. To design a voltage divider-bias JFET circuit for specified bias conditions
3. To test both of these circuits and, if necessary, redesign them

EQUIPMENT REQUIRED
Instruments
Dual-trace oscilloscope
DMM
DC power supply
9v battery with snap-on leads

Components
Resistors
(1) 1-k
(1) 1-k potentiometer
Since this is a design experiment, a number of resistor values will have to be determined
and requested from the stockroom.
Transistors
(1) 2N4416 JFET or equivalent

RESUME OF THEORY

Like the BJT, the junction field-effect transistors can operate in three modes: cutoff,
saturation, and linear. The physical characteristics of the JFET and the external circuit
elements connected to it determine the mode of operation. In this experiment, the JFET is
biased in the linear mode in accordance with a given set of circuit specifications.
JFETs, even of the same type, show a considerable variation in their
characteristics. In consequence, manufacturers rarely publish the drain characteristics of
JFETs but simply specify both the saturation current I DSS and the pinch-off voltage VP.
The designer can construct and transfer characteristics from these two values and any
intermittent values of ID and VGS from Shockleys equation.
The transfer curves together with the operating specifications will be used to
determine needed values for the various circuit elements to be used in the two bias
design. In both cases, a procedure will be suggested that will place Q-point at or near the
specified DC operating conditions and will allow for a specified AC signal to be
amplified without distortion. Upon completion of the design, the experimenter will
construct the actual circuit and take the DC measurements to ensure correct operation of
the circuit. In case the design does not meet the specifications, a corrective procedure is
suggested.
PROCEDURE
Part 1. Determining IDSS and VP
This part of the experiment will determine IDSS and VP for the JFET to be employed in the
design process of this experiment.
a.
b.

Construct the network Fig. 14.1. Insert the measured value of RD.
Set VGS to zero volts and measure VRD. Calculate ID = IDSS = VRD/RD using the measure
resistance value and record below.

IDSS (measured) = 9.485mA__

c.

Make VGS increasingly negative until VRD =1mV (and ID= VRD/RD 1uA). Since ID
is small (ID

0A), the resulting value of VGS is the pinch-off voltage VP. Record

below.
VP (measured) = -3V__

Part 2. Self-Bias Circuit Design

This part of the experiment will determine R D and RS for the self bias configuration of figure 14.2. the Qpoint is calculated at IDQ=1/2(IDSS), VDSq = (VDSmax) with vDD= 2VDSq.
a. Using the specified Q-point and the results of part 1, with the constrain that V DSmax=30 V,
calculate IDQ VDSq and VDD.

IDq (Calculated)=_4.74mA______
VDSq(calculated)= _15V__________
VDD(calculated) =__30V__________

b. Using the IDSS and VP determined in Part 1, sketch the transfer characteristics in Figure 14.3.

c. The choice of IDQ= (IDSS) will permit a maximum swing in collector current for the AC domain.
Draw a horizontal line from (IDSS) on the IC axis to the transfer curve of Fig. 14.3 and label the
intersection as the Q-Point to define the self-bias line. Label the resulting line as the self-bias line
for future reference.
d. Determine the value of RS from

| || |

RS =

V GS
V
=
I
I D

Where || specifies the magnitude of the quantity and the change in each quantity from the origin
to the Q-point.
RS(calculated)= ____170.21 _____________
Determine the closest commercial value (Available in the laboratory) to the calculated R S and
insert its resistance value in the space provided on Fig. 14.2. In Addition, Insert the calculated
value for VDD from Part 2(a).
RS(commercial value) =_180 _________________
Insert the commercial and measured value of R S in the space provided on Fig. 14.2.
e.

The Resistance of RD will now be determined by an application of Kirchhoffs voltage law to the
output circuit of Fig. 14.2 followed by the use of Ohms Law. For the output circuit of Fig. 14.2,

V R =V DD V DS V R
D

Determine VRs= IDqRS (where RS is the measured resistance.

VRD = 30 15 (4.74x10-3)(180)
V RD(calculated)=
14.146V
Determine RD using IDQ from part 2(a) and Ohms law.
RD=VRD/ID=(14.147)/(4.74X10^-3)
RD(calculated)= 13164.83
Determine the closest commercial resistance value (available in the laboratory) to R D and record
below.
RD(commercial value) = 3000
f.

Using the commercial values of R D and RS and the calculated value of V DD construct the
network of Fig. 14.2. Energize the network and measure V DSQ and VRD. Use the measure value of
RD to calculated IDQ. Record the levels of VDSQ and IDQ below.
VDSQ(measured)= 13.477V
IDQ(measured) = 5.23mA
Record the design levels of IDQ and VDSQ calculated in Part 2(a).
VDSQ(calculated)=15V
IDQ (calculated) = 4.74mA

g. Compare your date from Part2(a) with the data from part 2(f).
-The group found out that the calculated values (VDSQ and IDQ) and measured values (VDSQ and
IDQ) have small differences with percent deviation of 10% only.
Perform a percent deviation calculation. Use the data from part 2(a) as the standard.

Vdsq (Specified)
Vdsq ( Specified )Vdsq(Calculated )

Idq( Specified) Vdsq=

Idq ( Specified )Idq (Calculated)
Idq=

15 v
15 v 13.477 v
4.74 mA Vdsq=
4.74 mA5.23 mA
Idq=
= 10.338 %

= 10.153 %

How could you reduce the size of that deviation if such was needed.
- We must adjust the resistances to have the desired V DSQ and IDQ. So that, percent
deviation of VDSQ and IDQ will lessen. Also, rounding-off for commercial values affect
the measured VDSQ and IDQ.
Part 3. Voltage-divider circuit design
This part of the experiment will determine the value of

RD ,

Rs ,

R1 , and

the voltage-divider configuration of Fig. 14.4. The Q-point is to be establish at

ID
And

= 4 mA

V DS

=8V

Additional specifications:

V DD = 20 V
R2 = 10 Rs

R2 . For

Values

obtained:

R1= 56k
R1(meas) = 56.667k
R2 = 10k
R2(meas) = 10k
RD = 2k
RD(mea) =2k
Rs = 1k
Rs(meas) = 1k
Using the specified value of VDD, the calculated value of VG (from the measured value of RS), and
the commercial value of R2, calculate the value of R1 using Eq. 14.3.

V G=

R2 (V DD )
R1 +R 2

R1 (calculated)=_____56.667 k_______

Determine the closest commercial value (available in the laboratory) to R 1 and insert below.
R1 (commercial value)=______56 k __________
Insert the commercial and measured values of R1 in Fig. 14.4.
e. Using the commercial values RD, RS, R1 and R2 and the specified value of VDD, construct the
network of Fig. 14.4. Energize the network and measure VRD. Using the measured value of RD,
calculate IDQ. Record the levels of VDSQ and IDQ below.

I D=

V RD 8.187
=
R D 2000

4.094 mA

V DS
ID

(measured)=______7.718V__________

(calculated)=_______4.094 mA__________

Record the specified design values of VDSQ and IDQ

V DS

ID

(specified)=_______8 V__________
(specified)=_______4 mA__________

f.

Using the following equations, determine the percent difference between specified and measured
values of

ID =
Q

ID =
Q

|I D

Q( specified)

ID

I D

|I D

and

|V

Q (calculated)

Q (specified )

V DS

DQ

|V DS

Q( specified )

V DS

|V DS

|4 mA4.0935 mA|
= 2.338 %
|4 mA|

Q (calculated )

Q (specified )

|8 V 7.718|
= 3.525 %
|8V |

VD =
Q

ID

(calculated) = __2.338 %_______

V DS (calculated) = ____3.525 %____

Q

Are you satisfied with your design effort? Be specific.

-

Yes, the design percent error falls to 3% (VDS) and 2% (IDQ). This means there is a
small discrepancies in the performed experiment.

g. If the percentage difference is more than 10%, how would you improve the design? Take careful
note of your voltage-divider bias line on Fig. 14.3 when you consider alternative designs.
-

All % error are less than 10 %.

Make adjustments in your design to reduce the percentage differences in

ID

and

V DS

to less

than to 10%. Record the new values of RD, RS, R1 and R2 below. In addition, record the new values of

ID

and

V DS

and calculate the percentage differences with specified levels.

..
RD (commercial value) =_____2 k _______
RS (commercial value) =______1 k ______
R1 (commercial value) =_

56 k ______

R2 (commercial value) =____10 k _______

ID

(calculated) =____4.0935 mA____

V DS
ID

(measured)=____7.718 V____
(calculated) = __2.338_%_____

V DS (calculated) = ___3.525 %_____

Q

Analysis:
The group analysed the data and found that: the characteristic curve of 2N4416 has I DSS=9.485
mA and VP = -3v. For self-bias configuration, commercial values of R D and Rs are 3k and 180,
respectively. While, having a percent deviation of 10 % for both VDSQ and IDQ. For voltage-divider
configuration, R1, R2, RD, and RS are 56 k, 10 k, 2 k, and 1 k, respectively. While, having a percent
deviation of 3 % for both VDSQ and IDQ.

Conclusion:
The group concluded that, it is necessary to determine the transfer characteristics curve of a
transistor to be able to design a configuration. Also, aside from the characteristic curve, the condition of
operation and Q-point must be known. With these, the circuit design for self-bias and voltage-divider is
possible.