Solutions Manual to accompany the text Introduction to VLSI Circuits and Systems by John P. Uyemura Preliminary Draft June, 2001 Note: This is the first draft ofthe Solutions Manual that was transcribed from tha author's hhand-scratched notes. It has not been proofread, nor have the solutions been checked for completeness or accuracy. While most of them are reasonably accurate, errors will be found. The final version of the Solutions Manual will be available in the near fre, JOHN WILEY & SONS, INC. NEW YORK + CHICHESTER « WEINHEIM + BRISBANE « SINGAPORE « TORONTO.Chapter 1 ‘There are no problems in Chapter 1. Chapter 2 [2.1] The nFET can pass any voltage in the range [0.Vmax) Where Vina (Vg ~ Vim) with Vg the voltage on the gate. With the stated values, Vina= 5-0.7=4.3 V. If Viq> Vmax then Vout 8 restricted t0 Vinge However, the nFET passes any voltage Vin < Vmax - This gives the following answers. (2) Vin= 2 V. Vou = 2 Vi (0) Vin= 4-5 V. Vout (©) Vin= 8.5 V. Vout = 8.5 Vi (@) Vin= 0.7 V. Voue= 0.7 V. ‘The main idea is to show the effect of the threshold loss through an nFET. 3 V is limited: [2.2] For Vi, < Vmax» then the input voltage fs transmitted through the chain. If Vi, > Vmax then a threshold drop occurs in the first transistor (only) and Vmax makes it to the output. With the stated values, Vma= 8.3-0.55=2.75 V This gives the following answers. (8) Vin= 2.9 V, Vous = 2.75 V (limited): (0) Vin= 8.0 V, Vous 2.75 V (limited); (0) Viq= 1-4 V. Vout= 1.4 Vi (@) Vin= 8.1 V, Vous 2.75 V (mited). [2.3] The output of the upper FET M1 (with V, applied) is used to control the gate voltage Vo of the lower transistor M2 (with V, applied). Both are susceptible to threshold voltage Problem (2.3)2 drops so that max(Vg) = (Vpp -Vmn) and max{Vour) = (Ve -Vm ). Using max{Vg) = (3.3-0.6 } = 2.7 V gives the following results. (@) Va= 8.3 V, Vp= 3.3 V: Vq= 2.7 V 50 Voy.= 2.7 - 0.6 = 2.1 V. 5 V, Vp= 3 V: Vg= 0.5 V so M2"is in cutoff. This makes Voy an unknown value since the transistor is an open circuit. V, Vp= 2.5 V:Vg= 2 V 80 Vout = 2 - 0. .8-V, Vp= 1.8 V: Vg= 2.7 V 50 Vout L4v. BV. [2.4] NANDS gate using an 8:1 MUX is shown in drawing below with Prob. [2.5] solution. [2.5] NORS gate using an 8:1 MUX is shown in drawing below with Prob. [2.4] solution. a Ta] pS | celery 2 | 26f$ 2off “ylo ° =o abe i abe 2 Output 2 Ourpur +3 3 i i ads 5 pele s ws 7 Problem (24) NAND3 Problem [25] NOR3 [2.6] The drawings below illustrate the XOR2 and XNOR2 MUX-based designs. To imple- ment the full-adder sum expression, we use s= (abcwhich shows that s can be calculated using 2 XOR gates. This is shown in Figure (c) below. a aa a a a fofo| ees a 40,59 ao.ro oore ptiot$ o—ist$ pial ro{$| L 263 XOR XOR }+5 oto ro ° ei oe) 1 ra orf? 2 3 3 orf (a) XOR2 (b) XNOR2 (c) sum Problem [2.6] [2.7] Rewrite the function to read f=abrebd to show that the function can be reduced to a simplified form. The gate is shown in the drawing. Yop pee aed pec ved pea ar — od Heo Problem [2.7] [2.8] The final design depends on the algebraic form selected. One approach is to first expand the terms as(a+b)-(a+e) = a+a-bra-c+b-c =a-(1+b)+a-crb-c a(lscj+bec asb-c ‘Then (a+b-c)-(b+d) a-beb-cta-d+b-d-c a(bed)+b-c(1+a) a(bed)+b-c ‘This form of the logic function gives the AOI gate shown, Note that there are variations possible. Problem [2.8] ea [2.9] Write B= x-(ytzey=x-yrx-zey sy (lsx)ex-e = yruz ‘This gives the simplified logic diagrams, which are then used to design the logic gate as shown,Yop OSes at nFETs i 4 n= Ly do mn i Problem [2.9] [2.10] Write Featb-c+a-b-c=a-(1+b-c)+b-c=a+be After reducing we see that this is the same circuit as for Problem [2.4] with the inputs relabeled. This is shown for completeness Problem (2.10)6 [2.11] ‘The pFET logic diagram and resulting gate are shown. oh d i a lpea F PFET Logie ot I» a 4 Problem [2.11] - [2.12] Solution is shown eee 0) pres aed 6 oq orf i ¢ c ‘ e A_/ et ol y é ‘pp a aed hs od pea be-d| poe 6 Problem [2.12][2.13] The logic expression is > xt x wae =U we ‘This leads to the nFET array shown. The circuit can be checked using series-parallel structuring. h ah Ke: wo Problem 2.13] = This example shows how the pFET logic equations can be used to describe a pFET network. The relationship to nFET equations is through the DeMorgan relations. [2.14] The 4:1 circuit directly illustrates how TGs are used in switching Problem [2.14][2.15] The logic equation can be written.as Jea-3ebes where aand bare the inputs, and s, S are the controls. An AOI22 gate would produce an output of FaAX+BY sowe assign a= A, b= B, X=, and Y= s and add an inverter. It is important to remem- ber that the location of the ports define how the output function is formed. a ae xe eal AC bee i ye] Aot22 foes ye Primitive Wared as 2:1 MUX (ports locations define mmputs) [2.16] This can be designed by using two input 2:1 MUXes that are controlled by so, and the MUXing the outputs by a 2:1 that is controlled by 5). 2 ot poo 21 PY a 2 so p31 Problem [2.16] [2.17] The period is9 Why such an easy problem? To illustrate the time frame that logic gates in a high-speed digital system must operate. As we will see in Part 2. fast circuits (short logic delays) can be difficult to design. [2.18] The smallest clock frequency is S min = 4Hz ‘While this is very slow, it does show that the clock cannot be idled. Chapter 3 [3.1] The resistance of the line is given by Rine = Ren where the number of squares can be divided into “normal” straight line contributions and corners. Let ne be the contribu- tion of a corner square. The number of square is given by tracing the line from A to B as. N= 154net124 n+ 14s net 44n.4224N,+9 = 76+56N, = 79.125 R = 25(79.125) = 1,978.1250 [8.2)The line resistance 15 Rine = Ret. Fdor the polysilicon line while the metal line is which is the smallest. [3.3](a) The sheet resistance is R,= 8 = 4x) _ 0.330 £* (1200x10) (b) The number of squares is given by 25 n= 22 = 156.25 squares so that the line resistance is10 Rune = (0-38)(156.25) = 52.082. [8.4]We have units of the RC product of fisl-f-|£ g]- 5ec- RC = (Q)F] which shows that r has units of sec as stated. [8.5] (a) Use the line resistance formula Rune = (25: (b) The line capacitance is (c) The line time constant is 15, 1 = RuneCine = (2000)(6.906x10"*) = 18.81 ps [3.6] (a) For n-type material, (©) The hole density is Pro = (6) The electron mobility is 1380-92 Hy = 92 7 pat = 493 cm? /V-sec 14{ 420 13x10”, while the hole mobility is bp = 47.7(92)+ 498-477 — = 135.9em2/v-see 14{ 4207 16x10" ‘The mobility is then given byul © = GaN + BpP)= ny since the majority electron concentration dominates. 27.71 [Q-cm) 13.7] Nq> Ng so the material is p-type. The majority carrier density is Ppo= 5.98x10"°em * and the minority carrier density is ni _ 45x10? Myo = Bo = Ce oamo Pp (5.98x10"*) = 35.2 cm [8.8] (a) We have carrier densities of .26x10%em Pro (©) The mobilities are in = 1373.36 and pp = 485.6 cm?/V-sec so that the conductivity is calculated from o = (1.6x10"% ')[(5.26x10°)](1373.36) + (4x10"*)(485.6)] This gives 9-031 p= (1/e) = 92.17{2-cm) (c) The resistance is e R= | 100x10 (82 17)) . 32.179 0 {3.9} (a) Start with : ; my a= ert su, (b) Differentiate: do ay, Ke so we require (c) The last equation shows that the highest resistively material is slightly p-type.12 13.10} (a) This is = 3.837107 = (0) ky = Hn Cox= (Bn = kin (W/D aS 13.11] By =k’, (W/L) with 10x10" (a) By = k’y (W/L) = 172.65(10/0.5) = 3.453 x 10°7 A/V?. The resistance is Ry = 111.39. (0) The resistance is reduced to leg = »{2uesoee) 9X8.854x10 | = 172.054/V? 1 R= : = 50.630 (1.726510 (22),.3-0.8) 18.12] (@) k’p= tp Cox 80 we caleulate 66.06nA/V" ‘The resistance is then given by R, 1 = 216.259 3, (6s.06xi0*(34)(3.3-0.8) [3.13] Start with Cox = S28 = 3.63x107F, Toe om? (2) k’g = Hp Cox 196.28 A/V? and K'p= tp Cox= 79.97 WA/V2, With the aspect ratios we have By = 6.73 mA/V* and B, = 2.74 mA/V? so that Ry = 56.1 Q and Ry = 142.48 Qusing the formulas. (0) Ry= 0.8 Ry 80 = 44.88913, - 3 B, = 8.408x10° = k, 33) 36.8 jum needed for the PFET. which gives the value of W 18.14] The function is Out = Bey w) ‘This leads to the following circuit. Ybp wed bs Problem [3.14]4 13.15] The function is bed aed od ve el pea Problem [3.15] F=abera-d=-a (bord) which is shown in the circuit below.15 [3.16] The OAl function is go = (@4b) (erd)-e This is obtained from the CMOS circuit shown below. The placement of the inputs has be = chosen to facilitate the layout. 7 i Problem (3.16) Circuit,16 18.17] Expanding gives a+b) [erd)-e acta d+b-c+b de erbcerb de cera ‘The third line is an expanded AOI form, but uses excess transistors. This can be seen in. the circuit below. Although we could do a somewhat messy layout, of the gate as-is, we can see by inspection that the expanded AO! form is not an efficient implementation of the logic function. Problem [3.17] [3.18] Yes, this is a functional gate. The function is f=abrerd as can be verified by tracing the circuft.7 13.19] We start with g- aber ‘The CMOS circuit and layout are drawn below. Yop vDD «eal, fbeo t+ a ee ao wef jhee eH Problem [3-19] Chapter 4 ‘There are no problems in Chapter 4. Chapter 5 ‘There are no problems in Chapter 5. However, the concepts can be illustrated by assign- ing layout problems using a CAD tool set. A suggested list of simple structures is, an nFET and a pFET with a minimum aspect ratio; scaled FETs; series connections that share drain/source regions for 2 FETs and 3 FETs; minimum size inverter; NAND2 and NOR? gates with standard size transistors; a simple AOI and OAl gate.18 Chapter 6 : 16.1] (a) The oxide capacitance per unit area is = For _ (8.9)(8.854x10) ak 345x107, = tee 100x10 cm’ pm [b) k'n = tly Cox = 189.92 HA/V? and k'p = tp Cox = 75.51 wA/V? C. 16.218, = 110 (10/.35) = 3.143 ma/V? (@) Vegi = 2 -0.7 = 1.3 V > Vpg= 1 V so the transistor is non-saturated. The current is Ip (4 8)easn-1 = 2.51maA (b) Now Vq¢= 2 -0.7 = 1.3 V (Bn/3) 3 (Via Vi Be V9 Vien z a) 12908) 2.4-0.55-)" « 63.16ua/v? 17.10] (@) The resistance of a FET is . 1 © (@x10°)(8.3-0.7) ‘The time constant for the output capacitor is obtained from the Elmore formula as 38R,Cout + 2RxCa+RaCy RylBCou¢#2C + Cy) 192.31[(3)180 + (2)36 + 36)x107* 95.77 ps Ra = 192.319 Th ee Rn Rn Rn C Problem [7.10] (by we ignore ©; and Cp, = 8R,Coys = 75 ps which gives a percentage error of % Exror $5.77-18) 199 99 « (2522575) x100 % = 21.6%25 7-11] The circuit and the relative device sizes are shown in the drawing. ee [te Bp 2B FETS on eter are cised wan Tx 9B Problem [7.12] 7.12] The circuit and the relative device sizes are shown in the drawing. Al nFETs hhave the same size B= 2 Bp Problem (7.12)26 Chapter 8 18.1] The general form of the rise time equation is 4 “te tet aC, so the information gives the two equations 123.75x10""* = t+ a(100x105) 138.6x10" = ty +.0(115x10""%) {a) Subtracting the top equation from the bottom one gives, 14.85x10"? = 0(15x107) 80 “ ) 99x10" 2.2R, ‘Thus, R, = 4509. (0) Use either equation to find to: 128.75x10"* = t+ 0(100x10"") = t,9 + 990(100%10"") so ty = 2475x107! = 2.2R,Cper- This gives 2475x0 _ Crop = PATO 5 os tr Thus, we can write the general expressions t, = 24.754 0.990, ps = ty where C; is in units of fF. (c) With a scaling factor of 3.2x., t,pis the same but a is scaled to (.99/3.2)=0.308. This ives the expression t 24.75 +0.309C, ps [8.2!The delay through the 3-stage chain is ta = 2t,+ty where t, = 430+8.68(45) = 595.6 ps ty = 300+2.56(45) = 415.2 ps so27 tg = 2(595.6)+415.2 = 1.606 ns [8.3]We estimate the delay by adding times ta = tynort tr.nore + ty. nanda + fr, nor where we assume that a switch occurs at every gate. Using the formulas for the specified mevalues gives ta = [tyo + GnulZCmin)) + [Bty9 + 2A pul4Cmuin)) + [Bt yo + VE pu(SCmin)) + [e+ #00C a] crewing te Atos Boe Cran bpp Pap Ca [8.4}{a) The input capacitance is Cin = CoxLW(1 41) = Coq(0.4)(2.2)(1 + 2.6) = 25.344 1F (©) The number of stages is 25.344x10™ 38x10"? ~ (sour) = 721 so we select N= 7. (©) The reference resistance 15 Ryym = 1725 2, 80 Rp.2.= (1725/2.2) = 784.1 @. Since CLF Logs 2 (Gif aa the total delay is 5 tq = NSt, = 7(2.85)(784.1)(25.344x10 for the simplified analysis. ') = 396.45 ps I8.5]We calculate the number of stages as Cx) - sa ( 402107") > m(ce) - re) so we select N= 6. The scaling factor is = In(800) = 6.6828 cyt s-(a) -9 ‘so that we start with B, (known), and calculate the driver sizes as = Bo = 3B; By = 98), By = 278, Bs = 81B,, By = 2438, [8.6]The line capacitance is Cun (0.86)(272) = 233.92 1F so the number of stage is w= (28322) « 15 52 is N = 2 for a non-inverting design. The scaling factor is estimated by _ (233.92\7 _ s= (7) = which is accurate enough for a rough design. Thus, if the first stage has a size 6, then the second (driver) stage has a size of 2.18. I8.71The transcendental equation is Sin((2)-1) = 0.72 ‘Trial and error gives S = 3.37. [8.8]We first calculate the path effort with r= 2.5 Fs t= sonal «(SSVSEV RR) «2 so that the stage value is 1 F = (34.64)* = 2.43 This is used to calculate the input capacitance to each stage, which can in turn be used to find the scale factors if desired. Starting with the last stage we have 2 nye P= 28 =e (10/2.48)€ = 4.12€ . For the third stage, 80 Cy29 2.43 ha 5 - BAS) 50 C, = 2.91C . For the second stage, hg = L = (248. 291 Sig ore (5/25) es 50 C, = 1.54C . For the input stage, 2.43 _ 1.54C i Oa ong o7a le acy so C,=C asrequired. {8.9]This path has a branching factor that we compute as = (2241) +(3B)+r) | 1342r @Q)+1) “Ger B ‘The path effort is then F = GHB = 9,9,BgsH so that the stage value is, 2 J = (104.66)° = 4.71 ‘This is used to calculate the input capacitance to each stage, which can in turn be used to find the scale factors if desired. Starting with the last stage we have 7a = 0G 6/35) °C $0 Cy = 8.64C . For the second stage, hy = ot 4am 3.640 bag, ~ @77V45735) ~~ Cy 50 C, = 2.75C . For the first stage, hy i__471 _3.64c © ag sl a which gives C,30 {8.10]The circuit is shown below. Q1 Ma 7 1" Cour7R Vout vi Problem [8.10] ae ‘The output swing fs computed from Von = Voo- Var vee as Voy because the nFET allows the output to discharge to 0 V. I8.11}The NOR2 circuit is shown below. It illustrates how the static gate is used to drive the upper BJT, while only the nFET logic section is needed for the lower BJT. Ypp Problem [8.11]31 [8.12This is designed by using the static CMOS gate to control the upper bipolar output transistor, and the nFET logic section between the base and collector of the lower BUT. ‘The lower BJT also has a pull-down FET on the base to drain off charge. Vp Problem [8.12] = [8.13] We can wire a pair of FETs at the output (although this introduces other prob- lems). Problem [8.13]32 Chapter 9 {9.11 (a) Yes. The circuit is shown. It is based on the symmetry in the truth table where 2 input combinations yield a 0 output, while the other two give a logic 1. 7 Yop ae pao Fe poe f | Fez bey 1 Problem [9.1] + (0) No, this is not an intelligent choice (although it s an iteresting circuit). Why not? Use the function table to write the SOP expression so no gate is needed at all! This is a useful point, as some may try to build a complicated logic gate without looking for the simplest solution. 19.2] For the standard circuit, we use the RC equivalent shown in (a), while the charge chain for the mirror cireutt is shown in (b). The difference between the two is effect of the 48 fF capacitor: it is shared with the other branch in (a), doubling the value at that node. Rp Rp Rp Rp == Cx == Cout (a)Aotnas 2Cy due (©) Mirror only has Cx. to other 2 pFETs Problem [9.2] ‘The resistance is (250x10" ( For the standard circuit,tay = 2.21(2R,)Cou¢+ 2R,Cpx] = 1.8nS (i For the mirror circuit, thy = 22U2R,)Court RyCpx) = 1.3205 19.3] (a) Using equation (9.3) of the text allows us to write By Vpp- Wn a5)? Be 2Vpp-Vin)Vor- Von 2(4.8)(0.3)-(0.3)" ‘This means By _ g.o9 2 —Kal4)_ 20,4) 3,” °°? = ECW7D, * BSNW7Ly, so that the pFET aspect ratio must have (W/L), = 1.26. (b) Now we have so Note that this is too large to be interpreted as a logic 0 as the input to an identical stage. [9.4] The NOT gate is defined by By _ 120(W/L)y 3,7 58) which gives (W/L), = 6.34. For a NAND2 gate, the each nFET should have an aspect ratio of (2), =X), 208 while a NANDS gate would use nFETs of size To compare the area, let us normalize the channel length to L= 1 unit and compare gate areas. For the NAND2, the gate area of the nFETs is A = 2(12.68) = 25.36 square units while the area of the nFETs is A = 3(19.02) = 51.06 square units = 6.9234 Since the pFET sizes can be the same for both gates, this illustrates that the nFET gate area will increase by a factor of about 2 when a NAND2 gate is changed to a NAND3. [9.5] The circuits are shown below. Problem [9.5] [9.6] The AOI and OAI cireuits are shown below. The OAI will have a slower discharge because of the higher capacitance at the node indicated, so the AOI is preferred for fast switching (ty). a - ow = P| pee a pe a Problem [9.6]35 [9.7] One circuit is shown below. ‘The input logic forms to variables that control the output FETs Qp= F-D=T+B 9, = THD = 7-3 When T= 1, gn=0 (which turns off the nFET) and gp = 1 which turns off the pFET. When T= 0, the control signals are gq = D= gp . If D=O, then the nFET is on and the output is 0, while D= 1 turns on the pFET at gives a 1 at the output. [9.8] A C?MOS circuit for the function ST bey is constructed by designing a standard CMOS logic gate, and then inserting clocked transistors between the output and the respective FET logic arrays.36 Problem [9.8] [9.9] The leakage is expressed by Vout ~ Cou Gee which has the solution = ~ Be, Vout) = Vou(0)~ ett Hold times are computed by solving for time: t Cout Vpp(0)- V; n= (FE) Mp0l0)- Val where V; is the minimum logic 1 voltage. (a) With the values given ( 76x10" .0.46x10°°-0.127x10°) (b) Repeating with a lower power supply voltage gives the |s-21 = 593.4 ns ty (—Be* _|joo-2 4] = 208.41 ns \0.46x100,127x10°°) ‘The hold times are short because of the small capacitance and the relatively large nFET Teakage current state.37 [9.10] (a) We start with the capacitor I-V equation in the form ten)» Oot then rearrange and integrate: = Solving or V(t) = Voe’ where the time constant is CourVo "7 “E (b) Write = Cou ‘3 For the hold time, V{tj) = 0.4 Vgso CourVor,(_Vo. Cour CouVo, ty = Selene) = Seueincas) = Seu" 0 6) is the estimate.38 19.11] The dynamic circuit is shown below. Ypp pen aed pec f ay ep lhe Problem [9.11] [9.12] The dynamic circuit has the usual structure: an nFET logic array sandwiched between a clocked complementary pair. Ypp pec pe b aed pea : F | i | ae Peo Problem [9.12] aol [9.18] The total charge in the initial configuration is, Q7=5(100) = 500 fc so equating this to the final distribution gives39 r= (100 + 37)¥;= 500 fC Solving, ¥; <(}Q0)s = 998 v [9.14] (a) The charge sharing calculation is. Or = 2(87)Vinax = ((87)(3)+851V, .25 V (ignoring body bias). Then where Vinax= = (74 = vy = (FA)aas = 1.00 v (b) For this problem, note that only the charge on two of the initially-charged capacitors contribute to the final sharing problem. Equating initial and fiinal values gives Or = 287)Vinax = ((87)(2)+85]V, which gives Vj= 1.98 V. 19.15] Construct the logic arrays separately, then embed them in the general circuit. ‘This gives the circuit shown Problelm [9.15]40 [9.16] Using the technique discussed in the book, we start with the general tree and then reduce. The pairs marked in bold X's are eliminated because the input pairs are identical. The resulting nFET tree has only 4 pairs. Translating the tree to circuits and adding a pFET latch gives the final circuit. Problem (9.16] = Chapter 10 It should be noted that there are usually several ways to construct the Verilog code for any given problem. The solutions listed here are written in the style introduced in the text. 110.1) ‘module Prob_t (F1, F2, a,°b, ¢, d); input a,b, c,d; output F1, F2; wire wt : nor (F4, a,b); and at (w1, a,b, ¢) ; and a2 (F2, w1, d) ; ‘endmodule [10.2] module Prob_2 (out_1, out_2, a, b,c); input a, be;al output out_1, out_2; wire wi; xor (wt, aD); xnor(out_1, wi, ¢); and{out_2, a, b,c); endmodule 110.3} module sr_nand (out, not_out, in_t, in_2); input in_t, in_2 ‘output out, not_out; nand #2 g1 (out, in_1, not_out), #2 92 (not_out, in_2, out) ; endmodule 110.41 module decoder (d0, d1, 2, 03, s_1, $0); input s_1,s_0; output do, d1, d2, Wire not_s0, not_s1 ; not #1 invO (not_80, 80) ; not #1 inv (not_s1, $1) ; and #2 a0 (d0, not_s0, not_st) ; and #2 at (¢1, s_0, not_s1) and #2 a2 (02, not_s0, s1) and #2 a3 (43, $0, s1); endmodule42 [20.5}The circuit diagram for the static gate is shown in the drawing. The FETs are Problem [10.5] labeled to identify them in the code. module AOI_gate(f, a, b,c, d) ; input a, b, c,d; output Wire wot, wn2, wpt, wp2 : supply1 vdd ; ‘supply0 gnd : nimos nt (1, wnt, a), ‘2 (wn1, gnd, b) , 1n3 (wnt, gnd,), 1 (f, wna, ) 15 (wn2, and, d) ; pmos p1 (f, vdd, a), p2 (f, wpT, a) , 3 (wp, wp2, b), 4 (vdd, wp2, d) , pS (vdd, wp2, b) ; endmodule .43 [0.6}The circuit diagram for the static gate is shown in the drawing using FET labels to help write the Verilog listing. Yop pale epee prea pap module AOLgate_ex (F, a,b, 6, d, 6); input a,b, c,d, @; output wire wnt, wn2, wpt, wp2 ; supply! va suppliyO gnd ; amos nt (f, wnt, a), 12 (wnt, gnd, ¢) , 113 (wnt, gnd, e) , 14 (wnt, wn2, b) , 15 (wn2, gnd, ) ; pullup (f) ;// This is a simple resistor model in piace of the pFET I" The pFET would be included using mos pt (f, vad, 0); in the code in place of the pullup */ endmodule : [10.7]The TG MUX listing is constructed below. module CMOS_MUX (F, pO, pt, s, snot); input pO, pt, s, s_not; output F cemos #2 tg0 (F, pO, s_not, 5); cmos #2 191 (F, pt, s, snot); endmodule44 [10.8] module two_phase_clock (clk, clk_bar) ; output clk, clk_bar; = feg clk, clk_bar ; 7 intial clk = ~ elk_bar; ‘olk_bar = ~ clk ; end ‘endmodule [10.9]We will write this in a style that illustrates how descriptive levels can be mixed. module logic (q, a, B,¢, €,1) output f; input a, b,c, e, 1; reg clk; not nt (a_bar,a), 2 (c_bar,¢); assign ‘A= (abar & b) | (¢ &e) | (¢_bar & 1); ‘endmodile ‘module clock (clk) ; reg cl initial clk =0; always begin #5 lk, end endmodule module dtf (q, A, clk) ; output q ; input A, clk ; always @ (posedge clk ); q=A; endmodule45 Chapter 11 [21.1] (@) The TG mux circuit is shown below (taken from Problem (2/14), po pl p2 ps Problem [11.1] (a) module TG_MUX (f, p0, pt, p2, p3, s1, s1_not, s2, 82_no!) ; input pO, p1, p2, p3, 81, s1_not, 82, s2_not ; output f; wire WO, wi, w2, W3, ‘emos tg0_0 (pO, w0, st_not, s1 ); ‘emos t90_1 (f, WO, s0_not, 80); ‘emos tg1_0 (pt, wi, S1_not, st); comos tot_t (f,w1, 80, 80_not); ‘omos tg2_0 (92, w2, 51, s1_not ); cemos tg2_1 (f, w2, s0_not, 80) : ‘omos tg3_0 (p3, w3, 51, s1_not ); ‘emos tg3_1 (f, 3, 50, 80_not ); endmodule (c) Each path has two series-connected TGs giving the equivalent circuit shown below. ‘The value of 2C in between the resistors is due to a C contribution from each side. The output capacitance Coy: Consists of the right side of 4 TGs (one from each path) and the external load Cy,48 Cour 40+ Cy Problem [11.2] (¢) ‘The time constant for a path is Tn = Cou2Rra) +(20)Rro (CL +4C\2Rrq)+2CR ro 2RygC,+ 10RpgC ‘This indicates that the TG circuit may be slow. The actual values depend on the aspect. ratios and process parameters. [11.2] For a 16:1 MUX, we may use a high-level approach to obtain the following. module mux_16 (out, sel, 0, p1, p2, P3, p4, P,P, p7, PB, p9, p10, p11, p12, P13, p14, p15); input pO, P1, p2, p3, pé, P5, PS, 7, PB, p8, p10, p11, p12, p13, p14, p15; input[ 3:0] sel; output out assign out 20000) ? po : 20001) ? pt : 20010) ? p2: 20011) ? p3 20101) ? pS 20140) ? ps: 21000) ? pB 21001) ? pg 2’p1011) 2 ptt 21100) 2 pt2: endmodiulea7 GUM ga Tr eee $150 roto }- Pil ~ $2 P22 res 0 150 i bes mato Pa) 2 Problem {11.3} pods (0) The easiest implementations are the NAND circutts shown in Figures 11.1 and 11.4 of, the text (not reproduced here). TGs could also be used, but they will be harder to apply to the Logical Effort calculation in part (c) of the problem, (c) Using the NAND gates. the cascade is a NANDS to a NAND4 (for a 4:1), and then a NAND2 to a NAND2 (for the 2:1). The cascade is shown below. a 10 Cay Problem [11.3] Cascade ‘The input to the NANDS gate is C,. We can write GEG where we have assumed that r= 2 for simplicity. The electrical effort is G = 91929394 5.926 : CG so For a NANDS gate, the input capacitance scales as (3x 3+7)Cynye- If we define the NAND3 unit a5 Cyn: = Ciny We obtain = (2228) - 152 IT which provides all the values needed to complete the Logical Effort scaling of each stage. To complete the problem, we work from the last stage towards the input.48 114 E152, 976 - 7:89Cinw meng. 67g 07 = Ce $0 Cigg = 10.22C pp. Finally, j 10.121 het o.9i2 = 10:12Cinw a Cina gives us Cia, = 11-1Ciqy- These values. along with the input capacitance equations, provide the sizing of each stage in the chain. [11.4] The 7G circuit is shown below. Note that pull-down resistors are used at the out put to insure that the voltages can reach 0. S Fe Bee Problem (11.4) For the Verilog listing, we can write49 module TG_decoder (40, d1, d2, d3, s1, s1_not, 52, s2_not) ; input s1, st_not, $2, s2 not output do, dt, d2, 03; wire WO, wi, w2, 3, wp; supplyt vd ; ssupplyO gné mos pu (vdd, wp, gna); Cemos tg0_0 (Wp, WO, $1_not, S1 ); ‘cmos tg0_1 (40, w0, sO_not, sO); ‘emos tgt_0 (wp, wi, S1_not, $1): ‘emos tgt_1 (d1, w1, 80, 80_not ); ‘emos t92_0 (wp, W2, st, S1_not ); ‘emos tg2_1 (42, w2, sO_not, 80) : emos 1g3_0 (wp, W3, 51, s1_not ) cmos tg3_1 (43, w3, s0, 80_not ); pulldown (40) , (61), (42), (43) ; endmodule [11.5] The simplest way to design this is to just add inverters to an active-high circuit! Une De bee a tr) Do dp Problem [11.5] 1 7 (a) The Verilog listing is module decode_4_low (d0, d1, d2, 43, s0, st) ; input s0, st ; output dO, d1, 02, d3 ; Wire WO, wt, w2, Ww ; nor (w3, ~s0, ~s1), (w2, ~80, 1), (wi, s0, st), (WO, 50, s1); not (d0, w0 ),(6t.w1), (a2, w2), (23, w3 endmodule : (b) To modify the circuit to include an enable control, we can expand the NOR gates to 3- inputs and add the En to each. When En =1, every output is at a logic 1. Alternately, we could put tri-state not gates to isolate the outputs. The variation on either is straightfor- ward and not shown explicitly here. 111.6] The circuit shown here uses dynamic logic and is based on the logic diagram in Figure 11.4(b). Four NANDS gates are used for the inputs (only one is shown in the cir- cuit) to produce outputs gO. gl. g2. g3: these are fed into a NAND4 gate which has the MUXed output f. 4 NAND gates produce g0. g1. g2. 63 Problem [11.6]51 {11.71 A design for the switching array is shown below. This combines thé rotate right Ro.0 — RoANR/D RolwR/L) Ro Ro. 8e(R/L)Ro.SelR/L) cht oS et ct % oh ce) a cel fo wm AU AT AU] A AT fs I Problem (11.7] and rotate left arrays and eliminates the redundancy for rotate 0 and 2. The control sig- nals can be produced by a simple active high decoder with the outputs ANDed with the (R/D signal to specify right or left rotation. 111.8] A structural listing is a little tedious, as it shows every gate and connection. module equality (Equal, a,b); input [7:0], b; output Equal ; wire WO, wi, w2, WS, w4, WS, WG, W7 5 wire wa, wb ; xnor gO (WO, af0}, bf0}), * 91 (w1, at], b[1]}), 92 (w1, al2), bi2) ), 93 (w2, a[3}, b[3} ), 94 (w4, ald], bl4]), 95 (w5, af5}, bIS) ), 96 (w6, a[6), b(6) ), 97 (w7, a[7], bI7} hand m1 (wa, WO, wi, w2, w3 ); rand n2 (wb, w4, w5, W6, w7 ); nor (Equal, wa, wb 0; endmodule52 111.9] This listing is a high-level description that uses a 4 bit register called bit_reg that stores the bits operations are ‘and then shifts with the clock edge. The Verilog concantenation and shift used to achieve the bit movement module shitt_reg_4b (d_out_in , clk ) 2 input d_in, clk output d_out ; reg [0:3] bitreg ; assign d_out = bit reg{ 3}; assign @ (posedge clk ) begin bit_reg <= { Lin, bit_reg{1:3}}; end endmodule Amore straighforward approach is to define a DFF module and then instance it into the structural code. For example module aff (9, 6, ck); input ¢, clk; output always @ (posedge clk) a=d; endmodule module shitté (d_out, c_in, clk); input d_in, cl output d_out ; wire WO, wt, w2 5 reg WO, wi, w2, d_out: df 90 (w0, d_in, ok); aff gt (wt, WO, clk ); aff g2 (w2, wt, ck); ff 93 (d_out, w2, clk); = endmodule (b) A CMOS switch-level circuit is shown below. Problem {11.9} clk_bar clk a a 4 aTh mS a oa T rs clk clk_bar53 (©) For the FF shown, we can define one module by ‘module cmos_dif (qd, clk, clk_bar); input d, clk, kbar; output reg nimos (w', d, clk_bar ); not gt (w2, wt); riot g2 (wt, w2); ramos (w, wit, ck); rimos (W2, d, ck); not 93 (q, w2) not 94 (w2, q) mos (w3, wi2, lk) ; endmodule ‘This can be instanced into the shift register by allowing for the clk_bar signal. 111.10} A simple listing is module regBb (4, 6, ok, En ); output {7:0 Ja; input [7:0] input clk, En; reg[7:0]q initial q = 0; always @ ( (posedge cik) and En ) ‘ondmodule [11.11] The code below uses resistive nmos switches since the transistors are used as, pass devices. module register (Qa, Qb, D, WE, Re_a, Re_b); input D, WE, Re_a, Re_b ; output Qa, Ql; wire win, ws, Wo : mos (win, D, WE ); rot gt (ws, win), 92 (win, ws ),g3 (Wo, ws }; rmmos (Qa, wo, Re_a ); mos (Qb, wo, Re_b ); endmodule54 Chapter 12 [12.1] The simplest gates are shown below. Ypp aA ze4 Hee Fe He? Problem [12.1] ok ‘These can be described by the following Verilog listings. module sum (sum, a,b); input a,b; output sum ; wire wnt, wn2, wn ; supply va supply0 gnd ; ramos nt (sum, wnt, ~2), 12 (wnt, ond, ~b) , 13 (sum, wn2, a) , 14 (wn, and, b) mos pt (s, vad, gnd) endmodule module carry (c, a,b); input a, b; output o; wire wnt, wn2 ; mos n1 (wnt, wn2, 2), 12 (wn2, gnd, b); mos pt (wnt, vad, and); mos n3 (c, gnd, wnt); mos p2 (c, vd, and) ‘endmodule55 {12.2} (a) The CPL circuits needed for the sum and carry are shown below. el a es al ae a5 ‘Sum circuit Cany circuit (b) A Verilog description for a two-input array is as follows module CPL_2 (f1, 12, A, B, C, D); input A, B, C, D; output f1, 12; nmos nt (A, 11,4), 1n2 (wn2, gnd, b) ; mos n3 (¢, gnd, wnt), 14 (wn2, gnd, b); ‘endmodule56 [12.3] (a) The static circuits are Ypp Yop aed p* ~ bed po % ae * Fe He Problem (12.3) (a) (b) Domino designs give a similar structure Yoo Yoo » % ae He % ae —| en a ye ° ‘ Problem [12.3] (0) (c) The TG designs are based on a 2:1 MUX design (although others are possible). Note & Problem [12.3] (b) that the generate circuit produces an output of aif b= 1, and an automatic output of 0 if by= 0. This is the AND operationYpp Problem [12.4] ot Fo to: toe58 112.5] The mirror circuits are constructed as shown in the figure. arf Borah ond co Po ri Po [p+ Po Heri Problem [12.5] pr Po Pa Hpo1 dre dros [12.6] Sizing enters the problem when @ = 0 and p=las shown in the left side of the drawing, Eliminating the FETs that are OFF yields the pseudo-nMOS circuitry shown on the right. The ratio of FETs M1 and M4 determines the output voltage Vout for Ge Problem [12.6] Ideal value isOV We5 59 will assume that the propagate voltage representing p; has an ideal value of Vix = Vpp + and that = 0 is a perfect ground, To design the circuit, we use the pseudo-nMOS ratio equation for a reasonable value of Vor say. Vor = 0.2 V. : - Bas (Voo-IWrd)® (2.3)? Bos 2(Vpp-Van)Vor-Vaz 2(2.3)(0.2) - (0.2) 6.01 ‘This means: Bat < 6,9) = Ka(W/bim _ W/Lna Boe EW Dye ~ (W7D) pe so that the two are sized according to (W/L)qy = 2A(W/L) pg ‘The values will changed if the input conditions are different, but the procedure is the same. [12.7] (a) The evolution of the ladder is shown for the case where the carry-in propa- gates all the way through the chain. If any generate bit is a 1, the corresponding propa- gate bit is a 0 and the carry chain is opened. () Since every stage precharges at the same time, the voltage at Z is Vpp corresponding toa carry-out of cy = 0. ‘The g-input nFETs — | are off for a propaga- tion event Problem (12.3](a) (c) Suppose thatp,= 1 and gi= 0 for all i Every node must store charge and is subject to a charge leakage from the OFF transistors. However, in this case the input bit Gp is pro- vided by a static inverter (see drawing in the text) which provides hard support to the power supply or ground. The inverter is able to maintain the value on the right side of ‘the chain so that charge leakage will have minimal effects. If the propagation is stopped60 ‘ 1, the Gj. = 0 through the nFETs, and this provides a at any point with pj= 0 and connection to ground. [12.8] Using equation (12.37) we have Average carry chain length = logo(64) = logo(25) = 6 bits : Average carry chain length = logg(128) = logo(2”) = 76 bits [12.9] The block diagram is shown. Each 4-bit group produces a carry-out bit that 1s used to select the next 4-bit group. <1512>m <11,5> in <74> in spar aay siti, piranst aon ‘biadder fo [abitadder bo [-bitadder }o 2 Le A wart tio tae} He ‘abitadder } eo 11 Teale ebitadier }! | [amtadder } |[anader }? 5 tn waa qeaaeie | ara 15.25 in isin Gain <15,12> sum <11,5> sum aan cas {12.10} A block diagram is shown. eee 111 tf Regatr — 3—y 7 % bo x} UY © {ria el ra 7 Problem [12.10] Ps Po A ‘The Verilog module can be written in various ways depending on the amount of structural detail desired. A high-level description of the basic array is quite simple:61 module 2x2_mult (p, @,®); input (1:0 ]a, 0; output [ 3:0] assign 2 pearb; endmodule Alternates include bit-level or function level descriptions. The input latch can be added with a clocking signal. There are a large number of multiplier descriptions that can be constructed, and the interested reader is directed to the literature. [12.11] An 8 x 8 multiplier would have the same basic form, but cannot easily be con- structed using the 4x4 as a primitive. This is due to the fact that the 8x8 would require that the HA and FA locations altered depending upon their bit locations in the array. The basic cells (AND, HA) or (AND, FA) could be used. Note that the 8x8 will exhibit a long ‘worst-case delay due to the increased length of the critical data path. 112.12] For an 8x8 array multiplier, we use the simple block placement demonstrated in the 4 x 4. The placement of each cell in the matrix implies the connections. For example, the upper right corner cell has inputs ap, by and multiply to produce po. The first diagonal in the upper right has a cell with inputs a), Bo and another with inputs ag, by to produce do, There are also implied carry-out bits from one diagonal to the next. This illustrates how basic cells can be tiled to create the array. Fy Ge Os Oy Oy ay cp [- PERPFTS PisPiePisPi2Pi1 PoP Ps62 112.18} (a) for 10110011 the encoded digits are determined by writing 101 110 001 110 giving -1, -1, #1, - (b) 01101101 is parsed as 011 101 110 010 to give +2, -1, -1, +1 {€) 01010010 is parsed as 010 010 001 101 to give +1, +1, +1, -1 a Chapter 13 118.11 \6T cell ‘module ram_6T (bit, bit bar, wordline) ; input bit, bi_bar, wordline; output bit, biLbar ; wire wat, wa2 ; supply va suppliyO gnd ; rnmos nat (bit, wat, wordline}; inmos n1 (wal, gnd, wa2); mos pt (wat, vd, wa2); Amos na2 (bit_bar, wa2, wordline); inmos n2 (wa2, gnd, wat); mos p2 (wa2, vdd, wat); endmodule N4-T cell ‘module ram_4T (bit, bit_bar, wordline) ; input bit, bit_bar, wordiine; output bit, bit_bar; wire wat, wa2 supply1 vad ; : suppliy0 gnd ; Amos nat (bit, wat, wordline); mos nt (wat, gnd, wal); pullup (wat); Amos na2 (bit_bar, wa2, wordline); Amos n2 (wa2, gnd, watt); pullup (wa2); endmodule ——. Sec —{13.2] The Verilog statements are quite simple. reg [31:0] mem[ 0: 2047); reg [7:0] storage [ 0: 16383}; reg[7:0] file [08191]; = 2 (18.3] Yes. This is because the complementary input will aid the cell in swtiching states. This design is actually used in many commericial SRAMs to conserve layout area Laisenarges Vp 10 OV, which helps swatch the cell Problem (13.3) pulldown state [13.4] This is an open-ended problem. The difference between the two designs is that a single gate drives a very large load capacitor and will have to be driven by a scaled chain to be fast, while a DWL architecture splits up the load into several gate/load groups and can be scaled accordingly. With a scaled design where B < By < By < etc. and the delays (a) Single drver Cig laree c large () DW design Problem (13.4) (including all contributions due to the sub-lines) are equalized, then the equations of Logical Effort provide the design criteria.64 113.5] A simple solution is to change the wordline signals applied to the access transis- tors to mutually exclusive control bits of WL1x and WL2x that are generated by basic AND logic. \ z =o Problem [13.5] a wt WL? [13.6] (@) The maximum charge that can be stored on the capacitor is Qnax = CeVmax = (55x10)(3.5} rs so the mumber of charges is 1.925x10 since one electron has a charge of @. () The leakage current is 75 nA. This means T= 75x10 so the rate of electrons Jeaking in 1 second is seo? 18x10 = 4.68x10"" [electrons/second] L.602%10 (©) The time required for the # of stored charges to be reduced to 100 is approximately : ° = AN J 120x108 100 _ 9 57y6 Tw 4.68x10 [28.7] (a) The maximum stored charge is Omar = CeV nar = (45x105)(8.8-0.55)= 1.24x10 © (b) The minimum final voltage after leakage and charge sharing is given as v= 15 = (Se \vsl) = (S8)vceo so the minimum stored voltage is65 vatty) = (22). = 983v In other words, the V;value Js too high (the cell will not work)! This problem was included to show how dificult it is to actually store a voltage in a DRAM cell. It usually ~ amazes the neweome how much charge sharing drops the voltage. Suppose instead that we drop the requirement to a more reasonable value of say Vp = 0.2V. In this case, we would have vate) = (BE which is possible. Using this value, we estimate the hold time using (0.2) = 1.31V _ 45x10" = (1.44) = 0.864us 75x10 118.8] The initial voltage at time t= 0 is Vmax= Vp - Vmn=3-0.65=2.35 V. The change in the stored voltage for a given time increment At is 250x107, a (At) = 4545.45(A¢ sono ao so the capacitor loses all of its stored charge after a time I aVe = g(a) = 0.517 ms ms.V,= Vj= 0 V. Note that even if the leakage is reduced to 0.25 pA. the charge only lasts for 517 ms. The instructor may want to have the students plot retention time for various leakage cur- rents. This usually builds an appreciation for the problem faced by DRAM designers.68 113.9] The logic diagram is shown below. Problem [13.9] Logic rere th abe ‘This can be translated into a CMOS NOR-NOR-NOT in a straightforward manner. The logic diagram shown illustrates the structure. & th in m. my Problem [13.9] NOR-NOR67 113.10] The OR-AND array is shown below. Problem [13.10] To implement this in a pseudo-nMOS basis (where NOR gates are easier), a straightfor- ward approach fs to use NOR-NOR cascades. The second NOR can be reduced to an an AND gate with assert-low inputs (via DeMorgan); the assert low inputs are restored by the input NOR gates to produce the same OR-AND sequence. [18.11] The basic AND-OR design is shown. i 1m Problem [13.11] Logic68 7 : ‘The NOR-based logic provides a basis for a CMOS implementation. To J Problem [13.11] NOR Logie ¥YY¥Y ff 113-12] The NOR-NOR implementation of the OR-AND PLA is shown in the logic dia- ‘gram below. This can be translated to a CMOS network (using dynamic NOR gates) in a straightforward manner. Problem [13.12]69 [13.13] The circuit diagram is constructed by using the FET locations as shown below. wee @ % 1-3] 4] al > oo! py © Y 2, a =| fe 8 8] Problem 13-13] : ot = > > 113.14] The wiring is shown below. This follows the layout strategies introduced in Part 1 of the book. .70 Chapter 14 114.1] (a) The parallel-plate formula gives EoxW _ (3.9)(8.854x10"*)(0.5x10*) p13 187x107 F/em Toe Lao or we can change units to ¢ = 0.187 pF/em (©) With fringing effects, io toa. e= toft.as(e)+20(¢)""] . Fy 15/25 019°? = aayeesoao™[1.15($4) +2.9(22) 7 = 1.105x10"? F/em= 1.105 pF/cm (©) The error incurred by neglecting fringing is = (1:108-0.15: E % Error = (1455 9-157) x 100 =85.79 9 ‘This large error arises from the condition t > w, so the fringing fields are a major contri- bution, It also illustrates the point that fringing capacitance is a major contribution in fine-tine VLSI. (@) For the line capacitance we have Chine = el = (1-105%10 ‘The line resistance is computed as (10x10) = 11.05 8 a « Run = (008/228) = 160 where the number of squares is n= (W/w) 114.2] (@) The capacitance per em is £02 c te 19(2)+2¢(-4) *) A - yas. = casyessen™fias(238) 26(23)] = 1.165x10" Fyem (b) The line values are 32, Chine = Cl = (1165x107 )(48x10) = 5.592 F andnm Ripe = Ran = (0.05)( 855) = 6.860 (©) With m= 7, the individual rung elements have values of tne = 0.80iF Rr, = Rie 20.982 c, tp 7 which gives the ladder shown. 0982 0.982 0.982 0.982 0982 0.982 0.982 OA “per Posw posm pose Problem 14.2 ‘The time constant is mom+1) 78) ae 2 Using the simpler equation gives a larger estimate of 1, RinCm (0.98)(0.8x10"") = 0.022 ps RuneCune = (6.86)(5.592x10""*) = 0.038 ps [14.3] With CMP, the thickness of a metal line is equal to the oxide thickness next to it. This allows us to find the oxide thickness for each layer. ‘The answers to this problem vary with the line width w, which was omitted to allow different values to be selected. In the solutions, we will take w = 0.35 um for every layer, but the instructor may wish to change the value(s) to describe a different process. For M1, Toy = 1-1 um and ox stage) ea gh) = (8.9)(8, asaxio™[1.15(S5°) +2. 3) = 0.965 pF/em For M2, Toy = 1.1+ .58+1.2 = 2.88 um and c= oys.esenr"[1.9( 223) «2.0(229)"] = 0.820 pF/cm72 For M3, Tay = 2.88+.68+1.2 = 4.76 um and ce (3.9)(8.854x107)[1.15(; = 0.657 pF/em For M4, Tox = 4.76+ .68 + .90 = 6.34 um and ce (s.9y(8.8540x10"[1 15( = 0.611 pF/em ‘This shows the decrease in capacitance per unit length as metal interconnect lines are added. [14.4] ‘The overlap capacitance per unit area is estimated using Son 2 Cov = a= Fem where the oxide thickness is determined by the metal-metal oxide. For M1-M2, (3.9)(8.854x10"* (2x10) Cov 2.88 nF/cm? = 0.0288 F/um? For M11-M3, = 1.12 nF/em? = 0.0112 #F/um? 114.5} (a) The line capacitance per unit length is (10,000 1 micron) = (8.9)(6.95440)[1.15(222) + 2.0(28) “| 1.072 pF/em* so Chine = el = (1.072x107)(122x10) = 13.08 ‘The line resistance is (b) For m= which gives a time constant of73 For m=6, : so that, mine Dp, ce = 22)(0.465)(1.09x107) Since the delay has differential origins, this is more accurate than the m=2 case. 0.011 ps 114.6] {@) The line resistance per unit length is Re, 0.008 . 998.57 a/em ae 95)" e) | while the capacitance per unit length is c= 3.9)(6.85a00") 18( = 1.034 pF/em (b) We write 0 squaring gives t= 2.37x10%2* (0) With lengths of 100, 200, and 300 microns, we have thoo = 2.37x107%(100x107)? 2.87 ps taoo = 2.37x10°°(200x107)7 46 ps typo = 2.37x10(300x10)” = 21.29 ps [14.7] (a) The coupling capacitance per unit length is [oo -om(g.)-004 [8 sofo0n()°089{z5)-007(s5) (33) 6.91x10 Ce 138 F/em?74 (©) For 20 um, the coupling capacitance is C, = 6.91x10""(20x10) = 1.38 F For 30 jum, the coupling capacitance incfeases to a 13, C, = 6.91x10"*(30x10%) = 2.07 fF [14.8] (a) The line capacitance per unit length is © = 8.9(6.854x10"[1.19(928) « 2.0(988)""] = 0.978 pF/em (b) The coupling capacitance per unit length is terfo os( 52) +0. 89) =o. ong py afooo 2) 0eS)-00( 3) (a3) 7.967x10"° F/cm? (©) The capacitance per unit length 1s c + 2ce so that the total capacitance seen into a line Cyq = (0.978 + 0.797)x10"™ (18x10) = 3.194 fF 124.9] (@) The line capacitance per unit length is € = 3.9(8.0540 = 1.089 pF/em so that the line capacitance is Cine = 1.089x10 (50x10) = 5.45 fF ‘The line resistance is = 0.008 52 Rine = 0.008 22° (b) With s = 1.5, the new width and length are w = 0.267 um and 1 = 33.33 um while the other parameters are left the same. We thus recalulate the values as 0.6252 ¢ = (@.ye.asen0™)[1.15(2287) .2.9(288)™) 1.086 pF/em75 so that the line capacitance is 036x107 Cuine = (83.33x10) = 3.45 F The line resistance is invariant: [14.10] (a) v{z.t)=Vpp erfe(0.9) = (0.2031) Vpp- (0) We have c= (3.98. asaxi0™)[1.15( 55 = 0.566 pF/em and or 1.4x10"°2? sec = Bz™ where zis in cm. This case must be used with care, as the large value of = 0.9 indicates avery small voltage. [14.11] ‘The forward trigger voltage is + _ 3.34 /6(0.7) vt = 884607). asy 1+ 6 and the reverse trigger voltage is + , 448.3-0.8) vy: = 4438-018) 1+ Le7V76 114.12] For V* we rewrite the equation as f- ve Bs VV a so for V* =3.9 V we need a device ratio of For the reverse-trigger voltage we have & vo Bo Vpp~|Vrel~V" sowe have B, 12 > Be (s=08-13) = 0.16 Chapter 15 ‘There are no problems in Chapter 15 Chapter 16 ‘There are no problems in Chapter 16