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Clockless Chips: A Seminar Report ON
Clockless Chips: A Seminar Report ON
ON
CLOCKLESS CHIPS
ACKNOWLEDGEMENT
At the outset, I thank the lord almighty for the grace, strength and hope to make
our endeavor a success
We express our deep felt gratitude to Dr.x , Head of the Division
of Computer Science for his constant encouragement.
I am profoundly grateful to Mr. x , Lecturer, Department of Computer
Science, my mentor and seminar guide for his valuable guidance support,
suggestions and encouragement.
I would also like to thank our staff coordinator, Mr. x for his
words of support.
Further more I would like to thank all others, especially our parents and
numerous friends. This project would not have been a success without the
inspiration, valuable suggestions and moral support from the through out its
course
ABSTRACT
Clockless chips are electronic chips that are not using clock for timing
signal. They are implemented in asynchronous circuits. An asynchronous circuit
is a circuit in which the parts are largely autonomous. They are not governed by
a clock circuit or global clock signal, but instead need only wait for the signals
that indicate completion of instructions and operations. These signals are
specified by simple data transfer protocols. This digital logic design is
contrasted with a synchronous circuit which operates according to clock timing
signals.
The term asynchronous logic is used to describe a variety of design styles,
which use different assumptions about circuit properties. These vary from the
bundled delay model - which uses 'conventional' data processing elements with
completion indicated by a locally generated delay model - to delay-insensitive
design - where arbitrary delays through circuit elements can be accommodated.
The latter style tends to yield circuits which are larger and slower than
synchronous (or bundled data) implementations, but which are insensitive to
layout and parametric variations and are thus "correct by design."
Unlike a conventional processor, a clockless processor (asynchronous
CPU) has no central clock to coordinate the progress of data through the
pipeline. Instead, stages of the CPU are coordinated using logic devices called
"pipeline controls" or "FIFO sequencers." Basically, the pipeline controller
clocks the next stage of logic when the existing stage is complete. In this way, a
central clock is unnecessary. It may actually be even easier to implement high
performance devices in asynchronous, as opposed to clocked logic.
Clockless chips
CONTENTS
1. INTRODUCTION
1.1 Definition
2. CLOCKLESS APPROACH
3.1 Performance
3.2 Speed
4. ASYNCHRONOUS CIRCUITS
6. SIMPLICITY IN DESIGN
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15
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7.3 In Pagers
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8. CHALLENGES
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9. CONCLUSION
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10. REFERENCES
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LIST OF FIGURES
1.
Figure1
2.
Figure2
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3.
Figure3
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4.
Figure4
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1. INTRODUCTION
1.1 DEFINITION
Every action of the computer takes place in tiny steps, each a billionth of
a second long. A simple transfer of data may take only one step; complex
calculations may take many steps. All operations, however, must begin and end
according to the clock's timing signals.
The use of a central clock also creates problems. As speeds have increased,
distributing the timing signals has become more and more difficult. Present-day
transistors can process data so quickly that they can accomplish several steps in
the time that it takes a wire to carry a signal from one side of the chip to the
other. Keeping the rhythm identical in all parts of a large chip requires careful
design and a great deal of electrical power. Wouldn't it be nice to have an
alternative?
Clockless chips
The clock is a tiny crystal oscillator that resides in the heart of every
microprocessor chip. The clock is what which sets the basic rhythm used
throughout the machine. The clock orchestrates the synchronous dance of
electrons that course through the hundreds of millions of wires and transistors of
a modern computer.
Such crystals which tick up to 2 billion times each second in the fastest of
today's desktop personal computers, dictate the timing of every circuit in every
one of the chips that add, subtract, divide, multiply and move the ones and zeros
that are the basic stuff of the information age.
One advantage of a clock is that, the clock signals to the devices of the chip
when to input or output. This functionality of the synchronous design makes
designing the chip much easier. The circuit which uses global clock can allow
data to flow in the circuit in any manner of sequence and order does not matter.
Clockless chips
Clock
(Frequency
Figure 1
The diagram above shows the global clock is governing all components in the
system that need timing signals. All components operate exactly once per clock
tick and their outputs need to be ready and next clock tick.
2. CLOCKLESS APPROACH
2.1 CLOCK LIMITATIONS
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Clockless chips
One can create a clock that is so fast and it sends its timing signals to the
logic circuits which are governed by the clock timing signals. These logic
circuits are supposed to respond to every tick of the clock and yet when they can
compile to match the speed then logic circuits will be not optimum according to
the speed of clock and hence the input and output can go incorrect. This will
result hardware problem since one has to assemble chips to achieve the speed of
clock and hence much more complicated situation arise.
2.2 ASYNCRONOUS VIEW
By throwing out the clock, chip makers will be able to escape from huge
power dissipation. Clockless chips draw power only when there is useful work
to do, enabling a huge savings in battery-driven devices.
Like a team of horses that can only run as fast as its slowest member, a
clocked chip can run no faster than its most slothful piece of logic; the answer
isn't guaranteed until every part completes its work. By contrast, the transistors
on an asynchronous chip can swap information independently, without needing
to wait for everything else. The result? Instead of the entire chip running at the
speed of its slowest components, it can run at the average speed of all
components. At both Intel and Sun, this approach has led to prototype chips that
run two to three times faster than comparable products using conventional
circuitry.
Another advantage of clockless chips is that they give off very low levels of
electromagnetic noise. The faster the clock, the more difficult it is to prevent a
device from interfering with other devices; dispensing with the clock all but
eliminates this problem. The combination of low noise and low power
consumption makes asynchronous chips a natural choice for mobile devices.
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Clockless chips
However there are several problems that are associated with synchronous
circuits:
3.1 LOW PERFOMANCE
In a synchronous system, all the components are tied up together and the
system is working on its worst case execution. The speed of execution will not
be faster than that of the slowest circuit in the system and this will determine the
final working performance of the system. Although there are faster circuits
which have sophisticated performance but since they are depending of some
other slow components for input and output of data then they can no long run
faster than the slowest components.
Hence the performance of the synchronous system is limited to its worst case
performance.
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Clockless chips
begin
processing
the
results,
rather
than
waiting
for
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Clockless chips
Apart from the problems above, the clock is synchronous circuit and globally
distributed over the components which are obviously in running in different
speed and hence the order of arrive of the timing signal is not important. Data
can be received and transmitted in any form of order regardless of there
sequential order they arrive at the fist stage of execution.
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Clockless chips
4 ASYNCRONOUS CIRCUITS
Asynchronous circuits are the electronic digital circuits that are not
govern by the central clock in their timing instead they are standardized in their
installation and they use handshakes signals for communication to each other
components. In this case the circuits are not tied up together and forced to
follow the global clock timing signals but each and every component is loosely
and they run at average speed.
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Clockless chips
startups,
Asynchronous
Digital
Devices
and
Self-Timed
Solutions, are populating now, and clockless-chip research has been going on
the longest.
For a chip to be successful, all three elements-design tools, manufacturing
efficiency and experienced designers-need to come together. The asynchronous
cadre has very promising ideas.
There is now way one can obtain pure asynchronous circuits to be used in the
complete design of the system and this is one of major barrier of clockless
implementation but the circuits were successfully standardized and hence they
do not have to be in synchronous mode. And hence handshakes were the
solution to overcome synchronization. One component which needs to
communicate with the other uses the handshake signals to achieve the
establishment of connection and then with set up the time at which is going to
send data and at the other side another component will also use the same kind of
handshakes to harden the connection and wait for that time to receive data.
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Clockless chips
Handshakes
Interface
clock
Synchronous System
(Centralized Control)
Asynchronous System
(Distributed Control)
Figure 2
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Clockless chips
6. SIMPLICITY IN DESIGN
Clockless chips
* Operation is free of glitches as each gate can make only one transition.
Typically handshake signals are used to indicate the readiness of such a circuit
to accept new data (the previous computation is complete) and the delivery of
such data by the requesting function. Similarly there may be output handshake
signals indicating the readiness of the result and the safe delivery of the result to
the next stage in a computational chain or pipeline.
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Clockless chips
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Clockless chips
Figure3
The figure show first circuit being not asynchronous and then the second shows
dual rail with every bit taken into computation.
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Clockless chips
The figure shows how power is less confused by first taking down the frequency
by dividing the give frequency to two and the next one show as many circuits
are cascaded the more the frequency is divided. This provides a crucial
reduction on power consumption.
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Clockless chips
Clockless chips are used in other applications also on rather than in design of
computers and these are:
Wearable computers are mobile computers that are worn on the body.
They have been applied to areas such as behavioral modeling, health monitoring
systems, information technologies
Government
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Clockless chips
pager
(sometimes
called
beeper)
is
simple
personal
A filter bank is an array of band-pass filters that separates the input signal
into several components, each one carrying a single frequency subband of the
original signal. It also is desirable to design the filter bank in such a way that
subbands can be recombined to recover original signal. The first process is
called analysis, while the second is called synthesis. The output of analysis is
referred as subband signal with as many subbands as there are filters in filter
bank.
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Clockless chips
8. CHALLENGES
2. Lack of expertise.
3. Lack of tools.
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Clockless chips
9. CONCLUSION
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Clockless chips
10. REFERENCES
1. Scanning the Technology: Applications of Asynchronous Circuits C. H.
(Kees) van Berkel, Mark B. Josephs, and Steven M. Nowick proceedings of
IEEE, December 2004.
2. Computers without clocks Ivan E Sutherland and Jo Ebergen Scientific
American, August 2006.
3. Is it time for Clockless chips? David Geer published by IEEE Computer
Society, March 2005.
4. Guest Editors Introduction: Clockless VLSI Systems Soha Hassoun,
Yong-Bin Kim and Fabrizio Lombardi copublished by IEEE CS and IEEE
November December 2005.
5. It's Time for Clockless Chips Claire Tristram from MIT Technology
October 2008
6. Old tricks for new chips Apr 19th 2012 From The Economist print edition
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