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VND 7N V04 Sonda PDF
VND 7N V04 Sonda PDF
/ VND7NV04 / VND7NV04-1
OMNIFET II:
FULLY AUTOPROTECTED POWER MOSFET
BLOCK DIAGRAM
DRAIN
2
Overvoltage
Clamp
INPUT
Gate
1 Control
Linear
Current
Over Limiter
Temperature
3
SOURCE
FC01000
1
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
SOURCE 1 8 DRAIN
SOURCE DRAIN
SOURCE DRAIN
INPUT 4 5 DRAIN
(*) For the pins configuration related to SOT-223, DPAK, IPAK see outlines at page 1.
ID
VDS
DRAIN
IIN RIN
INPUT
SOURCE
VIN
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1
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
THERMAL DATA
Value
Symbol Parameter Unit
SOT-223 SO-8 DPAK IPAK
Rthj-case Thermal Resistance Junction-case}}} MAX 18 2.1 2.1 C/W
Rthj-lead Thermal Resistance Junction-lead MAX 27 C/W
Rthj-amb Thermal Resistance Junction-ambient MAX 96 (*) 90 (*) 65 (*) 102 C/W
(*) When mounted on a standard single-sided FR4 board with 0.5cm2 of Cu (at least 35 m thick) connected to all DRAIN pins.
ELECTRICAL CHARACTERISTICS (-40C < Tj < 150C, unless otherwise specified)
OFF
Symbol Parameter Test Conditions Min Typ Max Unit
Drain-source Clamp
VCLAMP VIN=0V; ID=3.5A 40 45 55 V
Voltage
Drain-source Clamp
VCLTH VIN=0V; ID=2mA 36 V
Threshold Voltage
VINTH Input Threshold Voltage VDS=VIN; ID=1mA 0.5 2.5 V
Supply Current from Input
IISS VDS=0V; VIN=5V 100 150 A
Pin
Input-Source Clamp IIN=1mA 6 6.8 8
VINCL V
Voltage IIN=-1mA -1.0 -0.3
Zero Input Voltage Drain VDS=13V; VIN=0V; Tj=25C 30
IDSS A
Current (VIN=0V) VDS=25V; VIN=0V 75
ON
Symbol Parameter Test Conditions Min Typ Max Unit
Static Drain-source On VIN=5V; ID=3.5A; Tj=25C 60
RDS(on) m
Resistance VIN=5V; ID=3.5A 120
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1
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
SWITCHING
Symbol Parameter Test Conditions Min Typ Max Unit
td(on) Turn-on Delay Time 100 300 ns
VDD=15V; ID=3.5A
tr Rise Time 470 1500 ns
Vgen=5V; Rgen=RIN MIN=150
td(off) Turn-off Delay Time 500 1500 ns
(see figure 1)
tf Fall Time 350 1000 ns
td(on) Turn-on Delay Time 0.75 2.3 s
VDD=15V; ID=3.5A
tr Rise Time 4.6 14.0 s
Vgen=5V; Rgen=2.2K
td(off) Turn-off Delay Time 5.4 16.0 s
(see figure 1)
tf Fall Time 3.6 11.0 s
VDD=15V; ID=3.5A
(dI/dt)on Turn-on Current Slope 6.5 A/s
Vgen=5V; Rgen=RIN MIN=150
VDD=12V; ID=3.5A; VIN=5V
Qi Total Input Charge 18 nC
Igen=2.13mA (see figure 5)
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2
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
5/29
1
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
VD
Rgen
Vgen
ID
90%
tr tf
10%
t
td(on) td(off)
Vgen
A
A
D
I FAST L=100uH
OMNIFET DIODE
S B
B
150 D
VDD
Rgen
I
OMNIFET
Vgen
S
8.5
6/29
1
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
Figure 3: Unclamped Inductive Load Test Circuits Figure 4: Unclamped Inductive Waveforms
RGEN
VIN
PW
VIN
7/29
1
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
850 350
Tj=25C
800 300
750 250
Tj=150C
700 200
650 150
600 100
550 50
500 0
0 2 4 6 8 10 12 14 0 0.25 0.5 0.75 1 1.25
Id(A) Id(A)
110
Id=3.5A
100
90
Tj=150C
80
70
60
50
Tj=25C
40
30
Tj= - 40C
20
10
0
3 3.5 4 4.5 5 5.5 6 6.5 7
Vin(V)
18
120 Vds=13V
Tj=150C
16
Tj=-40C
100 14 Tj=25C
Id=6A Tj=150C
Id=1A 12
80
10
60 Tj=25C
8
Tj=-40C Id=6A 6
40
Id=1A
Id=6A 4
20 Id=1A
2
0 0
3 3.5 4 4.5 5 5.5 6 6.5 0 1 2 3 4 5 6 7 8
Vin(V) Id(A)
8/29
1 1
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
100 7
Tj=150C
Vin=5V
6
80
5
60 Vin=3.5V
4
Tj=25C
Vin=5V
40 3
Vin=3.5V
Tj=-40C
Vin=5V
2
20
1
0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
Id(A) Vin(V)
di/dt(A/us) di/dt(A/us)
8 2.25
7 2
Vin=5V Vin=3.5V
6 Vdd=15V 1.75 Vdd=15V
Id=3.5A Id=3.5A
5 1.5
4 1.25
3 1
2 0.75
1 0.5
0 0.25
100 200 300 400 500 600 700 800 900 1000 1100 100 200 300 400 500 600 700 800 900 1000 1100
Rg(ohm) Rg(ohm)
Input Voltage Vs. Input Charge Turn off drain source voltage slope
dv/dt(V/us)
Vin(V)
300
8
7 250
Vds=12V
Id=3.5A Vin=5V
6
200 Vdd=15V
Id=3.5A
5
150
4
100
3
2 50
1
0
100 200 300 400 500 600 700 800 900 1000 1100
0
0 5 10 15 20 25
Rg(ohm)
Qg(nC)
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1
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
250
500
Vin=3.5V f=1MHz
200 Vdd=15V Vin=0V
Id=3.5A 400
150
300
100
50 200
0
100
100 200 300 400 500 600 700 800 900 1000 1100
0 5 10 15 20 25 30 35
Rg(ohm) Vds(V)
2.5 800
2
600
1.5 td(off)
400
1 tf
td(on)
0.5 200
0 td(on)
0 250 500 750 1000 1250 1500 1750 2000 2250 2500 0
3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25
Rg(ohm) Vin(V)
ID(A) Rds(on)
12 2.25
11
2
10 Vin=5V
Vin=5V Id=3.5A
9
Vin=4.5V 1.75
8 Vin=4V
7 1.5
6 Vin=3V
5 1.25
4
1
3
Vin=2.5V
2
0.75
1
Vin=2V
0 0.5
0 1 2 3 4 5 6 7 8 9 10 11 12 13 -50 -25 0 25 50 75 100 125 150 175
VDS(V) T(C)
10/29
1 1
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
Normalized Input Threshold Voltage Vs. Current Limit Vs. Junction Temperature
Temperature
Vin(th) Ilim (A)
1.15 15
1.1 14
Vds=13V
Vds=Vin 13
1.05 Vin=5V
Id=1mA
12
1
11
0.95
10
0.9
9
0.85
8
0.8
7
0.75 6
0.7 5
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
T(C) Tj (C)
Tdlim(us)
7
6.5
Vin=5V
Rg=150ohm
6
5.5
4.5
3.5
5 10 15 20 25 30 35
Vdd(V)
11/29
1 1
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
ILMAX (A)
100
10
B
C
1
0.01 0.1 1 10 100
L(mH)
Conditions:
VCC=13.5V
Values are generated with RL=0
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed
the temperature specified above for curves B and C.
VIN, IL
Demagnetization Demagnetization Demagnetization
12/29
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
ILMAX (A)
100
10
B
C
1
0.01 0.1 1 10 100
L(mH)
Conditions:
VCC=13.5V
Values are generated with RL=0
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed
the temperature specified above for curves B and C.
VIN, IL
Demagnetization Demagnetization Demagnetization
13/29
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
ILMAX (A)
100
10
A
B
C
1
0.01 0.1 1 10
L(mH)
Conditions:
VCC=13.5V
Values are generated with RL=0
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed
the temperature specified above for curves B and C.
VIN, IL
Demagnetization Demagnetization Demagnetization
14/29
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
SO-8 PC Board
Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm,
Cu thickness=35m, Copper areas: 0.14cm2, 0.6cm2, 1.6cm2).
15/29
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
SOT-223 PC Board
Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm,
Cu thickness=35m, Copper areas: 0.11cm2, 1cm2, 2cm2).
140
130
120
110
100
90
80
70
60
0 0.5 1 1.5 2 2.5
Cu area (cm^2)
16/29
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
DPAK PC Board
Layout condition of Rth and Zth measurements (PCB FR4 area= 60mm x 60mm, PCB thickness=2mm,
Cu thickness=35m, Copper areas: from minimum pad lay-out to 8cm2).
90
80
70
60
50
40
30
0 2 4 6 8 10
PCB CU heatsink area (cm^2)
17/29
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
ZT H (C/W)
1000
100 Footprint
6 cm2
10
0.1
0.0001 0.001 0.01 0.1 1 10 100 1000
Time (s)
18/29
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
ZT H (C/W)
1000
Footprint
100
2 cm2
10
0.1
0.0001 0.001 0.01 0.1 1 10 100 1000
T ime (s)
19/29
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
ZT H (C /W)
1000
Footprint
100
2 cm2
10
0.1
0.0001 0.001 0.01 0.1 1 10 100 1000
T ime (s)
20/29
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 2.2 2.4 0.086 0.094
A1 0.9 1.1 0.035 0.043
A3 0.7 1.3 0.027 0.051
B 0.64 0.9 0.025 0.031
B2 5.2 5.4 0.204 0.212
B3 0.85 0.033
B5 0.3 0.012
B6 0.95 0.037
C 0.45 0.6 0.017 0.023
C2 0.48 0.6 0.019 0.023
D 6 6.2 0.236 0.244
E 6.4 6.6 0.252 0.260
G 4.4 4.6 0.173 0.181
H 15.9 16.3 0.626 0.641
L 9 9.4 0.354 0.370
L1 0.8 1.2 0.031 0.047
L2 0.8 1 0.031 0.039
H
C
A
A3
C2
A1
L2 D L
B3
B6
B5
B
3
=
=
B2
G
E
2
=
=
1
L1
21/29
11
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 2.2 2.4 0.086 0.094
L2 0.8 0.031
R 0.2 0.008
V2 0 8 0 8
D
C
A
C2
A1
V2
A2
L2
B
=
=
FLAT ZONE
0.60 MIN.
=
B2
G
E
=
=
L4
H
22/29
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 1.8 0.071
e 2.3 0.09
e1 4.6 0.181
V 10 (max)
A1 0.02 0.1 0.0008 0.004
0046067
23/29
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 1.75 0.068
a2 1.65 0.064
a3 0.65 0.85 0.025 0.033
c1 45 (typ.)
e3 3.81 0.150
M 0.6 0.023
F 8 (max.)
24/29
1
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
REEL DIMENSIONS
Base Q.ty 1000
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C ( 0.2) 13
F 20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width W 12
Tape Hole Spacing P0 ( 0.1) 4
Component Spacing P 8
Hole Diameter D ( 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F ( 0.05) 5.5
Compartment Depth K (max) 4.5
Hole Spacing P1 ( 0.1) 2
End
Start
25/29
1
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
SO-8 TUBE SHIPMENT (no suffix)
B
C Base Q.ty 100
Bulk Q.ty 2000
Tube length ( 0.5) 532
A A 3.2
B 6
C ( 0.1) 0.6
REEL DIMENSIONS
Base Q.ty 2500
Bulk Q.ty 2500
A (max) 330
B (min) 1.5
C ( 0.2) 13
F 20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width W 12
Tape Hole Spacing P0 ( 0.1) 4
Component Spacing P 8
Hole Diameter D ( 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F ( 0.05) 5.5
Compartment Depth K (max) 4.5
Hole Spacing P1 ( 0.1) 2
Start
26/29
1
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
A
6 .7 1 .8 3 .0 1 .6 C Base Q.ty 75
Bulk Q.ty 3000
2 .3 Tube length ( 0.5) 532
6 .7
A 6
2 .3
B B 21.3
C ( 0.1) 0.6
REEL DIMENSIONS
Base Q.ty 2500
Bulk Q.ty 2500
A (max) 330
B (min) 1.5
C ( 0.2) 13
F 20.2
G (+ 2 / -0) 16.4
N (min) 60
T (max) 22.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width W 16
Tape Hole Spacing P0 ( 0.1) 4
Component Spacing P 8
Hole Diameter D ( 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F ( 0.05) 7.5
Compartment Depth K (max) 6.5
Hole Spacing P1 ( 0.1) 2
Start
27/29
1
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
A
C
Base Q.ty 75
Bulk Q.ty 3000
Tube length ( 0.5) 532
B A 6
B 21.3
C ( 0.1) 0.6
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1
VNN7NV04 / VNS7NV04 / VND7NV04 / VND7NV04-1
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a trademark of STMicroelectronics
http://www.st.com
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