UNIVERSITY OF CALIFORNIA, BERKELEY

College of Engineering
Department of Electrical Engineering and Computer Sciences

Elad Alon Homework #8 EECS141

Due Tuesday, Nov. 24th @ 240 Cory

PROBLEM 1: DOMINO LOGIC AND CHARGE SHARING

a) Implement the logic shown below as a single complex, dynamic gate (with four
inputs) followed by an inverter.

A
B
C
X
D

b) What pattern of the inputs P1, G0, and G1 results in the worst-case drop in voltage
on node G1:0_b due to charge sharing for the gate shown below? Assuming VDD =
1.2V, CG = 2fF/m, and CD = 1.5fF/m, what is this worst-case voltage?

PROBLEM 2: DOMINO SIZING AND DELAY

Consider the domino circuit shown on the next page. Assume long-channel transistors,
CL = 300fF, Cin = 5fF, CG = 2fF/m, CD = 1.5fF/m, and that input signal C is the last
one to arrive.

a) Find the logical effort of each stage in the critical path for the evaluation edge
(rising edge of Out).

b) Find WN1 and WN2 to give minimal delay.

c) Estimate the delay of the critical path in F04. Include the worst-case parasitic
delay terms. Recall that 1FO4 is equal to (4+)tinv.

d) From the standpoint of minimum delay, is this the optimum number of stages? If
not, how many stages would you use to minimize the delay?

VDD VDD

CLK 2/3*WN1 4WN2

Out

CL
A WN1 C WN1 WN2

B WN1 D WN1

CLK WN1