Diode Transistor Logic (DTL).

DTL 
(TTL)

VD,on = 0.7 V, VCE,sat = 0.2 V 


     DTL


VCC  VCE ,sat

IC 

Num
R2

N
I

Fan in { 
Fan out { 


 TTL .
VLSITTL

TTL


NMH = 2.0 V; NML = 0.1 V


 
Emitter Coupled Logic (ECL).

ECL 
A F(VC1) F(VC2)
0 (- 1.6 V) 0 (- 0.8 V) 1 (0 V)
1 (- 0.8 V) 1 (0 V) 0 (- 0.8 V)


ECL ORNOR


 FET 

N JFET 

  x
  x
  x


 
Integrated Injection Logic (I2L)

 I2L


 3
2 2H r H 0 2
 VGS  VDS  2  (  VGS ) 2
2WqaN D P e
1

 VDS 
3

3 qN D a 2
I DS

L


qa 2 N D
2H r H 0 Pinch-off 
VP


 VDS(sat) = VGS - VP 

I DSS 1  GS
2
V

I DS (sat )
VP


MOSFETIGFET


depletion NMOS


  NMOS

VDD  I RD R D VDD  R D >2( VGS  VT )  VDS @VDS

K
Vout
2


NMOS

F = A NOR B

F = A NAND B


 enhancement NMOS
 NMOS


kn VGSVT  kn VDSVT  ,
1 W 2 1 W
VDS tVDS(sat) VGSVT
2 L 2 L
2
ID


NMOS



NMOS



NMOS

W / L 1

W / L 2
AV


MOS


NMOS


CMOS MOS


 CMOS 

Vin 

Vin 

ID {
VDS
# k n
W
VGS  VT VDS
R DS L

 CMOS 


 CMOS

For theQ N transistor :

W 1 2
I DN k n Vin  VTN Vout  Vout for Vout d Vin  VTN ,
L n 2
1 W
k n Vin  VTN  for Vout ! Vin  VTN ,
2
I DN
2 L n
and for the Q P transistor :

k p VDD  Vin  VTP VDD  Vout   VDD  Vout  for Vout t Vin  VTP ,
W 1 2
I DP
L p 2

k p VDD  Vin  VTP  for Vout  Vin  VTP .

W 2
I DP
L p
WpPp = WnPn
NMH = NML = 0.125(3VDD + 2VT)


CMOS

VT | 0.2 VDD 

1.6C
t PHL
k n ( W / L )VDD




2
PD fCVDD


 BiCMOS

CMOS  BJT 

Bipolar-CMOS 


 MESFET

MESFET 

MESFET


CMOSPTL 


VinNMOS 
iD = 0.5kn(VDD - Vout-VT)2

VinNMOS 
iD = 0.5kn(VDD - VT)2


CMOS PTL 

Vo1  QR


CMOS PTL 


PTL


 
     


    Qp      I
 Qe   Qp I precharge phase setup
evaluation phase 


 
       


SR

CMOS SR 


SR 

D 





 
CMOS  

 CMOS 

R VDD
C(R  R on ) ln
R  R on VDD  VT
T