Elektronika Digital 2

VE033104

Introduction to Sequential Circuit

Mohammad Syafrudin
 Gate Propagation Delay

NAND2
A A
F tPD F
B B

Logic Symbol Logic Symbol Followed by Pure Delay

(No Delay)

F A B F (t ) A(t ) B(t )
 Prapagation Delay for Inverting

X X
H

Vs Vs
L
tPHL tLH
H
90%
Vs Vs
L 10%
tHL tPLH

Propagation Delay Times for an Inverting Gate

 Sequential Circuit

X
1 B
A

1
A
0 20
5 10 15
1
B
0
6 8 10 16 18 20
1
X
0
5 7 9 10 15 17 19
Gated Oscillator
 State Transition Diagram

B
A

0
1 0
0 1
1

Stable State, Transitional State :

- Kondisi masukan A = 0, State 1 adalah Stable State, sementara State 0
adalah Transitional State.
- Kondisi masukan A = 1, pasangan State 0 dan State 1 membentuk
sebuah pasangan Oscillating State
 Binary Storage Elements
(Digital Latching Circuit)

S
1 Y
2 Z

Z(t) = 0 t 0
S(t) = 0 t 0
Z (t 1 2 ) Z (t ) S (t ) Y(t) = 1 t 0

1
S
0
t1 t2 t3 t4
1
Y 0
t1+1
1
Z
0
t1+1+2
Drawback of Latching Circuit
Jika pulsa dengan durasi pendek
(lebih kecil dari total delay rangkaian)
diberikan pada masukan S,
menyebabkan keluaran akan ber-
osilasi.
Perlu diperhatikan, lebar pulsa minimal
yang direkomendasikan.
 Set-Reset Storage Elements
S Y
1
2 Z
R

Y (t 1 ) Z (t ) S (t ) Jika: 1 2
Z * (t 2 ) Y (t ) R(t ) Z (t 2 ) R(t )[ Z (t ) S (t )]
Z (t 1 2 ) Y (t 1 ) R(t 1 )
Z (t ) S (t ) R(t 1 )
Z (t 1 2 ) R(t 1 )[ Z (t ) S (t )]
 Set-Reset Storage Elements
S Distributed Delay Model
Y
1
1 Z
R

Jika: 1 2
Z (t 2 ) R(t )[ Z (t ) S (t )]
Lumped Delay Model
S Y
ZND
R

Z
2
Set-Reset Storage Elements
S 1
0 Y
0 1
0
Z
R
0

Present Next State Y(t+) Z(t+)

State Present Inputs S(t) R(t)
Y(t) Z(t) 00
00 11
Set-Reset Storage Elements
S 1
0 Y
0 0
Z
R
1

Present Next State Y(t+) Z(t+)

State Present Inputs S(t) R(t)
Y(t) Z(t) 00 01
00 11 10
Set-Reset Storage Elements
S 0 Y
1 0
Z
R
1

Present Next State Y(t+) Z(t+)

State Present Inputs S(t) R(t)
Y(t) Z(t) 00 01 11
00 11 10 00
Set-Reset Storage Elements
S 0 Y
1 1
0
Z
R
0

Present Next State Y(t+) Z(t+)

State Present Inputs S(t) R(t)
Y(t) Z(t) 00 01 11 10
00 11 10 00 01
Set-Reset Storage Elements
S Y
Z
R

Present Next State Y(t+) Z(t+)

State Present Inputs S(t) R(t)
Y(t) Z(t) 00 01 11 10
00 11 10 00 01
01 01 00 00 01
11 00 00 00 00
10 10 10 00 00
Set-Reset Storage Elements
S Y
Z
R

Present Next State Y(t+) Z(t+)

State Present Inputs S(t) R(t)
Y(t) Z(t) 00 01 11 10
00 11 10 00 01
01 01 00 00 01
11 00 00 00 00
10 10 10 00 00
 Set-Reset Storage Elements
S Y
Z
R

Present Next State Y(t+) Z(t+)

State Present Inputs S(t) R(t)
Y(t) Z(t) 00 01 11 10
00 11 10 00 01 = Stable State
NS = PS
01 01 00 00 01
11 00 00 00 00
10 10 10 00 00
Conclusion:
C1:Masukan S(set),membuat keluaran Z
bernilai 1, pada saat yang sama
berfungsi sebagai masukan Reset
pada keluaran Y.
C2:Masukan R(reset),membuat keluaran
Z bernilai 0, pada saat yang sama
berfungsi sebagai masukan Set
pada keluaran Y.
Conclusion:
C3:Pada keluaran yang Complement
(01 dan 10), adalah Stable state,
terjadi pada saat Present Input S(t)
R(t): 00, 01, dan 10.
C4:Syarat masukan: S(t)R(t) = 0
C5:Jika batasan masukan: S(t)R(t) = 0,
maka Y = Z
 NOR-gate S-R Flip-Flop

S Z 1
S 1

0
R 0
R Y=Z*

NOR-Gate SR Flip-Flop Logic Symbol

 NOR-gate S-R Flip-Flop
Non-complement / Set Output:
Bernilai 1 ketika S=1 & R=0

S 1

Z Complement / Reset Output:

Bernilai 0 ketika S=0 & R=1

R 0

Z (t ) R(t )[ Z (t ) S (t )]
Y (t ) S (t )[ R(t ) Y (t )] atau Z * (t ) S (t )[ R(t ) Z * (t )]
Keluaran Y dapat dikatakan sebagai complement dari Z (Y = Z ) jika masukan
S dan R memenuhi persyaratan penggunaan normal: S(t)R(t) = 0
 NAND-gate S-R Flip-Flop
NAND SR-FF adalah Complement dari NOR SR-FF

S Z* 1
S 1

Z*

0
R 0
R Z

NAND-Gate SR Flip-Flop Logic Symbol

 NAND-gate S-R Flip-Flop
NAND SR-FF adalah Complement dari NOR SR-FF

OUTPUT
Non-Complement Complement
Z * (t ) S (t )[ R(t ) Z * (t )]
NOR Z (t ) R(t )[ Z (t ) S (t )] atau
SR-FF
Y (t ) S (t )[ R(t ) Y (t )]

NAND
Z * (t ) S (t ) R(t ) Z * (t ) Z (t ) R(t ) S (t ) Z (t )
SR-FF
 NAND-gate S-R Flip-Flop
NAND SR-FF adalah Complement dari NOR SR-FF

Syarat Masukan
NOR SR-FF S(t) R(t) = 0

NAND SR-FF S(t) R(t) = 1

 Set-Reset Storage Elements
S
Z*
Z
R

Present Next State Z*(t+) Z(t+)

State Present Inputs S(t) R(t)
Z*(t) Z(t) 00 01 11 10
00 11 11 11 11 = Stable State
NS = PS
01 11 11 01 01
11 11 10 00 01
10 11 10 10 11
 Clocked-Storage Element
R Z (t ) [ R(t ) C (t )][ S (t )C (t ) Z (t )]
Z

C
Z * (t ) [ S (t ) C (t )][ R(t )C (t ) Z * (t )]
Z*
S

S Z (t ) S (t )C (t ) [ R(t ) C (t )]Z (t )
Z

C
Z * (t ) R(t )C (t ) [ S (t ) C (t )]Z * (t )
Z*
R
 Clocked-Storage Element
R
Z S 1

C Z
Z* R 0
S C

Z (t ) [ R(t ) C (t )][ S (t )C (t ) Z (t )]
Z * (t ) [ S (t ) C (t )][ R(t )C (t ) Z * (t )]
Ketika C(t) = 0 Ketika C(t) = 1

Z (t ) Z (t ) Z (t ) R(t )[ S (t ) Z (t )]
Z * (t ) Z * (t ) Z * (t ) S (t )[ R(t ) Z * (t )]
 Clocked-Storage Element
S
Z
S 1
C
Z
Z* R 0
R C

Z (t ) S (t )C (t ) [ R(t ) C (t )]Z (t )

Z * (t ) R(t )C (t ) [ S (t ) C (t )]Z * (t )
Ketika C(t) = 0 Ketika C(t) = 1

Z (t ) Z (t ) Z (t ) S (t ) R(t ) Z (t )
Z * (t ) Z * (t ) Z * (t ) R(t ) S (t ) Z * (t )
Summary:
NAND : Z (t ) S (t ) R(t ) Z (t )
NOR : Z (t ) R(t )[ S (t ) Z (t )]

PI PS NS
Description
S(t) R(t) Z(t) Z(t+)
0 0 0 0 NS = PS
0 0 1 1 HOLD

0 1 0 0 NS = 0
0 1 1 0 RESET

1 0 0 1 NS = 1
1 0 1 1 SET
 State Diagram of SR-FF
01 10

00 10
0 1
01 00

Bisa diringkas menjadi:

0- 10
0 1
01 -0