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AN102FETbiasing PDF
AN102FETbiasing PDF
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Siliconix 1
10-Mar-97
AN102
1.5
VDS = 15 V +VDD
1.2 RD
VGS = 0 1.2 eg Output
0.9
Constant RG
–0.2 V 0.9 VGG Load
I D (mA)
I D (mA)
RD = 39 k Line
0.6 –VGG
–0.4 V 0.6
ID
0.3 –0.6 V
0.3
–0.8 V
VGS(off)
0 0
0 10 20 30 40 50 0 –0.8 –1.2 –1.6
VDS (V)
eg VGS (V)
Figure 1. Output Characteristic Curve—A large dynamic Figure 2. Transfer Curve—Constant-voltage bias is
range is provided by the operating point at maintained by the VGG supply as shown on this
VDSQ = 15 V, IDQ= 0.4 mA, and VGSQ = –0.4 V. typical transfer curve. Input signal eg moves the
load line horizontally.
1.5 1.5
VDS = 15 V +VDD VDS = 15 V
RD
1.2 eg Output 1.2
RG ID
0.9 0.9
I D (mA)
I D (mA)
ac Load Line
ac Load Line Slope – wC
0.6 0.6
ID
Signal
0.3 0.3
dc Load Line dc Load Line
0 0
0 –0.4 –0.8 –1.2 –1.6 0 –0.4 –0.8 –1.2 –1.6
Figure 3. Constant-current bias fixes the output voltage for Figure 4. Partial bypassing of the current source (Figure 3)
any RD. Hence, input signals cannot affect the Lowers the circuit gain by tilting the ac load line
output unless the current source is bypassed. from the vertical. The capacitor drop subtracts
from eg.
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AN102
If an ac ground is provided by a bypass capacitor across 1.5
VDS = 15 V +VDD
the current source, a vertical ac bias line will be
established. Input signal variations will then translate the RD
1.2 eg Output
ac bias line horizontally, and signal development will
proceed as with constant-voltage biasing (Figure 3).
RG RS
0.9
I D (mA)
Should the bypass capacitor not provide a sufficiently low Self-Bias dc
0.6 Load Line
reactance at the signal frequency, the ac bias line will not be
be vertical. It will still intersect the transfer curve at the
Q-point but with a slope equal to –(1/XC) = –wC (Figure 4). ID
0.3
0
This will lower the gain of the amplifier because of signal 0 –0.4 –0.8 –1.2 –1.6
degeneration at the source. The input signal, eg, is
reduced by the drop across the capacitor: VGS (V)
eg
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AN102
and the gate. This allows R1 and R2 to be small, without flexibility to provide constant gain despite variations in
lowering the input impedance. the forward transconductance, gfs, of the devices.
One point of caution is that as VGG is increased, VS The selfĆbias scheme is a reasonable choice for
increases, and VDS decreases. Therefore, with low VDD, singleĆended dc amplifiers and for ac amplifiers. In
there may be a significant decrease in the allowable unbypassed or dc circuits, some compromise must be
output voltage swing. made between the gain loss due to current feedback
degeneration and the advantage of current stabilization
achieved with high RS.
Biasing for Device Variations
An appropriate choice of IDQ limits can be made by
The value of the combination-bias technique becomes using the pair of limiting transfer curves. For example,
apparent when one considers the normal production for RS = 1 kW, the load line shown on the selfĆbias
spread of device characteristics. The problem is curve of Figure 7c is established. The maximum I D
illustrated in Figure 7 where the lower and higher ranges is 0.52 mA, and the minimum ID is 0.24 mA. The
of the 2N4339 devices are shown. The two curves operating range of VDSQ may be calculated for any
illustrate the operating current variations using various value of VDD and RD . Clearly, for RD = 39 kW, the
types of biasing in a normal production lot. Other devices maximumĆlimit device (device B) would operate
with even wider min/max IDSS limits will show wider with VDSQ = 9.8 V and the minimumĆlimit device
variations. (device A) would operate with V DSQ = 20.6 V. This
results in satisfactory operation for all devices.
However, such a variation in I DQ imposes severe
Attempting to establish suitable constant-voltage bias limitations on the circuit design.
conditions for a production spread of devices is practical
only for circuits with very small values of dc drain resistance
A better approach is illustrated by the combinationĆbias
—for example, circuits with inductive loads. As the
curve of Figure 7d with VGG = 1.2 V. The range of IDQ
constant-voltage bias plot of Figure 7a reveals, constant gate
for the bias condition is 0.25 mA to 0.32 mA.
bias causes a significant difference in operating IDQ for the
extreme limit devices. At VGS = –0.4 V, the range of IDQ
A similar minimum difference in IDQ could be achieved
is 0.13 to 0.69 mA, and VGSQ for a given RD will vary
with RS = 6 kW and VGG = 0 (a selfĆbias condition) but
greatly for most resistance-loaded circuits. For the example
the operating points would be pushed toward the toe of
of Figure 1, with RD = 39 kW and VDD = 30 V, VGSO varies
the transfer characteristics and allowable signal input
from near saturation (5 V) to 25 V.
would be reduced.
An excellent method of biasing is the The combination circuit (Figure 7d) allows almost ideal
constantĆcurrent method of Figure 3. Biasing in this operation over the full production spread of devices.
manner fixes the operating drain current for all Even with RD = 6 kWā, the VDSQ would range only
devices and sets VDSQ to VDD - IDQRL for any between 10 and 15 V.
device in the production spread. VGS automatically
finds a value to set the appropriate IDQ = constant
For the combination circuit, RD should be chosen to
for all devices. For the constantĆcurrent bias plot of
allow the largest output signal swing for IDQ midway
Figure 7b, with IDQ = 0.4 mA, VGS would range
between the two extremes of 0.25 and 0.32 mA; namely
from -0.11 to -0.67 V.
0.285 mA. Setting the voltage drop across RD at oneĆhalf
of (VDD - 2 VGS(off)typ) or 14 V, (30Ć2)1/2 yields RD =
Output characteristics are not needed as long as IDQ is (14 V/0.285 mA) = 49 kW.
chosen to be below the minimum IDSS. With RD = 39 kW
and VDD = 30 V, VDSQ is 14.8 V for all devices. Figure 10 shows the effect of temperature variation on
the transfer characteristics from 25 to 125_C. The
The disadvantages of the constantĆcurrent method are opposite change occurs from 25 to -55_C. The
that it allows no signal to be developed unless the current temperature effect is generally far less than the
source is bypassed and, as we shall see, it lacks the deviceĆtoĆdevice variation.
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+VDD +VDD +VDD
RG RS R1 RS R1 RS
+VGG
1.5
VDS = 15 V
1.2
I D (mA)
0.9
0.6 RS = 5 k
Figure 6. All three combination-bias circuits are equivalent. They add constant-voltage biasing to the self-bias circuit to
extablish a reasonably flat load line without sacrificing dynamic range.
I D (mA)
0.9 0.9
QB
0.6 0.6
QA QB
0.3 0.3
QA
0 0
0 –0.4 –0.8 –1.2 –1.6 0 –0.4 –0.8 –1.2 –1.6
VGG = –0.4 V V (V) VGS (V)
GS
I D (mA)
0.9 0.9
RS = 1 k
0.6 0.6
QB RS = 6 kW
0.3 QA 0.3 QB
QA
0
0 –0.4 –0.8 –1.2 –1.6 1.6 1.2 0.8 0.4 0 –0.4 –0.8 –1.2 –1.6
VGS (V) VGS (V)
Figure 7. Transfer Characterisitc Curves—2N4339: The advantages of combination biasing, when one is working with a spread
of device characteristics, are made obvious by plotting the load lines for the various types of biasing on a pair of
limiting transfer curves.
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Minimize The Gain Variations values. Thus, a constant, or nearly constant, stage gain is
obtained even with a bypass capacitor.
Leaving RS unbypassed helps reduce gain variations
from device to device by providing degenerative current The design procedure is as follows:
feedback. However, this method for minimizing gain Step 1. Select a desired IDQA below IDSSA. A good value,
variations is only effective when a substantial amount of allowing for temperature variations, is 60% of
gain is sacrificed. IDSSA. This will allow for decreasing IDSS due to
temperature variation and for reasonable signal
A better approach is to use the combinationĆbias excursions in load current.
technique with the bias point selected from the transfer
and transconductance curves (Figure 8). Step 2. Enter the transfer curves at IDQA 0.6 IDSSA
(0.3 mA) to find VGSQA. Thus VGSQA –0.2.
Step 3. Drop vertically at VGSQA to the minimum limit
transconductance curve to find gfsQA. The value as
read from the plot is approximately 1000 mS.
1.5
VDS = 15 V
Step 4. Travel across the gfs plot to the maximum
1.2 curve to find VGSQB at the same value of gfs.
This is VGSQB –0.7 V.
I D (mA)
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AN102
point QA and slide it, without changing its slope, until it is Before getting into the details of bias-circuit design,
tangent to the curve of device B. The tangent point is QB. several general observations can be made about the
circuits of Figure 9:
Circuits a, c, e and g can accept only positive and
FET Source-Follower Circuits
small negative signals, because these circuits have
The common-drain amplifier, or source follower, is a their source resistors connected to ground. The other
particularly valuable configuration; its high input circuits can handle large positive and negative signals
impedance and low output impedance make it very useful limited only by the available supply voltages and de-
for impedance transformations between FETs and bipolar vice breakdown voltage.
transistors. By considering eight circuits (Figure 9),
Circuits c, d, g and h employ current sources to im-
which represent virtually every source-follower
prove drain-current (ID) stability and increase gain.
configuration, the designer can obtain consistent circuit
performance despite wide device variations.
Circuits d and h employ JFETs as current sources.
There are two basic connections for source followers: Circuits d, f and h employ a source resistor, RS, which
with and without gate feedback. Each connection comes may be selected to set the quiescent output voltage
in several variations. Circuits 9a through 9d have no gate equal to zero.
feedback; their input impedances, therefore, are equal to
RG. Circuits 9e through 9h employ feedback to their gates Circuits d and h use matched FETs. RS is selected to
to increase the input impedance above RG. set ID . The dc input-output offset voltage is zero.
A Q1
RG R S1
B
RG RS RG RS RG IS C Q2
R S2
D
–VSS
–VSS
(a) (b) (c) (d)
Q1
RG R S1
RG RS RG RS RG RS
Q2
R S2
R1 R1 IS
–VSS –VSS
Figure 9. Virtually every practical source-follower configuration is represented in this collection of eight circuits. The
configurations in the top row do not employ gate feedback; the corresponding configurations in the bottom row
employ gate feedback.
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1.5 1.5
VDS = 15 V VDS = 15 V
2N4339
1.2 1.2
ID (mA)
TA = 25_C
ID (mA)
0.9 RS = 1 k 0.9
0
0 –0.4 –0.8 –1.2 –1.6 1.2 0.8 0.4 0 –0.4 –0.8 –1.2 –1.6
VGS (V) VGS (V)
Figure 10. Self-biasing (Figure 9a) uses the voltage Figure 11. Adding a VSS Supply to the self-bias circuit
dropped across the source resistor, RS to bias (Figure 9b) allows it to handle large negative
the gate. The load line passes through the signals. The load line’s intercept with the VGS
origin and has a slope of –1/RS. axis is at VGS = VSS. Bias Lines are shown for
VSS = –15 V and VSS = –1.6 V.
1.5 1.5
VDS = 15 V VDS = 15 V
1.2 1.2
I D (mA)
0.9 RS = 1 k
ID (mA)
0.8
0
0 –0.4 –0.8 –1.2 –1.6 0.8 0.4 0 –0.4 –0.8 –1.2 –1.6
VGS (V) VGS (V)
Figure 12. This load line is set by RS2 and Q2 which acts as a Figure 13. The bias load line is set by RS but the output load
current source (Figure 9d). This source follower, line is determined by RS + R1 when gate feedback
therefore, exhibits zero or near-zero offset. If the FETs is employed (Figure 9e). The feedback VFB is
are matched at the operating ID, the source follower determined by the intercept of the RS + R1 load
will exhibit zero or near-zero temperature drift. line and the VGS axis.
Biasing Without Feedback Is Simple A pair of matched FETs is used in the circuit of Figure 9d,
one as a source follower and the other as a current source.
Circuit 9b is an example of source-resistor biasing with The operating drain current (IDQ) is set by RS2, as
a –VSS supply added. The advantage over circuit 9a is indicated by the load line of Figure 13. In this illustration
that the signal voltage can swing negative to the drain current may be anywhere from 0.2 to 0.42 mA,
approximately –V SS . Two bias lines are shown in as shown by the limiting transfer characteristic intercepts;
Figure 11, one for V SS = –15 V and the other V SS = however, VGS1 = VGS2 because the FETs are matched.
–1.6 V. For the first case, the quiescent output voltage Other dual devices, such as 2N5912 and SST441, can
lies between 0.18 and 0.74 V. For the second, it lies operate at 5 mA and frequencies above 400 MHz.
between 0.3 and 0.82 V.
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AN102
1.5 feedback. The bias load line is set by RS (Figure 13). The
VDS = 15 V
output load line, however is determined by the sum of RS
1.2 + R1. The feedback voltage VFB, measured at the junction
I D (mA)
2 2
SST5484 2N4339 Max. SST/J202 Max.
1 SST/J201 Max. 2N5484 Max. 1
I D – Drain Current (mA)
0.5 0.5
0.01 0.01
0.1 0.5 1 5 10 0.1 0.5 1 5 10
RS – Source Resistance (kW) RS – Source Resistance (kW)
Figure 15. JFET Source Biased Drain-Current Figure 16. JFET Source Biased Drain-Current
vs. Source Resistance vs. Source Resistance
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VDD 200
g fs R D
AV 1 R g
D os
160 Assume VDD = 15 V, VDS = 5 V
RD
10 V
A V – Voltage Gain
RD I
VO 120 D
VIN 2N4338/9
SST/J201
80
SST/2N5485
RG RS CS
40 SST/J202
0
0.01 0.1 1
ID – Drain Current (mA)
Figure 17. JFET Source Biased Amplifier Figure 18. Circuit Voltage Gain vs. Drain-Current
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