2016 Euromicro Conference on Digital System Design
Design of Efficient 1’s Complement
Modified Booth Multiplier
Kiamal Pekmestzi
Dept. of Electrical and Computer Engineering
National Technical University of Athens
15780 Athens, Greece
pekmes@microlab.ntua.gr
Abstract— The 2’s complement representation is widely
adopted, since compared to the other signed number systems has
the advantage of simpler addition and single representation of
zero. Sing-magnitude representation is used in digital signal
processors for the representation of digital signals for low-power
purposes. The 1’s complement representation compared to the
2’s complement one has the advantages of the simpler conversion
to and from the sign-magnitude representation, simpler negation
and that truncation of negative numbers is equivalent to that of
the sign-magnitude representation. Therefore, the design of
efficient arithmetic units for this system should be examined. In
this work 1’s complement modified Booth multipliers with
complexity similar to that of the 2’s complement ones are
proposed.
Keywords— Multiplier; 1’s complement; 2’s complement; sign-
magnitude; modified Booth; digital signal processing
I. INTRODUCTION
Digital signal processing (DSP) is one of the core
technologies in multimedia and communication systems
leading to an increasing demand for high speed and low-power
digital signal processors [1]. The 2’s complement number
system is the most commonly employed in practice for general
purpose fixed-point DSP systems [2]. Its advantage over the
sign-magnitude and 1’s complement representations is the
simplicity of addition and the single representation of zero. A
drawback of its use in DSP systems is the large number of
redundant leading 1s required to represent small negative
numbers. Thus, for digitized signals with small fluctuations
around zero, there is high switching activity in the sign
extension bits and as a result, high power consumption [3], [4].
The use of the sign-magnitude number system, avoids the
extra switching activity of the sign extension bits, as only one
bit is used to represent the sign [3], [4]. The drawback of this
number system is the complexity of the addition which is the
most often used arithmetic operation in DSP. The use of sign-
magnitude adders [5], [6] has a penalty in area, power and
delay compared to a conventional 2’s complement ones. An
alternative way to perform the sign-magnitude operations is to
convert the operands into a 2’s complement format and to use
internal to the DSP system conventional 2’s complement
arithmetic units. Each converter is composed of a row of XOR
gates and an incrementer. The use of these converters has a
penalty of area, power and delay. According to [3], [4] sign-
978-1-5090-2817-7/16 $31.00 © 2016 IEEE
DOI 10.1109/DSD.2016.53
Constaninos Efstathiou
Dept. of Informatics
Technological Educational Institute of Athens
12210 Athens, Greece
cefsta@teiath.gr
magnitude representation is preferred in designs where large
capacitive loads are being driven such as I/O buses, etc. In this
case the power overhead of converting to and from the 2’s
complement representation is lower compared to the power
saving from the reduced switching activity on the bus. The 1’s
complement number system compared to the 2’s complement
one has the advantage of the simpler conversion to and from
the sign-magnitude representation, since only a single row of
XOR gates is required. Therefore, the overhead of the
conversion to and from the sign-magnitude representation is
lower. The 1’s complement representation has not been widely
used as traditionally had the drawback of the complex addition
operation and double representation of zero. This disadvantage
has led to the lack of investigation for the design of the rest of
the arithmetic units such as multipliers, fused multipliers-
adders, etc. However these drawbacks have eliminated, since
efficient 1’s complement adders which operate as fast as their
corresponding 2’s complement ones have been proposed in [7]-
[12], while 1’s complement adders with single representation
of zero are also proposed in [9], [12]. Another advantage of the
1’s complement arithmetic is the simpler negation operation. It
also has the advantage that in fixed point arithmetic, truncation
of negative numbers is equivalent to magnitude truncation [13].
Since multipliers have a significant impact on the
performance of DSP systems, high-performance and efficient
multiplication algorithms and implementations are required.
Various 2’s complement multiplication algorithms such as
Braun, Baugh-Wooley, Booth, modified Booth have been
proposed [5], [6], [14]-[20]. The modified or radix-4 Booth
multiplication algorithm reduces the number of partial products
which added and is known as one of the most efficient
multiplication schemes. Efficient 2’s complement modified
Booth multipliers are widely proposed in the literature.
Compared to the other two common signed integer
representations (sign-magnitude and 2’s complement), 1’s
complement multiplication has not been much discussed in the
literature, and most textbooks on computer arithmetic and DSP
simply omit the subject. Actual implementations have been
even rarer. A fast 1’s complement multiplication algorithm is
proposed in [21], while a first attempt to design a 1’s
complement multiplier using modified Booth encoding is
described in [22]. However, the algorithm in [22] leads to
multipliers with increased complexity compared to the 2’s
complement ones. A multiplier with one of its operands in 1’s
238
complement format and the other in minimum signed digit X 2 j = − xm−1 2 m+ j −1 + xm−1 2 j + xm−2 2 m+ j −2 + ! + x1 2 j +1 + x0 2 j
representation is proposed in [23].
= (−1 + xm−1 )2 m+ j −1 + xm−1 2 j + xm−2 2 m+ j −2 + ! + x1 2 j +1 + x0 2 j
In this work, we propose a new efficient 1’s complement
modified Booth (MB) multiplication algorithm. The proposed
= x m −1 2 m + j −1 + x m − 2 2 m + j − 2 + ! + x1 2 j +1 + x 0 2 j + x m −1 2 j − 2 m + j −1
MB multipliers are more efficient than the multipliers proposed
in [22] and its hardware complexity is similar to the 2’s m −2
complement MB multipliers. 1’s complement MB multipliers
with single representation of zero are also presented.
= xm−1 2 m+ j −1 + ¦x 2
i =0
i
i+ j
+ xm−1 (2 j − 2 k ) + ! + xm−1 2 k − 2 m+ j −1

The rest of the paper is organized as follows. In Section II, m−2

we present the proposed 1’s complement MB multiplication = x m −1 2 m+ j −1 + ¦x 2
i =0
i
i+ j
+ x m−1 (2 j −1 + 2 j −2 + ... + 2 k ) + ! + x m−1 2 k − 2 m+ j −1
algorithms. In Section III, we experimentally evaluate our
or X 2 j = xm −1 xm − 2 ! x1 x0 xm −1...xm −1 00 m −1+ j .

0 + xm −1 2 − 2
k
design in comparison with the conventional 2’s complement  ...
 

ones. Section IV concludes the paper. j −k k

The partial products AbiMB 2 2i in relation (3) are computed

II. DESIGN METHOD
as follows:
Let A1' s = a n −1 a n − 2 ... a1 a 0 and B1' s = bn −1b n − 2 ...b1b0 be the
n-bit 1’s complement representations of the signed numbers A If biMB = 1 , then AbiMB 2 2i = A2 2i = (an −1an − 2 ! a1a0 )2 2i
and B in the range [ −(2n −1 − 1), + (2n −1 − 1)] . Since 2n-1 bits are = (a n −1 a n −1 a n − 2 ! a1 a 0 )2 2i . Using relation (4) of Lemma 1 with
required for the representation of the product Q = A × B , its j=2i and k=2i, we get that
1’s complement representation will be of the form n + 2i
A2 2i = an −1an −1an − 2 ! a1a0 00

0 + an −1 2 − 2
... 2i
.
Q1' s = q 2 n − 2 q 2 n − 3 ... q1q 0 . The multiplier B is modified Booth
2i
encoded in order to reduce the number of the partial products.
The value of the multiplier B is given by the relation If = 2 , then
biMB = A2 2i +1 . From relation (4)
AbiMB 2 2i
with k=2i and j=2i+1 we get that
B = −( 2n −1 − 1)bn −1 + bn − 2 2n − 2 + ... + b2 22 + b1 2 + b0 (1) A2 2i +1 = an −1an − 2 ! a1a0 an −1 00 n + 2i

0 + an −1 2 − 2
2i
 ... .
2i
For even values of n the modified Booth encoding of B is
If biMB = −1 , then AbiMB 2 2i = − A2 2i
=

n / 2 −1 = (an −1an − 2 ! a1a0 )2 2i = (an −1an −1an − 2 ! a1a0 )2 2i .

B= ¦ i =0
biMB 2 2i (2)
The number –A in 1’s complement representation is
obtained by inverting all bits of A. For k=2i and j=2i, we get
that
where biMB = −2b2i +1 + b2i + b2i −1 are the modified Booth digits
n + 2i
and b-1=bn-1. Thus, the product Q is given by the relation − A2 2i = an −1an −1an − 2 ! a1a0 00

0 + an −1 2 − 2
... 2i
.
2i

n / 2 −1 If biMB = −2 , then AbiMB 2 2i = − A2 2i +1 from relation (4)

Q= ¦ Ab
i =0
i
MB 2i
2 . (3)
for k=2i and j=2i+1 we get that

− A2 2i +1 = an −1an − 2 ! a1a0 an −1 00

0 + an −1 2 − 2
... 2i n + 2i
.
The proposed design of the 1’s complement MB multiplier 2i
is based on the following Lemma:
n + 2i
If biMB = 0, then 0 = 100
 !

0 − 2 .
Lemma 1. Let X 1' s = xm −1 xm − 2 ! x1 x0 the m-bit 1’s n +1+ 2i

complement representation of a signed number X, then Concluding, each partial product in relation (3) is computed
as AbiMB 2 2i = PPi + Ri , where operands PPi and the
X 2 j = xm −1 xm − 2 ! x1 x0 xm −1...xm −1 00...0 + x 2 k − 2 m −1+ j (4)
 

m −1 corresponding correction terms Ri are shown in Table I.
j −k k
Operands PPi are of the form
where kj are arbitrary integers.
PPi = pi, n pi, n −1 pi, n − 2.... pi ,1 pi,0 00
 ...

0 .
Proof. Since X = − xm −1 (2m −1 − 1) + xm − 2 2m − 2 + ! + x1 2 + x0 , then 2i

239
 TABLE I. FORMATION OF THE PARTIAL PRODUCTS

b2i +1 b2i b2i −1 Meaning PPi Ri

biMB
100
 !
00

0 0 0 0 0 0-2 n+2i
n +1+ 2i

an −1an −1an − 2 !a1a0 00

 ...

0
0 0 1 1 +A22i an-122i-2 n+2i
2i

an −1an −1an − 2 !a1a0 00

 ...

0
0 1 0 1 +A22i an-122i-2n+2i
2i

an −1an − 2 !a1a0 an −1 00
 ...

0
0 1 1 2 +A22i+1 an-122i-2n+2i
2i

an −1an − 2 !a1a0 an −1 00
 ...

0
1 0 0 -2 -A22i+1 an −1 2 2i -2n+2i
2i

an −1an −1an − 2 !a1a0 00

 ...

0
1 0 1 -1 -A22i an −1 2 2i -2 n+2i
2i

an −1an −1an − 2 !a1a0 00

 ...

0
1 1 0 -1 -A22i an −1 2 2i -2n+2i
2i

100
 !
00

1 1 1 0 0 0-2 n+2i
n +1+ 2i

n / 2 −1 n / 2 −1 n / 2 −1
Then, Q = ¦ PP + ¦ R
i =0
i
i =0
i −( ¦2 n + 2i
+ 1) is of the form COR = −(010
 ...101

00
...
001

) .

i =0 n n

n / 2 −1 n / 2 −1 n / 2 −1
Therefore, its 2’s complement representation is
or Q = ¦ PP + ¦ p
i =0
i
i =0
i,n 2
2i
− ¦2i =0
n + 2i
(5) COR2' s = 101...
  01011 ...


11
n
.
n

where pi , n are the inverse of the most significant bits of the The bit with weight 22n-1 of COR2' s is ignored considering
partial products PPi. that it does not affect the (2n-1)-bit result. We get that,

Consider Q1' s = q2 n − 2 q2 n − 3 ...q1q0 the 1’s complement

n / 2 −1
representation of Q. Thus,
2n − 2 2n −3
Q= ¦ PP + Cin + COR
i =0
i 2 's + q 2n−2 (7)
Q= − q2 n − 2 (2 − 1) + q2 n − 3 2 + ! + q1 2 + q0
The value of vector q 2 n −2 q 2 n −3 ...q1q 0 as a 2’s complement n / 2 −1

number is where Cin = ¦p

i =0
i,n 2
2i
and COR2' s = 01
...
010

11
 ...

 11 .
n −1 n
Q2’s= − q 2 n −2 2 2 n − 2 + q 2 n −3−2 2 2 n −3 + ! + q1 2 + q 0 = Q-q2n-2 =
The sign bit q2n−2 is computed by the relation
n / 2 −1 n / 2 −1 n / 2 −1 q2n−2=an−1⊕ bn−1. The partial products derived according to the
= ¦ PP + ¦ p
i =0
i
i =0
i ,n 2
2i
− ¦2
i =0
n + 2i
− q 2n−2 or proposed algorithm are added using a Carry Save Adder (CSA)
Wallace tree [24]. The output vectors of the CSA tree are
added using a (2n-1)–bit Carry Look Ahead (CLA) adder [10].
n / 2 −1 n / 2 −1 n / 2 −1
Bit q2n − 2 is used as carry input to final stage CLA adder.
Q2’s= ¦ PP + ¦ p
i =0
i
i =0
i ,n 2
2i
− ¦2
i =0
n + 2i
− 1 + q 2n−2 (6)
Equivalently bit q2n − 2 can be added through the Wallace CSA
tree. The result Q of the multiplication is in 1’s complement
Relation (6) implies that Q can be computed using 2’s form. The block diagram of the proposed 1’s complement MB
complement addition of the summands in (6). However bits qi multipliers is given in Fig. 1.
represent the number Q in 1’s complement form. Term

240
 A1's Example. Let A1' s = a 7 a 6 ... a1a 0 and B1' s = b7 b6 ...b1b0 be the 8-
bn-1
PP0 Generator
3 bits
b0 bit 1’s complement representations of the multiplicand A and
010...10 1111...11 b1 the multiplier B. The multiplier B is MB encoded as:

MB Encoding
3 bits b2
(n-1)-bit n-bit PP1 Generator
b3
3 bits b4 B1's B = b3MB 26 + b2MB 24 + b1MB 22 + b0MB .
PP2 Generator b5
2n-1
The following partial products are derived according to our
3 bits
PPn/2-1 Generator bn-2 methodology:
bn-1

pn/2-1,n 0…0 p1,n 0 p0,n

Bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Wallace CSA Tree (n-1)-bit
PP0= p0,8 p0,7 p0,6 P0,5 p0,4 p0,3 p0,2 p0,1 p0,0
C S PP1= p1,8 p1,7 p1,6 p1,5 p1,4 P1,3 p1,2 p1,1 p1,0 p0,8
q2 n−2 PP2= p2,8 p2,7 p2,6 p2,5 p2,4 p2,3 p2,2 P2,1 p0,0 p1,8
CLA Adder

Q1's=(A× B)1's PP3= p3,8 p3,7 p3,6 p3,5 p3,4 p3,3 p3,2 p3,1 p3,0 p2,8
COR= -1 -1 -1 -1 p3,8 -q14
Fig. 1. Block diagram of the proposed 1’s complement Booth multiplier. q14 q13 q12 q11 q10 q9 q8 q7 q6 q5 q4 q3 q2 q1 q0

Various schemes of the MB encoder and the partial product

generator (PPG) have been proposed in the literature and can where q14=a7⊕b7. Using the 15-bit 2’s complement
also be used in the proposed 1’s complement multipliers. An representation of the constant correction we get the following
efficient MB encoder module implementation is given in partial products:
Fig. 2. The output encoding signals s, two and one of the MB
encoders are driven to the appropriate inputs of the PPGs
which compute the partial products PPi. The design of the PPG Bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
module is given in Fig. 3. According to our analysis (Lemma 1 PP0= p0,8 p0,7 p0,6 P0,5 p0,4 p0,3 p0,2 p0,1 p0,0
and Table I), an = an −1 and a−1 = an −1 . PP1= p1,8 p1,7 p1,6 p1,5 p1,4 P1,3 p1,2 p1,1 p1,0 p0,8
PP2= p2,8 p2,7 p2,6 p2,5 p2,4 p2,3 p2,2 P2,1 p0,0 p1,8
Inputs Outputs
Digit PP3= p3,8 p3,7 p3,6 p3,5 p3,4 p3,3 p3,2 p3,1 p3,0 p2,8
b2j+1 b2j b2j-1 sj twoj onej
p3,8 q14
0 0 0 0 0 0 +0
one j b2 j−1 COR2’s= 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1
0 0 1 0 0 1 +1
q14 q13 q12 q11 q10 q9 q8 q7 q6 q5 q4 q3 q2 q1 q0
0 1 0 0 0 1 +1
0 1 1 0 1 0 +2
b2 j
two j
1 0 0 1 1 0 -2 b2 j+1
The derived partial products are summed be a CSA
1 0 1 1 0 1 -1 sj Wallace tree and a final stage 15-bit parallel adder with input
1 1 0 1 0 1 -1 carry. Bit q14 is used as input carry to the final stage adder.
1 1 1 1 0 0 -0
We now consider a numerical example with 8-bit input
operands and the results in 1’s complement form.
Fig. 2. Truth table and implementation of the MB encoder module.
If A=37=00100101, B=-23=11101000 then

si a j
b0MB =+1 , b1MB =−2 , b2MB =−1 , b3MB = 0
sj twoj onej pi,j
0 0 0 0 si ⊕a j−1
si ⊕a j
0 0 1 aj PP0 = 1 0 0 1 0 0 1 0 1
onei twoi
PP1 = 0 1 0 1 1 0 1 0 1 0
0 1 0 aj-1
PP2 = 0 1 1 0 1 0 1 1 0 1
1 1 0 a j −1 PP3 = 1 0 0 0 0 0 0 0 0 1
0 0
1 0 1 aj 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1
-851 = 1 1 1 1 1 0 0 1 0 1 0 1 1 0 0
1 0 0 0 pi , j

Fig. 3. Truth table and implementation of the PPG nodule.

241
1’s Complement multipliers with single representation of zero. TABLE II. IMPLEMENTATION RESULTS OF THE PROPOSED 1’S
COMPLEMENT WITH A 2’S COMPLEMENT MULTIPLIER

1’s complement multipliers with single (all 0s) 16 bits

representation of zero can also designed using the proposed Delay Comparison of the proposed
2’s Complement 1’s Complement
methodology. According to relation (5) we get that (ns) with 2’s Complement
n / 2 −1 n / 2 −1 n / 2 −1 n / 2 −1 Area Power Area Power
¦ ¦ ¦ ¦
Area Power
Q1's = PPi + pi , n 2 2i − 2n + 2i . Operand − 2 n + 2i (um2) (mW) (um2) (mW)
1.08 7345 6.60 - - - -
i =0 i =0 i =0 i =0
1.12 6887 6.08 7451 6.36 -8.20% -4.61%
is of the form COR = −(010
 ...101

00
...
000

) . Therefore, its 1’s
 1.50 5361 3.51 5540 3.70 -3.34% -5.53%
n n 2.00 5170 2.44 5389 2.55 -4.23% -4.72%
complement representation is COR1' s = 101
 ...010

11 ...

 11 . The 2.50 5101 1.94 5288 1.94 -3.67% -0.26%

n n 24 bits
term 22n-1 of COR1' s is ignored, considering that it does not Delay Comparison of the proposed
2’s Complement 1’s Complement
(ns) with 2’s Complement
affect the (2n-1)-bit result. Then COR1' s = 01
...
010

11
 ...

 11 .
Area Power Area Power
n n Area Power
(um2) (mW) (um2) (mW)
n / 2 −1

¦p
1.25 15460 12.00 16023 11.70 -3.64% 2.51%
Operands PPi, Cin = i,n 2
2i
and COR1’s are added by 1.50 11436 7.35 11822 7.66 -3.38% -4.20%
i =0 2.00 10784 5.37 11132 5.50 -3.23% -2.50%
CSA Wallace tree [24]. The output vectors C, S of the CSA 2.50 10632 4.01 11009 4.37 -3.54% -8.74%
adder are added by a (2n-1)-bit wide 1’s complement adder 32 bits
with single representation of zero [10], [13]. The 1’s Delay Comparison of the proposed
2’s Complement 1’s Complement
complement multipliers with simple representation of zero (ns) with 2’s Complement
have the architecture of Fig. 1. This algorithm has also the Area Power Area Power
Area Power
advantage that it can easily extended to the design of fused 1’s (um2) (mW) (um2) (mW)
complement multiply-add units. 1.36 25155 17.51 25769 18.23 -2.44% -4.10%
1.50 20782 13.60 21326 13.90 -2.62% -2.21%
2.00 18326 9.18 18737 8.89 -2.24% 3.18%
III. COMPARISONS 2.50 18103 7.84 18483 7.78 -2.10% 0.68%

Up to now, the only 1’s complement  multiplier found

in literature is the proposed in [22]. The multiplication
algorithm in [22] has the drawback that each partial product
PPi has its 2i least significant bits equal to the most significant
bit leading to 50% more partial product terms which increases
proportionally the CSA tree hardware complexity. This
drawback is eliminated in the proposed 1’s complement MB
multiplication algorithm as the produced partial products have
similar form to those of the conventional 2’s complement MB
multiplier. The only difference is that an extra vector of n 1’s
(11...
we consider are described in structural Verilog HDL with
registered inputs and outputs and verified for their correctness.
They are synthesized using the Synopsys Design Compiler and
the TSMC 90nm standard cell library in typical conditions. The
synthesis was conducted considering the highest degree of
optimization in Synopsys Design Compiler. We synthesized
each design at the highest achievable frequency and then at
lower frequencies targeting to explore how both designs

11) is added along with the partial products, which behave considering different timing constraints in terms of area
 and power consumption. For each frequency, we simulated
n
both designs using ModelSim for the same set of 216 random
however does not introduce significant overhead. Actually, the
numbers. The inputs were generated randomly with equal
generation of the Cin term in 2’s complement multipliers
possibility of a bit to be 0 or 1. Finally, we used Synopsys
requires extra hardware, while in the proposed 1’s complement
PrimeTime-PX to calculate power consumption.
multiplier can be reused from the MSB of the partial products.
Consequently in an optimized e.g. full-custom design 1’s We observe that the delay, area and power measurements
complement multipliers it is possible to outperform the of the proposed 1’s complement MB multipliers are similar to
corresponding 2’s complement. Also, in the case of truncated the corresponding ones of the 2’s complement MB multipliers.
multipliers [25] this extra vector can be merged without More specifically, in the cases of 24 and 32 bits of input width,
overhead with the correction term used in the truncation. we observe that the lowest clock-periods that the 1’s and the
2’s complement MB multipliers achieve are the same. In the
In Table II the proposed 1’s complement Booth multiplier
case of 16 bits of input width, the 1’s complement MB
is compared with the conventional 2's complement MB one
multiplier delivers timing functional solutions which are only
with respect to the input width (i.e. 16, 24 and 32 bits). For the
by 40 ps slower than the ones of the 2’s complement MB
implementation of both multipliers we use the same MB
multiplier. Regarding area complexity and power dissipation,
encoders, PPGs, CSA trees and final stage adders. The CSA
the 1’s complement MB multiplier shows an average loss of
Wallace tree and the final stage adders have been imported
3.18% and 1.82% compared to the area occupied and the
from the Synopsys DesignWare Library. All the designs that
power consumed by the 2’s complement MB multiplier

242
respectively. Concluding the proposed 1’s complement MB
multipliers with complexity similar to that of the 2’s
complement ones are also proposed.
Traditionally the 2’s complement number system compared
to the 1’s complement one had the advantages of simpler
addition and the single representation of zero. In resent years
this advantage is eliminated, since 1’s complement adders with
single representation of zero which operate as fast as their 2’s
complement ones are proposed [9], [12]. The 1’s complement
number system has the advantage of the efficient conversion to
and from the sign-magnitude number system and the simpler
negation. Another advantage when 1’s complement
representation is used in DSP systems is that truncation of
negative fractional numbers is always equivalent to sign-
magnitude truncation. However in 2’s complement number
system, the truncation of negative fractional numbers is not
equivalent to magnitude truncation [13]. In some cases this can
lead to numbers which cannot be presented in sign-magnitude
form. For example, let the result of a multiplication is the
number 1.0001101 (=−0.1110011). The truncation of this
number to 4 bits in 2’s complement form is 1.000=-1 which
does not correspond to a number in sign-magnitude
representation.
IV. CONCLUSIONS
The 1’s complement number system is an interesting
alternative to the conventional 2’s complement one for the
representation of signed integers. It has the advantage of the
simple translation to and from the sign-magnitude one and the
equivalent magnitude truncation. Comparing the proposed 1’s
complement MB multipliers with their corresponding 2’s
complement ones, in most cases the lowest clock-periods are
the same. Also, the proposed 1’s complement multipliers have
area and power complexity, which are similar to their
corresponding 2’s complement multipliers. The use of the
proposed 1’s complement MB multipliers along with the
already proposed 1’s complement adders can be considered in
the design of DSP systems, where the sign-magnitude
representation is used for low power purposes.
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