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Jiaqi Wei1Ъ, Liang Chang1Ъ, Zhaohao Wang1, Xiaoyang Lin1, Kaihua Cao1,2, Hushan Cui1,2,
Wang Kang1, Haoxuan Chen1, Lang Zeng1, Youguang Zhang1, Chao Zhao1,2, Weisheng Zhao1*
1
Fert Beijing Research Institute, BDBC & School of Electronic and Information Engineering, Beihang University,
Beijing 10191, China
2
Institute of Microelectronics of Chinese Academy of Sciences
* Email: weisheng.zhao@buaa.edu.cn
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magnetic field is large enough (e.g., 48mT, after 5.05 ×
10e11 A.m-1). For the impact of filed-like torque, the pro-
gramming delay increase significantly when the factor
grows from 0.2 to 0.8, then shows a decrease when the
factor larger than 1.0, as shown in Fig. 5 (b). Note that, in
some values of factor (e.g., red line, 0.6 and 0.8), the pro-
gramming is failed since the current density or/and mag-
netic field is not sufficient.
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IPC Performance: With the same capacity (1MB), we Acknowledgement
evaluate the performance of on-chip cache under various The authors would like to thank the supports by the projects
benchmarks as shown in Fig. 6. Thanks to the advantage from National Natural Science Foundation of China (No.
of the SOT-cache in write operation, some benchmarks 61571023, 61501013 and 61627813), Beijing Municipal of Sci-
achieve significant performance improvement (e.g. Bzip2). ence and Technology (No. D15110300320000), the International
Nevertheless, a few benchmarks suffer from little im- Collaboration Projects No.2015DFE12880 and No. B16001.Jiaqi
provement due to infrequent data communication with Wei and Liang Chang contribute equally to this paper.
off-chip memory. The maximum performance improve-
ment can be up to 12%, and the average improvement is References
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