Introduction to VLSI:

Electronics industry has achieved a phenomenal growth over the last two decades,
mainly because of the rapid increases in integration technologies, large-scale systems
design. The applications of integrated circuits have been rising steadily which are used in
high-performance computing, telecommunications, and consumer electronics. Typically,
the required computational power of these applications is the driving force for the fast
development of this field. Figure 1.1 shows an overview of the prominent trends in
information technologies over the coming few decades.
The current leading-edge technologies such as low bit-rate video and cellular
communication. This trend is expected to continue, with very important applications on
VLSI and systems design. One of the most important features of information services is
their increasing need for very high processing power and bandwidth. The next important
characteristic is that the information services become more and more personalized such
as broadcasting, which means that the devices must be more intelligent to answer
individual demands and at the same time they must be portable to allow more
flexibility/mobility.
When data processing and telecommunications devices require more and more
complex functions, they need to integrate these functions in a small system. The number
of logic gates in a monolithic chip will decide the level of integration which has been
steadily increasing for nearly three decades, which is because of the rapid process in
processing technology and interconnect technology. Table 1.1 shows the evaluation of
logic complexity in integrated circuits over the last three decades. From the above fig. the
circuit complexity should be interpreted only as representative examples to show the
order of magnitude. A logic block can contain anywhere from 10 to 100 transistors,
depending on the function.

Table 1.1: Evolution of logic Complexity in Integrated Circuits

 ERA(number of
logic blocks per DATE COMPLEXITY
chip)
Single transistor 1959 less than 1
Unit logic (one
1960 1
gate)
Multi-function 1962 2–4
Complex
1964 5-20
function
Medium Scale
Integration 1967 20 – 200
(MSI)
Large Scale
1972 200 – 2000
Integration(LSI)
Very Large
Scale
1978 2000-20000
Integration
(VLSI)
Ultra Large
Scale
1989 20000-?
Integration
(ULSI)

The most important thing is that the logic complexity per chip has been increasing
exponentially. The monolithic integration of a large number of functions on a single chip
normally provides:
 Less area or volume
 Low power consumption
 Small testing requirements at system level
 High reliability
  High speed

The current trend of integration will also continue in the foreseeable future. Rapid
increases in device manufacturing technology and the steady reduction of minimum feature size
support this trend. After comparing the density of integrated circuits, a clear difference must be
made among the memory chips and logic chips. Figure 1.1 shows the level of integration
overtime for memory and logic chips. From the below figure, it is clear that the transistor count
for logic chips are less compared to the memory chips. The reason is, the memory chips contains
large complex inter connections. The memory circuits are highly regular and thus it requires
more cells with less area for interconnections.

Figure 1.1 Level of integration over time, for memory chips and logic chips.

1.3 VLSI Design Flow:

At different levels, the design process, is usually evolutionary in nature. It starts from a
set of requirements. First, initial design is developed and tested against the requirements. When
the requirements are not met, the design has to be improved. If such improvement is not possible
and costly, then the requirements are again revised and its impact analysis must be considered.

The Y-chart consists of the three major domains:

 1. Behavioural domain
2. Structural domain
3. Geometrical layout domain

Figure 1.2 Typical VLSI design flow in three domains.

The design flow starts from the algorithm that describes the behaviour of the target chip. The
architecture of the processor is first defined. Floor-planning method is used to map the processor
onto the chip surface. The behavioural domain defines the finite state machines which are
structurally implemented with functional modules such as registers and arithmetic logic units.
Then the modules are geometrically placed onto the chip surface using CAD tools. The next
evaluation starts with a behavioural module description.

Individual modules are then implemented with leaf cells, at this stage the chip is describes in
terms of logic gates. The last evaluation involves a detailed Boolean description of leaf cells
followed by a transistor level implementation of leaf cells. In standard base cell design, the leaf
cells are already pre-designed and saved in a library for logic design use.