1. If set A of the universal set U which of the following expression is true?

a. ¬A ∩ U = A
b. A – U = A
c. A ᴜ U = A
d. A ⊕ U = ¬A
2. Simulate the given instructions (below) and determine which among the choices is correct.
Initially CF=0; AF=0; ZF=0; SF=0; PF=0.
MOV AL, D6
MOV BL, E5
ADD AL, BL
a. CF=1; AF=1; ZF=0; SF=1; PF=0
b. CF=1; AF=1; ZF=0; SF=0; PF=1
c. CF=1; AF=0; ZF=0; SF=0; PF=1
d. CF=1; AF=1; ZF=1; SF=1; PF=1
e. None of the choices
f. CF=1; AF=0; ZF=0; SF=1; PF=1
3. Determine the property or properties of the relation of the set of integers to the set of
integers where (x,y) ∈ R if x is a multiple of y.
a. Symmetric
b. Reflexive, antisymmetric, transitive
c. Reflexive, antisymmetric, symmetric, transitive
d. Antisymmetric, transitive
e. Reflexive, symmetric, transitive
f. Reflexive, symmetric
g. Reflexive, transitive
4. Perform the binary division 111110011 ÷ 1001 to obtain the quotient.
a. 10010
b. 10101
c. 10111
d. 11011
e. None of the choices
f. 11101
5. How many clock cycles would it take to finish seven instructions in an 8-stage non-pipelined
processor?
a. 14
b. None of the choices
c. 24
d. 54
e. 16
f. 56
6. Determine the total memory access time for a series of instructions in a system with RAM
access time of 105 ns and cache access time of 10ns. Assume hit ratio of 0.75.
a. 42.5ns
b. 37.5ns
c. 38.75ns
d. 36.25ns
e. 35.75ns
f. None of the choices
7. The equivalent of 0.1010 base 2 in decimal is _________.
a. 0.8756
b. 0.6275 (nearest, Actual = 0.625)
c. 0.5672
d. 0.5786
e. 0.6758
8. Determine the equivalent statement of ¬Ǝx P(x).
a. ¬ ∀ x P(x)
b. ∀ x ¬P(x)
c. ¬Ǝx ¬P(x)
d. Ǝx ¬P(x)
9. In the game of tic-tac-toe, every game ends with one player winning or with a draw. In a tic-
tac-toe tournament, the player merely counts the number of times they win or draw. The
winner is the player with the larger count. If a match between player A and player B consists
of 25 games, player A scored 19 and player B scored 23, how many draws were there?
a. 10
b. 21
c. 29
d. 17
10. Suppose the universe of discourse of the propositional function P(x, y) consists of pairs x and
y, where x is (1, 2, 3) and y is (1, 2, 3). Represent the proposition ∀ y P(1, y).
a. P(1,1) ˄ P(1,2) ˄ P(1,3)
b. P(1,1) v P(1,2) v P(1,3)
c. P(1,1) ˄ P(1,2) v P(2,3)
d. P(1,1) v P(2,2) v P(3,3)
e. P(1,1) v P(2,1) v P(3,1)
f. P(1,1) ˄ P(2,1) ˄ P(3,1)
11. This processor introduced streaming extensions, with 128-bit registers designed to move
large data.
a. Pentium 1
b. 80486
c. None of the choices
d. Pentium 4
e. Pentium 3
f. Pentium 2
12. Determine the least number of NAND gate that can be used to implement the expression,
(AB + A’B’)’(CD’ + C’D)
a. 12
b. 10
c. 9
d. 13
e. 14
f. 11
g. 8
13. Compute for the number of clock cycles of 9 instructions in a superpipeline system.
a. 28
b. 126
c. 180
 d. 22
e. None of the choices
f. 18
14. Determine the bitwise implication of p = 1101011 and q = 1011100
a. 0100011
b. 0010100
c. 1011100
d. 1101011
15. If both inputs of a NOR gate is inverted the resulting gate is like the connective _______.
a. AND gate
16. What segment register is accessed by the instruction MOV AX, [BP]?
a. Stack Segment
b. Data Segment
c. Extra Segment
d. None of the choices
e. Code Segment
17. Simplify F(v, w, x, y, z) = Σ m (0, 1, 2, 4, 5, 8, 9, 10, 12, 16, 17, 18, 20, 21, 24, 26, 29) using
Karnaugh map.
a. v’w’y’ + v’x’z’ + vxz + v’y’z’ + v’x’y’ + vxy’z
b. w’y’ + x’z’ + v’y’z’ + v’x’y’ + vxy’z
c. none of the choices
d. vw’y’+ v’x’z’ + vxz + v’y’z’ + v’x’y’ + v’xy’z
18. The content of a 4-bit register is initially 0110. The register is shifted 8 times to the right,
with the sequence 10110111 as the serial input. The leftmost bit of the sequence is applied
first. What is the content of the register after the 6th shift?
a. 0110
b. 1011
c. 1101
d. 1110
e. 1001
f. 1010
19. The 74LS83 is an example of a 4-bit parallel adder. To expand this device to an 8-bit adder,
you must
a. Use eight adders with no interconnections
b. Use two adders with the carry output of one connected to the carry input of the other
c. Use two adders and connect the sum outputs of one bit to the bit inputs of the other
d. Use four adders with no interconnections
20. In stack memory addressing, whenever the data are popped from the stack, which bits are
removed from the location addressed by SP?
a. Low-order 8-bits
b. No bits are removed from SP but rather on BP
c. None of the choices
d. Both low-order and high-order 8-bits
e. High-order 8-bits
f. 16 bits from BP are removed
21. The binary equivalent of decimal 1234 is _____?
a. 0001 0000 1110 0001
b. 0001 0011 0010 0100
 c. 0001 0010 0011 0100
d. 0010 0100 0110 1000
e. 0000 0100 1101 0010
22. This flag is set when the result of an unsigned operation is too large to fit into the
destination
a. Zero Flag
b. Parity Flag
c. Overflow Flag
d. Sign Flag
e. Auxiliary Flag
f. Carry Flag
23. A processor running in this mode can exploit only the lowest 20 bits of its address bus and is
therefore limited to the meager 1MB memory space.
a. Virtual mode
b. None of the choices
c. Protected mode
d. Real mode
24. What circuit technology is preferable in systems requiring low power consumption?
a. CMOS
b. TTL
c. None of the choices
d. RTL
25. It is an addressing mode in the Z80 that uses absolute jump, one-byte opcode and a 2 byte
address
a. Immediate Addressing
b. Relative Addressing
c. Extended Addressing
d. Register Direct Addressing
e. Implied Addressing
f. Register Indirect Addressing
26. What is the result of NEG AX if AX contains FFECh?
a. 0020H
b. F7D8H
c. 0014H
d. None of the choices
e. 2345H
f. 3579H
27. Exclusive-OR (XOR) logic gates can be constructed from what other logic gates?
a. AND gates, OR gates, and NOT gates
b. AND gates and NOT gates
c. OR gates and NOT gates
d. OR gates only
e. AND gates and OR gates
28. This specifies the number of loads that output of a gate can drive without comprising its
performance
a. Output Line
b. Fan-out
c. None of the choices
 d. Fan-in
e. Input line
29. The flip-flop _________ table provides the value of the next state when the values of the
inputs and the present state are known
ANS: Excitation table
30. The execution time for an alu instruction going from memory to immediate requires how
many clock cycles?
ANS: 5 clock cycles
31. Intel introduced cache memory for this microprocessor when it was launched. The Western
Design Center, Inc (WDC) introduced this microprocessor in 1982 and was used as the CPU in
the Apple IIe and IIc personal computers.
a. IMP-16
b. CMOS 8502 (CMOS 65C02 talaga yung sagot)
c. MC 6809
d. TMS 9980
32. What flag register is not affected by the arithmetic operation ADD?
a. Trap Flag
b. Sign Flag
c. Parity Flag
d. Zero Flag

33. What registers are affected by the arithmetic operation,

XOR AH, FFH
a. SF
b. TF
c. DF
d. PF
34. Intel marketed this microprocessor in April, 1972, and was the basis for the famous "Mark-8"
computer kit.
a. 8085
b. 8088
c. 8086
d. 8008
35. The minimal hypothetical microprocessor only includes
a. ALU and set of main registers
b. ALU and control logic section
c. Main registers and control logic section
d. ALU and segment registers
36. How many clock cycles would it take to finish seven instructions in an 8-stage non-pipelined
processor?
a. 56
b. 54
c. None of the choices
d. 15
37. Which of the following inputs provide a don't care in the output y given by the function F(w,
x, y, z) in a BCD to excess-of-3 code converter?
a. 1011
b. 1001
c. 0000
d. 0001
38. A 3 input XOR can be implemented using how many 2 x 1 multiplexers?
a. 4
b. 8
c. 2
d. 3
39. Express the following function as a sum of minterms: (xy + z)(y + xz)
a. x’y’z + xy’z + xyz
b. x’yz + x’y’z + xyz’+ xyz
c. x’yz + xy’z + xyz’ + xyz
d. x’y’z + xyz’ + x’y’z’
40. Which of the following inputs provide a don't care in the output z given by the function F(w,
x, y, z) in a BCD to excess-of-3 code converter?
a. 0110
b. 1010
c. 0100
d. 0010
41. The Boolean expression.(X+Y+Z)’ = X’Y’Z’ is an example of which Law/Theorem?
a. idempotent law
b. consensus theorem
c. de morgan’s law
d. commutative law
42. Using the signed-2’s complement format, the representation of -7 is __________.
a. 1001
b. 1111
c. 1000
d. 1100
43. The 4-bit magnitude comparator combinational circuit generates the final output for A < B at
what logic gate?
a. 4 input AND logic gate
b. 4 input OR logic gate
c. 4 input XOR logic gate
d. 4 input NOR logic gate
44. A race condition happens in an R-S latch when the inputs are ____
a. R = 0, S = 0
b. R = 1, S = 1
c. R = 0, S = 1
d. R = 1, S = 0
45. The Boolean expression.(X’)’ is an example of which Law/Theorem?
a. Consensus theorem
b. Involution law
c. Idempotent law
d. Commutative law
46. The 4-bit magnitude comparator combinational circuit generates the final output for A = B at
what logic gate?
a. 4 input AND logic gate
b. 4 input OR logic gate
c. 4 input XOR logic gate
d. 4 input NOR logic gate
47. The content of a 4-bit register is initially 0110. The register is shifted 8 times to the right,
with the sequence 1011 0111 as the serial input. The leftmost bit of the sequence is applied
first. What is the content of the register after the 6th shift?
 a. 1010
b. 1011
c. 0110
d. 1101
48. Design a BCD to Excess-3 Code Converter. Designate the four input binary variables by the
symbols A, B, C, D, and the four output variables w, x, y, and z. What is the Boolean
expression of the output z with respect to inputs A, B, C and D?
a. A + B’C
b. C’D’ + CD
c. A + B(C+D)
d. D’
49. Determine the essential prime implicants of the function F(w, x, y, z) = ∑(0, 2, 4, 5, 6, 7, 8, 10,
13, 15)
a. w’x and w’z’
b. xz and x’z’
c. xyz’ and wy
d. x’yz and w’y’
50. A 3 x 8 decoder contains output from D0 to D7. Which output is activated high if the input
expression x'yz'?
a. D1
b. D2
c. D4
d. D5
51. This is the time needed by a gate in processing its input signals before the output signal can
be generated
a. Threshold time
b. Setup time
c. Propagation delay time
d. Hold time
52. Simplify the Boolean function F(A, B, C, D, E) = ∑(0, 1, 4, 5, 16, 17, 21, 25, 29)
a. A’B’D’ + AD’E + B’C’D
b. B’D’E + CD’ + ABC’D
c. B’D + A’BD + ABC’E’
d. BD + B’DE + A’B’C’