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Testing and Verification of Circuits

Prof. Indranil Sen Gupta

Department of Computer Science and Engineering
Indian Institute of Technology, Kharagpur

Reference Books
1. M.L. Bushnell and V.D. Agrawal, “Essentials of Electronic
Testing”, Kluwer Academic Publishers, 2000.
2. M. Abramovici, M.A. Breuer and A.D. Friedman, “Digital
Systems Testing and Testable Design”, Wiley-IEEE Press, 1993.
3. N.K. Jha and S. Gupta, “Testing of Digital Systems”, Cambridge
University Press, 2004.
4. L-T. Wang, C-W. Wu and X. Wen, “VLSI Test Principles and
Architectures”, Morgan Kaufman Publishers, 2006.
5. P.H. Bardell, W.H. McAnney and J. Savir, “Built-in Test for VLSI:
Pseudorandom Techniques”, Wiley Interscience, 1987.

Web site: http://144.16.192.60/~isg/TESTING/index.html

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Introduction

Why Testing?
• To determine the presence of fault(s) in a
given circuit.
– No amount of testing can guarantee that a
circuit (chip, board or system) is fault-free.
– We carry out testing to increase our
confidence in proper working of the circuit.

• Verification is an alternative to testing,

used to verify the correctness of a design.
– Simulation-based approach.
– Formal methods.

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Verification v/s Testing

Verifies correctness of Verifies correctness of

design. manufactured h/w.
Performed by simulation, Two-part process:
h/w emulation, or formal 1. Test generation
methods. 2. Test application

Performed once prior to Test application

manufacturing. performed on every
manufactured device.
Responsible for quality of Responsible for quality of
design. devices.

Levels of Testing
• Testing can be carried out at various
levels:
– Chip level
– Board level
– System level
• Cost :: Rule of 10
– It costs 10 times more to test a device as
we move to the next higher level in the
product manufacturing process.

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Alternate Way of Classification

• Transistor level
Important to
• Gate lebel develop correct
• RTL level fault models and
simulation
• Functional level models
• Behavioral level

PRIMARY FOCUS OF THIS COURSE:-

Chip-level testing
Gate-level design

Some Real Defects in Chips

• Processing Faults
– missing contact windows, parasitic
transistors, oxide breakdown
• Material Defects
– bulk defects (cracks, crystal imperfections)
– surface impurities (ion migration)
• Time-Dependent Failures
– dielectric breakdown, electron migration
• Packaging Failures
– contact degradation, seal leaks
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Faults, Errors and Failures

• Fault: A physical defect within a circuit or a system
– May or may not cause a system failure
• Error: Manifestation of a fault that results in incorrect
circuit (system) outputs or states
– Caused by faults
• Failure: Deviation of a circuit or system from its
specified behavior
– Fails to do what it should do
– Caused by an error

Fault
Error
Failure

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• An example: a car with a flat tyre

– Fault : pin puncture in the tyre
– Error : Erroneous state of air pressure in the
tyre
– Failure : Car cannot be driven safely

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Manifestation of Faults
• Two types of faults:
– Permanent: Faults that change the functional
behavior of a system permanently.
• Incorrect connections in ICs, PCBs
• Incorrect IC masks
• Functional design errors
EASIER TO DETECT
– Non-permanent: They occur at random times,
and affect the system’s functional behavior for
finite, but unknown periods of time.
DETECTION & DIAGNOSIS IS DIFFICULT
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• Two classes of non-permanent faults:

– Transient Faults:
• Caused by environmental conditions such as
cosmic rays, α particles, humidity, pressure,
vibration, etc.
• Example: Bit changes in RAMs caused by α-
radiation (called soft errors; no permanent
damage).

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– Intermittent Faults:
• Caused by non-environmental conditions,
such as loose connections, ageing
components, critical timing, etc.
• Behave like permanent failure for the
duration of the failure.
• Can be detected by continuously repeating
the test.

Fault Coverage
• A very commonly used metric:
– Fault coverage T is the measure of the
ability of a set of tests to detect a given
class of faults that may occur on the
device under test.

No. of detected faults

T =
No. of possible faults

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Defect Level
• Defect level (DL) is the fraction of shipped
parts that are defective.

DL = 1 – Y(1-T)

where Y is the yield, and T is the fault

coverage.

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Relating Defect Level to Fault Coverage

1
Y=.01
.9 DL = 1 - Y (1-T)
.8 Y = Yield
Y=.10
.7
Defect Level

.6
Y=.25

.5

.4
Y=.50

.3
Y=.75
.2
Y=.90
.1
Y=.99

0
0 10 20 30 40 50 60 70 80 90 100

Fault Coverage
Fault Coverage, T (%)(%)

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Why Testing is Difficult ?

• Test application time can grow exponentially
for exhaustive testing of circuits.
– For a combinational circuit with 50 inputs, we
need
250 = 1.1 x 1015 test patterns.
• Test generation of sequential circuits are even
more difficult.
– Lack of controllability and observability of flip-
flops.
• Functional testing may not be adequate for the
detection of physical faults.
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How To Do Test?
• Fault Modeling
– Identify target faults
– Limit the scope of test generation

• Test Generation
– Automatic or Manual

• Fault Simulation
– Assess completeness of tests

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• Testability Analysis
– Analyze a circuit for potential problem on test
generation

• Design For Testability

– Design a circuit for guaranteed test generation
– Introduce both area overhead and performance
degradation

Overheads of Testing
• Design for Testability (DFT)
– Chip area overhead
– Yield reduction
– Performance overhead
• Software processes of test
– Test generation
– Fault simulation
• Manufacturing test
– Automatic Test Equipment (ATE) cost
– Test center operational cost

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Basic Testing Principle

Input patterns Circuit Output response

Under
Test

Golden response
Comparator

Good / Bad

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Traditional Design Flow

• Conduct testing after design

Design for
Testability

Yes

Design Too large

Testability Testability
Specification Design or
Improvement?
too slow? Analysis
No
No
Yes
Done

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The Infamous Design/Test Wall

30 years of experience proves that

test after design does not work!

Oh no!
What does
Functionally correct! this chip do?!
We're done!

Design Engineering Test Engineering

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New Design Mission

• Design circuit to optimally satisfy or trade-off
their design constraints in terms of area,
performance and testability.

TESTABILITY

PERFORMANCE AREA

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New VLSI Design Flow

No

Design Functional Logic Yes

Structure Satisfied
Specification Behavior Synthesis

Test Plan Circuit ATPG

Testable Synthesis
Design Rules

Testability Placement/
Analysis Routing Tests

Mask

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Ideal Tests vrs. Real Tests

• Ideal Tests:
– Detect all defects produced in the
manufacturing process.
– Pass all functionally good devices.
– Problems:
• Very large numbers and varieties of
possible defects need to be tested.
• Difficult to generate tests for some real
defects. Defect-oriented testing is an open
problem.

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• Real Tests:
– Based on analyzable fault models, which may
not map on real defects.
– Incomplete coverage of modeled faults due to
high complexity.
– Some good chips are rejected.
• The fraction (or percentage) of such chips is
called the yield loss.
– Some bad chips pass tests.
• The fraction (or percentage) of bad chips among
all passing chips is called the defect level.

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Testing as Filter Process

0.7 0.95 0.68

Good chips Mostly

prob(pass test) = high
good
prob(good) = y
chips

Fabricated
chips
0.05
0.05
Defective chips Mostly
bad
prob(bad) = 1- y prob(fail test) = high
chips
0.3 0.95 0.32

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