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Figure 2 shows the modified protective network for Mode + Terminal − Terminal
CD4049/4050 buffer. The input diode to VDD is deleted 1 Input VSS
here so that level shifting can be achieved where inputs are 2 VDD Input
higher than VDD.
3 Input Associated Output
4 Associated Output Input
Pre- and post-zap performance is monitored on the input
leakage parameter at VDD = 18V. It has been found that all
Fairchild’s CMOS devices of CD4000 and 74C families can
withstand 400V zap testing with above mentioned condi-
tions and still be under the pre- and post-zap input leakage
conditions of ±10 nA.
www.fairchildsemi.com 2
AN-248 Electrostatic Discharge Prevention-Input Protection Circuits and Handling Guide for CMOS Devices
Handling Guide for CMOS Devices (Continued)
not be solved merely by using anti-static rails or containers Footnotes
as they do not necessarily shield devices from external
static fields, such as those generated by a charged person. 1. T.S. Speakman, “A Model for the Failure of Bipolar Sili-
Commercially available static shielding bags, such as 3M con Integrated Circuits Subjected to ESD,” 12th Annual
Proc. of Reliability Physics, 1974.
company’s low resistivity (≤104Ω/sq.) metallic coated poly-
ester bags, will help prevent damages due to external stray 2. M. Lenzlinger, “Gate Protection of MIS Devices,” IEEE
fields. These bags work on the well-known Faraday cage Transac. on Electron Devices, ED-18, No. 4, April
principle. Other commercially available materials are 1971.
Legge company’s conductive wrist straps, conductive floor 3. J.R. Huntsman, D.M. Yenni, G. Mueller, “Fundamental
coating, and various other grounding straps which help Requirements for Static Protective Containers.” Pre-
prevent against the electrostatic damage by providing con- sented at 1980 Nepcon/West Conference, Application
ductive paths for the generated charge and equipotential Note—3M Static Control Systems.
surfaces.
It can be concluded that electrostatic discharge prevention
is achievable with simple awareness and careful handling
of CMOS devices. This will mean wide and useful applica-
tions of CMOS in system designs.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support
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instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the www.fairchildsemi.com
user.
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