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  • Assignment 6

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    Arslan Arshad
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    The document provides instructions for Assignment 6 for an EE432 VLSI Design course. Students are asked to: 1. Draw the layout for CMOS inverters, NAND2, and NOR2 gates using Microwind and the 0.25u technology file. Apply DRC checks to remove violations. 2. Generate 3D views and cross-sectional views of the gates and include them in the assignment. 3. Apply power (VDD, VSS) and input signals to observe the output for each gate. The assignment is due on May 4th 2018 and must be original work submitted to the TA, with no late submissions accepted.

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    The document provides instructions for Assignment 6 for an EE432 VLSI Design course. Students are asked to: 1. Draw the layout for CMOS inverters, NAND2, and NOR2 gates using Microwind and the 0.25u technology file. Apply DRC checks to remove violations. 2. Generate 3D views and cross-sectional views of the gates and include them in the assignment. 3. Apply power (VDD, VSS) and input signals to observe the output for each gate. The assignment is due on May 4th 2018 and must be original work submitted to the TA, with no late submissions accepted.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    17 views2 pages

    Assignment 6

    Uploaded by

    Arslan Arshad
    The document provides instructions for Assignment 6 for an EE432 VLSI Design course. Students are asked to: 1. Draw the layout for CMOS inverters, NAND2, and NOR2 gates using Microwind and the 0.25u technology file. Apply DRC checks to remove violations. 2. Generate 3D views and cross-sectional views of the gates and include them in the assignment. 3. Apply power (VDD, VSS) and input signals to observe the output for each gate. The assignment is due on May 4th 2018 and must be original work submitted to the TA, with no late submissions accepted.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
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    Department of Electrical Engineering Information Technology University

    EE432 VLSI Design


    _____________________________________________________________________________________
    Assignment no. 6
    1. Draw the layout for CMOS inverter, NAND2 and NOR2 gates (n-well process) in Microwind.
    a. Click on File -> Select Foundry and select cmos025.rul., this sets your layout editor
    designs in 0.25u technology.
    b. Apply Design Rule Check (DRC) after completing layouts and remove any DR
    violation.
    c. Replace Lab 9 with your name and student ID in the layout.
    d. Generate the 3D view of gates and add their pictures in the assignment.
    e. Generate the cross sections (using process view button) across plane shown by all black
    dash lines and add their pictures in the assignment.

    f. Apply VDD and VSS to pFETs and nFETs, apply pulse signal to gates and observe output
    through visible output node for all three gates.

    1
    Department of Electrical Engineering Information Technology University
    EE432 VLSI Design
    _____________________________________________________________________________________
    Note: Submit Assignment to Mr. Saqib Iqbal.

    No late submission will be entertained.

    Copied assignments and those from which copied will be assigned zero marks.

    You can discuss with anyone but everyone need to submit assignment to TA with figures
    generated from software.

    Due Date: 4th May, 2018 at the end of class.

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