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Published in IET Power Electronics
Received on 1st October 2012
Revised on 31st January 2013
Accepted on 16th February 2013
doi: 10.1049/iet-pel.2012.0545
ISSN 1755-4535
Abstract: This study describes the design and performance evaluation of a bidirectional isolated dc–dc converter with an
extended dual-phase-shift (EDPS) scheme. The operation principle and equivalent circuits with consideration of the deadband
are presented. The deadband effect with EDPS is different from the conventional phase-shift (CPS) scheme, and the
corresponding compensation coefficient is determined. Different operation modes are identified with respect to phase-shift
angles of EDPS and load conditions. The safe operational area is also analysed with the comparison of different operation
modes. The output voltage and output power characteristics with open-loop or closed-loop operation are discussed. The
average theoretical 48.5% reduction in the output voltage ripple using EDPS has been achieved. The average reduction in
inductor peak and rms with EDPS are statistically calculated as 37.8 and 26.8%. The measured efficiency has improved from
68.1% using CPS to 81.9% using EDPS for low-power application.
Fig. 1 Topology and typical waveforms of a dual-active-bridge dc–dc converter with CPS scheme
a Topology
b Typical waveforms
EDPS and only the output voltage of this side is of Thus, the ‘minor parameters’ like deadband effect and key
three-level. Compared with DPS, EDPS can further reduce design issues should be considered in the design and
the reactive circulating current and the current stress performance evaluation of EDPS controlled converter. In
especially for middle- and high-power applications. order to avoid the limitation discussed above, each
Besides, EDPS shows the feature of easy-to-implement. operating stage with its equivalent circuit using EDPS
However, the prior studies with the advanced modulation scheme is investigated with the insertion of the deadband.
strategies show significant limitations that can be The comprehensive design and performance evaluation with
summarised as below: EDPS are provided, which include long-timescale
steady-state operations, such as output voltage and power
with open-loop or closed-loop control, SOA, efficiency, and
† The prior studies are originated from the ideal power flow short-timescale phenomenon such as the deadband effect.
model and neglect the effect of ‘minor parameters’ like The corresponding performance with CPS is adopted as
deadband, considering the complexity of the actual power benchmark. With the optimal operating mode of EDPS, the
flow model. The prior research on short-timescale transients average 48.5% reduction in the output voltage ripples has
is just focused on CPS. been achieved. The average reduction in peak and rms with
† Key design issues such as voltage ripple and safe EDPS are statistically calculated as 37.8 and 26.8%. The
operational area (SOA) with advanced modulation strategies measured efficiency has improved from 68.1% using CPS
are usually neglected. to 81.9% using EDPS for low-power application.
Fig. 4 Complete operating modes of EDPS considering the distribution of reactive current for boost operation
a EDPS_I
b EDPS_II
c EDPS_III
stage, where main energy exchanging components are Stage 6 [t5–t6]: At t5, Q14 is turned on under zero-voltage
highlighted to illustrate the power flow process in each stage. condition. The current iL increases linearly and the
corresponding slope is
Stage 1 [t0–t1]: Q11 is turned off and the antiparallel diode
DQ11 is conducting to freewheel the current iL because iL is
diL /dt = VS1 − VS2 /N /Ls (3)
in the negative direction. The primary current is
freewheeling through DQ11 and Q13. RQ13 represents the
on-resistance of Q13. The secondary current flows through Stage 7 [t6–t7]: t6 corresponds to the zero crossing instant of
Q22 and Q23. The primary voltage vT1shows the diode the inductor current iL. During this interval, the input voltage
conduction voltage and the secondary voltage vT2 is negative. vS1 provides the power to the load and compensates the power
Stage 2 [t1–t2]: At t1, Q11 will turn on and the primary loss in inductor L and output capacitor CS2.
current will flow through Q11/Q13 because the voltage drop Stage 8 [t7–t8]: Q11 is turned off at t7. The capacitor in parallel
across MOSFET when it conducts is lower than the with Q11 is charged linearly and the capacitor in parallel with
conduction voltage drop of diode. The current will Q12 is discharged until its voltage drop to the forward
commutate from DQ11 to Q11. Thus, Q11 is zero-voltage conduction voltage of DQ12. Then, the secondary current
soft-switching on at this condition. The secondary current will freewheel through Q14/DQ12. At t8, Q12 is turned on in
flows through Q22 and Q23. The primary voltage vT1 is zero-voltage condition. VT1 is zero and VT2 is positive. The
zero and the secondary voltage vT2 is negative. The corresponding equivalent circuits in this stage are shown in
inductor releases the energy and the current changing slope Figs. 3i and j. The current iL reduces linearly and the slope is
of iL is
diL /dt = −VS2 / NLs (4)
diL /dt = VS2 / NLs (1)
A similar operation can be analysed for the rest of the stages.
For the backward mode, the main difference is that VT1 is
Stage 3 [t2–t3]: Q22 and Q23 are turned off at t2. Their lagging to VT2 and its typical waveforms are shown in
antiparallel diodes DQ22 and DQ23 are conducting to Fig. 2b. The complete operations for backward mode in a
freewheel the current iL because iL is in the negative switching cycle can also be divided into 17 stages and the
direction. The primary current flows through Q11/Q13. The power flow analysis is similar to that of the forward mode.
inductor releases the stored energy and the voltage vCS2 is
still increasing. The process and the corresponding
equivalent circuit of this stage are shown in Fig. 3c. 3 Steady-state characteristics with EDPS
Stage 4 [t3–t4]: At t3, Q21 and Q24 are turned on and the
secondary current commutates from DQ22/DQ23 to Q21/Q24. 3.1 Operating modes with EDPS
The capacitor CS2 discharges and provides energy. This
energy will transfer from the secondary side to the primary Different from CPS, there are possible multiple zero crossing
side in this stage. The corresponding slope of iL is given by points of iL in the half switching cycle with EDPS. Figs. 4a–c
diL /dt = −VS2 / NLs (2)
Table 1 Expressions of current at the switching angles with
EDPS (pu)
Stage 5 [t4–t5]: Q13 is turned off at t4. The capacitor in Modes iL(0) iL(δ1) iL(δ2) iL(π)
parallel with Q13 is charged linearly and the capacitor in
parallel with Q14 is discharged until its voltage drop to the d≥1 −dD1 − −dD1 − dD2 −d + dD2 + dD1 +
forward conduction voltage of DQ14. Then, the primary dD2 + d − 1 + d − 1 + 2D2 dD1 − 2D1 + dD2 − d +
current will flow through Q11/DQ14. The transformer 1 1
d<1 D1 + D2 + d D1 + D2 + d − −D1 − D2 − −D1 −
primary voltage includes the input voltage vS1 and the −1 1 − 2dD1 d + 2dD2 + 1 D2 − d + 1
conduction voltage of DQ14.
where fs is the switching frequency. The variables VS1 , fs and Thus, the delivered power from VS1 is expressed as
Ls affect only the magnitude of Po. Table 1 shows that the
phase-shift pair (D1, D2) determines solely the operating P1 = VS1 IS1
modes and the amount of output power.
Under heavy load conditions, iL increases from an initial = VS1 VS2 D2 − D1 1 − D1 − D2 / 4NLs fs (8)
negative value in a switching cycle. As shown in Fig. 4,
there are two operating modes, EDPS_I and EDPS_II, The output power can be expressed according to the output
which are corresponding to the heavy load conditions for voltage and load resistance as
boost operation. Under light load conditions, iL increases
from a positive value at the beginning of the cycle, and
drops to a negative value at the end of the half switching Po = VS22 /RL (9)
Fig. 5 Experimental waveform of vT1, vT2, and iL for different steady-state operation modes under the heavy-load conditions
a EDPS_I for d > 1
b EDPS_II for d > 1
c EDPS_III for d = 1
d EDPS_III for d < 1
Fig. 7 Effect of the deadband using EDPS against output power Po when ‘D1 = 0.02’
a Comparison of the practical phase-shift angle using different deadband parameters against Po
b Relationship of the compensation coefficient k against Po
According to the typical inductor current waveform shown in different output power levels. The main parameters are
Fig. 4, the mathematical expression of the inductor rms listed as: VS1 = 20 V, d = 1.5, N = 6, Ls = 1 μH, fs = 50 kHz.
current (per unit) then can be derived as (see (18)) The dash lines show the boundaries of different operating
The SOA design is essential to guarantee the safe operation modes using EDPS. As shown in Fig. 8b, the operating
of power devices such as MOSFETs. One of the major issues modes are arranged as ‘EDPS_III’, ‘EDPS_II’ and
considering the SOA design is the determination of the range ‘EDPS_I’ from the left to right. The distinctive features for
of key parameters such as the leakage inductance Ls and these operating modes of EDPS are shown in Fig. 8b.
switching frequency fs. Fig. 8a shows the calculated results However, EDPS_II always shows the lowest rms current for
of the inductor peak current iLpeak with EDPS as a function all output power levels.
of Ls and fs through simulation. The range of fs is initially The relationship of the minimum Irms with EDPS against
set as 50–500 kHz considering the application the inductance Ls under different switching frequency fs are
characteristics of MOSFETs. Fig. 8a shows that iLpeak drops derived and shown in Fig. 8c for ‘Po = 200 W’. The rms
dramatically with the increase of fs. The inductance Ls also current limit of MOSFET is set at 30 A, shown as the
determines the inductor peak current iLpeak. With a fixed green solid line in Fig. 8c. The derived inductance range
value of fs, a large inductance of Ls will reduce iLpeak, should be between 0.7 and 3.6 μH if the MOSFETs are
however, large Ls will limit the maximum output power of operated at 50 kHz. If Ls < 0.7 μH, the inductor rms current
EDPS controlled converter according to (13). will exceed the threshold of 30 A. If Ls > 3.6 μH, the 200
The rms current of the transformer primary side Irms could W output power will not be achievable. As shown in
be calculated according to (18). Owing to one more Fig. 8c, the inductance ranges with fs = 100 kHz and fs =
phase-shift variable using EDPS, Irms can be tuned to 200 kHz are [0.3 μH, 1.8 μH] and [0.2 μH, 0.9 μH],
achieve the minimum. Fig. 8b shows the optimised Irms respectively, which are significantly narrower than that
using EDPS against the phase-shift variable D2 for three with fs = 50 kHz.
2 2
Irms = iL (0) bEDPS II 1 + 1 − bEDPS II 3 + iL d1 bEDPS II 2 − bEDPS II 1 + iL d2 bEDPS II 3 − bEDPS II 2 /3
2
3 3 3
= 2(d − 1) dD1 + dD2 − d + 1 − d −d + dD2 + dD1 − 2D2 + 1 −d −d + dD2 + dD1 − 2D1 + 1 /(6(d − 1))
(18)
Fig. 10 Comparison of the inductor peak current and the rms current of DAB converter using CPS and EDPS_II against the output power
a Experimental waveforms with CPS
b Experimental waveforms with EDPS_II
c Comparison of the calculated inductor peak current
d Comparison of the calculated inductor rms current
current of DAB converter using CPS, DPS and EDPS_II
DVS2 DT iL d1
DVS2 % = = − Io (23) with respect to the output power Po. Both the peak and the
V S2 2VS2 CS2 N rms current are dramatically reduced with the proposed
EDPS for the whole output power range. The average
Substitute (10), (11), (21) and the current expression in reduction in peak and rms are statistically calculated as 37.8
Table 1 to (23), the expression for DVS2 %; can be obtained and 26.8%. The measured efficiency is improved from
as (see (24)) 68.1% using CPS to 81.9% using EDPS_II for ‘Po = 25 W’.
As shown in (24), the output voltage ripple is a function of Figs. 10c and d also show the comparison of the inductor
CS2, RL, d, N and the phase-shift pair (D1, D2). For the given peak and rms current using DPS and EDPS. This
parameters of CS2, RL, d, N, the voltage ripple can be comparison shows that EDPS can further reduce the
regulated through phase-shift pair, which adds one more reactive circulating current and the current stress especially
tuning parameter compared with CPS. Figs. 9c and d show for middle and high power range compared with DPS.
the experimental waveforms of iB2 using CPS and EDPS_II.
The measured ripple rms value of iB2 is smaller than that
of CPS. The current ripple of iB2 with EDPS_II is
6 Conclusion
discontinuous in the switching period. However, the current This paper presents the operation, design and performance
ripple of iB2 with CPS is always fluctuating and continuous. characteristics of an isolated bidirectional DAB dc–dc
Fig. 9e shows the comparison of the output voltage ripple converter with the proposed EDPS scheme. The
ratio using CPS and EDPS with respect to the output power comprehensive analysis is provided, which includes the
Po. Significant reduction of voltage ripple has been determination of key parameter such as the leakage
illustrated and the average reduction is statistically inductance Ls and switching frequency fs, detailed operating
calculated as 48.5%. The minimised output voltage ripple stages analysis with their equivalent circuits, long-timescale
also reflects the significant reduction in reactive circulating steady-state operations such as output voltage and power
current by using EDPS. with open-loop or closed-loop control, and short-timescale
phenomenon such as the deadband effect. Compared with
5.2 Efficiency CPS scheme, the EDPS can improve both the static and
dynamic performance of the DAB converter because of the
Figs. 10a and b show the experimental waveforms of vT1, vT2 flexibility of two degrees of freedom tuning. With the
and iL using CPS and EDPS_II. Figs. 10c and d show the optimal operating mode of EDPS, the average 48.5%
comparison of the calculated peak current and the rms reduction in the output voltage ripples has been achieved.
2
N 2 Ls D21 − D22 + dD1 + dD2 − D1 − D2 + 1 − d
DVS2 % = (24)
2CS2 RL D2 − D1 1 − D1 − D2 RL D21 − RL D22 − RL D1 + RL D2 − 4Ls fs N 2