Physics Laboratory Report: Experiment#1

Physics Laboratory Report
Laboratory ( Digital Logic Design )

PHYS-402
Experiment#1
Design and study of logic circuits
Aspects to be covered are:
1) Design and study of the NAND gate

2) Design and study of AND gate
3) Design and study of OR gate
4) Design and study of NOT gate
5) Design and study of XOR gate
5) Convert NAND gate to OR, AND and NOT gate
Experiment Conduct by: M . Salman, BS-M-P-15-49
Partner’s Full Name: Shahzada Muzamil & Osama Khan

Laboratory Section: Morning, Group#1
Supervisor: Dr. Nauman Usmain
Digital Electronics Laboratory, Department of Physics,

Bahauddin Zakariya University, Multan
EXPERIMENT
Study of LOGIC Gates
Objectives:
a. To construct the circuit to verify the NAND gate build on IC
b. To convert NAND gate to AND gate
c. To convert NAND gate to OR gate
d. To convert NAND gate to NOT gate
e. To construct XOR gate using NAND gate
HARDWARE SOLID STATE COMPONENT REQUIRED

a. Power Supply : DC Power Supply
b. Equipment : Digital Breadboard
c. Resistor : 0Ω
d. Capacitor : 0µF
e. Semiconductor : IC 7400
f. Miscellaneous : Breadboard, Connecting Wires
Lab Sessions
Session-1
Verify NAND gate
Session-2
Verify conversion of NAND gate to AND gate
Session-3
Verify conversion of NAND gate to OR gate
Session-4
Verify conversion of NAND gate to NOT gate
Session-5
Verify construction of XOR gate
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LOGIC Gates
As well as a standard Boolean Expression, the input and output information of any ”Logic
Gate” or circuit can be plotted into a standard table to give a visual representation of the
switching function of the system.
The table used to represent the Boolean expression of a logic gate function is commonly
called a Truth Table. A logic gate truth table shows each possible input combination to the
gate or circuit with the resultant output depending upon the combination of these input(s).
For example, consider a single 2-input logic circuit with input variables labeled as A and B.
There are “four” possible input combinations or 22 of “OFF” and “ON” for the two inputs.
However, when dealing with Boolean expressions and especially logic gate truth tables, we
do not general use “ON” or “OFF” but instead give them bit values which represent a logic
level “1” or a logic level “0” respectively.
Then the four possible combinations of A and B for a 2-input logic gate is given as:
 Input Combination 1. – “OFF” – “OFF” or ( 0, 0 )
 Input Combination 2. – “OFF” – “ON” or ( 0, 1 )
 Input Combination 3. – “ON” – “OFF” or ( 1, 0 )
 Input Combination 4. – “ON” – “ON” or ( 1, 1 )
Therefore, a 3-input logic circuit would have 8 possible input combinations or 2 3 and a 4-
input logic circuit would have 16 or 24, and so on as the number of inputs increases. Then a
logic circuit with “n” number of inputs would have 2n possible input combinations of both
“OFF” and “ON”.
So in order to keep things simple to understand, in this tutorial we will only deal with
standard 2-input type logic gates, but the principals are still the same for gates with more
than two inputs.
Then the Truth tables for a 2-input AND Gate, a 2-input OR Gate and a single input NOT
Gate are given as:
Digital Electronics Laboratory, Department of Physics, Bahauddin Zakariya University, Multan

Page | 6
2-Input AND Gate

For a 2-input AND gate, the output Q is true if BOTH input A “AND” input B are both true,
giving the Boolean Expression of: ( Q = A and B ).
Symbol Truth Table
A B Q
0 0 0
0 1 0
1 0 0
1 1 1
Boolean Expression Q = A.B Read as A AND B gives Q
Note that the Boolean Expression for a two input AND gate can be written as: A.B or just
simply AB without the decimal point.
Conversion of NAND gate to AND gate

Page | 7
Circuit Diagram of Conversion of NAND gate to AND Gate Arranged on

Breadboard

Page | 8
2-Input OR (Inclusive OR) Gate

For a 2-input OR gate, the output Q is true if EITHER input A “OR” input B is true, giving
the Boolean Expression of: ( Q = A or B ).
Symbol Truth Table
A B Q
0 0 0
0 1 1
1 0 1
1 1 1
Boolean Expression Q = A+B Read as A OR B gives Q
Conversion of NAND gate to OR gate

Page | 9
Circuit Diagram of Conversion of NAND gate to OR Gate Arranged on

Breadboard

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NOT Gate (Inverter)

For a single input NOT gate, the output Q is ONLY true when the input is “NOT” true, the
output is the inverse or complement of the input giving the Boolean Expression of: ( Q =
NOT A ).
Symbol Truth Table
A Q
0 1
1 0
Boolean Expression Q = NOT A or A Read as inversion of A gives Q
The NAND and the NOR Gates are a combination of the AND and OR Gates respectively
with that of a NOT Gate (inverter).
Conversion of NAND gate to NOT Gate

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Circuit Diagram of Conversion of NAND gate to NOT Gate Arranged on

Breadboard

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2-Input NAND (Not AND) Gate

For a 2-input NAND gate, the output Q is true if BOTH input A and input B are NOT true,
giving the Boolean Expression of: ( Q = not(A and B) ).
Symbol Truth Table
A B Q
0 0 1
0 1 1
1 0 1
1 1 0
Boolean Expression Q = A .B Read as A AND B gives NOT-Q

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Circuit Diagram of NAND Gate Arranged on Breadboard

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2-Input EX-OR (Exclusive OR) Gate

For a 2-input Ex-OR gate, the output Q is true if EITHER input A or if input B is true, but
NOT both giving the Boolean Expression of: ( Q = (A and NOT B) or (NOT A and B) ).
Symbol Truth Table
A B Q
0 0 0
0 1 1
1 0 1
1 1 0
Boolean Expression Q = A ⊕ B
XOR Gate

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Circuit Diagram of XOR Gate Arranged on Breadboard

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Summary of 2-input Logic Gates

The following Truth Table compares the logical functions of the 2-input logic gates above.
Inputs Truth Table Outputs For Each Gate
A B AND NAND OR NOR EX-OR EX-NOR
0 0 0 1 0 1 0 1
0 1 0 1 1 0 1 0
1 0 0 1 1 0 1 0
1 1 1 0 1 0 0 1
The following table gives a list of the common logic functions and their equivalent Boolean
notation.
Logic Function Boolean Notation
AND A.B
OR A+B

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NOT A
NAND A .B
NOR A+B
EX-OR (A..B) + (A.B) or A ⊕ B
EX-NOR (A.B) + (A.B) or A ⊕ B
2-input logic gate truth tables are given here as examples of the operation of each logic
function, but there are many more logic gates with 3, 4 even 8 individual inputs. The multiple
input gates are no different to the simple 2-input gates above, So a 4-input AND gate would
still require ALL 4-inputs to be present to produce the required output at Qand its larger truth
table would reflect that.

PHYS-402
Experiment#2
Design and study of subtractor circuits
1) Design of subtractor circuit

2) Design half subtractor circuit
3) Verify half subtractor truth table
4) Design full subtractor circuit
5) Verify full subtractor truth table
5) Verify all theoretical and experimental results


EXPERIMENT
Study of SUBTRACTOR Circuit
Objectives:
a. To construct the circuit to verify subtractor circuits by NAND gate build on IC
b. To construct half subtractor using NAND gate
c. To construct full subtractor using NAND gate
d. To have clear mathematical explanation of subtractor circuits
e. To verify the truth table of subtractor circuit

c. Resistor : 0Ω
d. Capacitor : 0µF
Lab Sessions
Session-1
Verify half subtractor
Session-2
Verify full subtractor
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P a g e | 23
Half Subtractor
Definition: The Half Subtractor is a digital circuit which processes the subtraction of two 1-
bit numbers. In this, the two numbers involved are termed as subtrahendand minuend. In
the subtraction procedure, the subtrahend will be subtracted from minuend. The circuit of
Half subtractor consists of two inputs and two outputs.
The inputs of the half subtractor circuit will be subtrahend and minuend. On the other hand,
the output will be the difference and the borrow. The word “HALF”before the subtractor
signifies that it deals with only two 1-bit numbers, it has nothing to do with the borrow from
the previous stage. The logic symbol of half subtractor is represented in the diagram below.
Procedure of Subtraction
We are very familiar with the addition procedure; it is quite easy to add two binary numbers
rather than subtracting them. To understand the internal operation of the half subtractor, we
must first understand the subtraction rules of binary numbers.
The above image clearly elaborates the subtraction rule of binary numbers. Let’s take an
example of subtraction of two multi-bit number with the help of above-defined rules.

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Circuit of Half Subtractor
The logic circuit of Half subtractor involves usage of logic gates. In order to design logic
circuit, we should understand two concepts. First is the difference operation of half subtractor
resembles operation of which logic circuit. Secondly, the borrow generated by half subtractor
will also be in accordance with the particular operation which will resemble operation of any
logic gate.
If we observe carefully, it is quite evident that the difference operation performed by half
subtractor is exactly similar to the operation of EX-OR gate. Thus, we can easily utilize the
EX-OR gate for generating difference bit. Similarly, the borrow generated by half subtractor
can be easily obtained by using the combination of NOT gate and AND gate.
Truth Table of Half Subtractor

The truth table is a key tool to understand the working of any digital circuit. The truth table is
nothing but the possible combination of inputs and their resultant output. In case of half
subtractor there are two inputs. Thus the number of possible combinations will be 4.
The resultant of all the 4 inputs will be described as outputs. The output of half subtractor is
described in two columns. One will signify the difference bit, and another will signify the
borrow bit. To derive the truth table, just use the EX-OR operation of two inputs for
generating difference and NOT followed by AND operation for generating the borrow bit.

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Equation of Half Subtractor
The equation of Half Subtractor can be easily written if we are familiar with the operation of
EX-OR gate. The difference equation will be written in terms of EX-OR of two inputs. And
the borrow equation can be determined by using the negation operation of the two terminals
followed by the AND operation of the two inputs obtained after negation.
Half Subtractor using NAND gates

The NAND gate is one of the universal gates. It is crucial to have an understanding of
universal gate. This is because a universal gate is something which can be used to design any
digital circuit. Similarly, NAND gate can also be used to design half subtractor.
The key point which is to be kept in mind while designing the circuit using universal gate is
that the architecture in which it is to be connected so that it performs the desired operation.
The total of 5 NAND gate are used for designing of Subtractor circuit.
Half Subtractor using NOR gates
The NOR gate is also one of the universal gates. The subtractor can be designed by using 5
NOR gates. The NOR gates are to be connected in such a manner that combination of some
of the NOR gates generate the difference bit while the combination of other NOR gate should
generate the borrow bit.
The below diagram illustrates the connection of NOR gates to form the Subtractor.

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Application of Subtractor
The general thinking which dominates is that subtraction is harder than the addition that is the
reason that subtractors are not much popular in comparison to half adders. This is because the
subtraction can also be done using addition by using the complement of binary numbers.
Thus, it would not be wrong to say that subtractors are not used extensively. But some of the
areas where it finds application is in arithmetic and logic units of processors.
It should be noted that so far we have discussed half subtractor which can be used for
subtraction of numbers in the least significant column. For subtraction of multi-bit numbers,
subtractor can be used only for the least significant bit. In such cases, we need full subtractor
or n-bit subtractor.

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Half Adder
Definition: Half Adder is the digital circuit which can generate the result of the addition
of two 1-bit numbers. It consists of two input terminal through which 1-bit numbers can be
given for processing. After this, the half adder generates the sum of the numbers and carry if
present.
It is very easy to guess the working of the adder just by its name. This is because the word
adder consists of keyword “ADD” which means to add any numbers. But what does this
keyword “HALF” signifies. You might have confronted this question while going through
digital electronics. Let’s discuss what does this mean.
The word “HALF” before the adder signifies that the addition performed by the adder will
generate the sum bit and carry bit, but this carry from one operation will not be passed for
addition to successive bits. Therefore, it is called half adder.
Although, the major significance of adder is that it can perform addition but apart from this it
is also used in processors of computer systems for address decoding. We will also discuss
other crucial application later in this article.
Half Adder Circuit

The circuit of half adder can be designed with the help of basic building blocks of digital
electronics realm i.e. logic gates. Half adder can also be designed with the help of universal
gates. We will discuss all the possible designing one by one in this article.
In the above circuit diagram, it is apparent that one AND gate is used along with EX-OR
gate. This is the simplest of all the other possible designs of half adder. The input numbers to

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be added is given to AND gate as well as EX-OR gate. The AND gate will generate the sum
bit of the addition performed and the EX-OR gate will generate the carry bit as output.
Half Adder Truth table
The truth table of any digital circuit is significant to understand its operations. The truth table
consists of all possible combination of input that can be given to the digital circuit and all the
resulting outputs.
Half Adder using NAND Gates

The half adder can also be designed with the help of NAND gates. NAND gate is considered
as a universal gate. A universal gate can be used for designing of any digital circuitry. It is
always simple and efficient to use the minimum number of gates in the designing process of
our circuit. The minimum number of NAND gates required to design half adder is 5.
The first NAND gate takes the inputs which are the two 1-bit numbers. The resultant NAND
operated inputs will be again given as input to 3- NAND gates along with the original input.
Out of these 3 NAND gates, 2-NAND gates will generate the output which will be given as
input to the NAND gate connected at the end. The gate connected at the end will generate the
sum bit. Out of the 3 considered NAND gates, the third NAND gate will generate the carry
bit. The NAND operation can be understood more clearly with the help of equation given
below. These equations are written in the form of operation performed by NAND gates.

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Half Adder using NOR Gates
The NOR gate is also a universal gate. Thus, it can also be used for designing of any digital
circuit. The Half adder can be designed using 5 NOR gates. This is the minimum number of
NOR gates to design half adder.
Firstly, three NOR gates are used in the designing and the output from two of these NOR
gates is given to fourth NOR gate. The output from second NOR gate is given to the gate
connected at the end. This will generate the sum bit of the addition of two 1-bit numbers.
The operation of the above circuit diagram can be understood more clearly with the help of
equation. The sum bit and carry bit can be written in terms of NOR operations performed by
the logic gates.
Half Adder using basic gates

The Half adder can also be constructed using basic gates such as NOT gate, AND gate and

P a g e | 30
OR gate. To understand how to interconnect them so that they constitute Half Adder we
should be acquainted with the resulting operation of sum bit and carry bit.
The resulting carry bit of the addition is nothing but the AND operation of both the inputs.
And the resultant sum bit is the EX-OR operation of the operands. To design such a circuit
which produce the desired result we need 3-AND gates, 2-NOT gates and 1-OR gate.
The NOT gate will negate one of the input and combine with another original input and
passes through NAND gates. It must be noted that we need two NOT gate because only one
input in negated form will be passed from one NOR gate. To generate the negation of another
input we need another NOT gate.
And therefore, the output from two NAND gates will be given as input to the OR gate which
will generate the Sum bit of the addition of two 1-bit numbers. And the third AND gate will
simply take the two inputs and generate the carry bit of the addition.
Application of Half Adder

Half Adder is used in the arithmetic logic unit of the processor of the computer system for
performing arithmetic operations of input. Besides, it is also used in calculators for the
addition of number, in address decoding in processors, calculation of table indices etc.

P a g e | 31

PHYS-402
Experiment#3
Design and study of adder circuits
1) Design of adder circuit

2) Design half adder circuit
3) Verify half adder truth table
4) Design full adder circuit
5) Verify full adder truth table
5) Verify all theoretical and experimental results



EXPERIMENT
Study of SUBTRACTOR Circuit
Objectives:
a. To construct the circuit to verify adder circuits by NAND gate build on IC
b. To construct half adder using NAND gate
c. To construct full adder using NAND gate
d. To have clear mathematical explanation of adder circuits
e. To verify the truth table of adder circuit

c. Resistor : 0Ω
d. Capacitor : 0µF
Lab Sessions
Session-1
Verify half adder
Session-2
Verify full adder
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Full Adder
Full adder is a digital circuit used to calculate the sum of three binary bits which is the main
difference between this and half adder. Full adders are complex and difficult to implement
when compared to half adders. Two of the three bits are same as before which are A, the
augend bit and B, the addend bit. The additional third bit is carry bit from the previous stage
and is called Carry – in generally represented by CIN. It calculates the sum of three bits along
with the carry. The output carry is called Carry – out and is represented by COUT.
The block diagram of a full adder with A, B and CIN as inputs and S, CoUT as outputs is
shown below
Schematic Representation of Full Adder
Full Adder Truth Table
The truth table for full adder is shown below.

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Based on the truth table, the Boolean functions for Sum (S) and Carry – out (COUT) can be
derived using K – Map.
For Sum S
The simplified equation for sum is S = A ̅ B ̅ Cin + A ̅ BC ̅ in + ABCin
For Carry – out COUT

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The simplified equation for COUT is COUT = AB + ACIN + BCIN
In order to implement a combinational circuit for Full Adder, it is clear from the equations
derived above, that we need 4 three input AND gates and 1 four input OR gate for Sum and 3
two input AND gates and I three input OR gate for Carry – out.
The logic circuit for full adder is shown below.
Full Adder Logic Diagram
Implementation of Full Adder using Half Adders
A full adder can be formed by logically connecting two half adders. The block diagram that
shows the implementation of a full adder using two half adders is shown below.
We know the equations for S and COUT from earlier calculations as

P a g e | 38
S = A ̅ B ̅ Cin + A ̅ BC ̅ in + ABCin
Cout = AB + ACin + BCin
We can rewrite the equation for sum as follows.
S = A ̅ B ̅ Cin + A ̅ BC ̅ in + ABCin
= Cin (A ̅ B ̅ + AB) + C ̅ in (A ̅ B + A B ̅ )
Therefore S = CIN XOR (A XOR B)
= Cin (A X-NOR B) + C ̅ in (A X-OR B)
= Cin XOR (A XOR B)
Cout is simplified as
COUT = A B + A CIN + B CIN.
COUT = AB + A CIN + B CIN (A + ̅A)
= ABCIN + AB + ACIN + ̅A B CIN
= AB (1 +CIN) + ACIN + ̅A B CIN
= A B + ACIN + ̅A B CIN
= AB + ACIN (B + ̅B ) + ¬ ̅A B CIN
= ABCIN + AB + A ̅B CIN + ̅A B CIN
= AB (CIN + 1) + A ̅B CIN + ̅A B CIN
= AB + A ̅B CIN + ̅A B CIN
̅ B + A ̅B )
= AB + CIN ( A
Therefore COUT = AB + CIN (A EX – OR B)

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Based on the above two equations, the full adder circuit can be implemented using two half
adders and an OR gate. The implementation of full adder using two half adders is show
below.
Implementation of Full Adder with 2 Half Adders

Full Adder using NAND Gates
As mentioned earlier, a NAND gate is one of the universal gates and can be used to
implement any logic design. The circuit of full adder using only NAND gates is shown
below.
Full Adder using NAND Gates

Full adder is a simple 1 – bit adder. If we want to perform n – bit addition, then n number of 1
– bit full adders should be used in the form of a cascade connection.

P a g e | 40
Digital Electronics Laboratory, Department of Physics, Bahauddin Zakariya University, Mutlan

Physics Laboratory Report: Experiment#1

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Physics Laboratory Report

Laboratory ( Digital Logic Design )

Design and study of logic circuits

Aspects to be covered are:

1) Design and study of the NAND gate

Experiment Conduct by: M . Salman, BS-M-P-15-49

Partner’s Full Name: Shahzada Muzamil & Osama Khan

Digital Electronics Laboratory, Department of Physics,

HARDWARE SOLID STATE COMPONENT REQUIRED

Digital Electronics Laboratory, Department of Physics, Bahauddin Zakariya University, Multan

2-Input AND Gate

Symbol Truth Table

Boolean Expression Q = A.B Read as A AND B gives Q

Conversion of NAND gate to AND gate

Digital Electronics Laboratory, Department of Physics, Bahauddin Zakariya University, Multan

Circuit Diagram of Conversion of NAND gate to AND Gate Arranged on

Digital Electronics Laboratory, Department of Physics, Bahauddin Zakariya University, Multan

2-Input OR (Inclusive OR) Gate

Symbol Truth Table

Boolean Expression Q = A+B Read as A OR B gives Q

Conversion of NAND gate to OR gate

Digital Electronics Laboratory, Department of Physics, Bahauddin Zakariya University, Multan

Circuit Diagram of Conversion of NAND gate to OR Gate Arranged on

Digital Electronics Laboratory, Department of Physics, Bahauddin Zakariya University, Multan

NOT Gate (Inverter)

Symbol Truth Table

Boolean Expression Q = NOT A or A Read as inversion of A gives Q

Conversion of NAND gate to NOT Gate

Digital Electronics Laboratory, Department of Physics, Bahauddin Zakariya University, Multan

Circuit Diagram of Conversion of NAND gate to NOT Gate Arranged on

Digital Electronics Laboratory, Department of Physics, Bahauddin Zakariya University, Multan

2-Input NAND (Not AND) Gate

Symbol Truth Table

Boolean Expression Q = A .B Read as A AND B gives NOT-Q

Digital Electronics Laboratory, Department of Physics, Bahauddin Zakariya University, Multan

Circuit Diagram of NAND Gate Arranged on Breadboard

Digital Electronics Laboratory, Department of Physics, Bahauddin Zakariya University, Multan

2-Input EX-OR (Exclusive OR) Gate

Symbol Truth Table

Digital Electronics Laboratory, Department of Physics, Bahauddin Zakariya University, Multan

Circuit Diagram of XOR Gate Arranged on Breadboard

Digital Electronics Laboratory, Department of Physics, Bahauddin Zakariya University, Multan

Summary of 2-input Logic Gates

Inputs Truth Table Outputs For Each Gate

A B AND NAND OR NOR EX-OR EX-NOR

Logic Function Boolean Notation

Digital Electronics Laboratory, Department of Physics, Bahauddin Zakariya University, Multan

EX-OR (A..B) + (A.B) or A ⊕ B

EX-NOR (A.B) + (A.B) or A ⊕ B

Digital Electronics Laboratory, Department of Physics, Bahauddin Zakariya University, Multan

Design and study of subtractor circuits

Aspects to be covered are:

1) Design of subtractor circuit

Experiment Conduct by: M . Salman, BS-M-P-15-49

Partner’s Full Name: Shahzada Muzamil & Osama Khan

Digital Electronics Laboratory, Department of Physics,

HARDWARE SOLID STATE COMPONENT REQUIRED

Digital Electronics Laboratory, Department of Physics, Bahauddin Zakariya University, Multan

Digital Electronics Laboratory, Department of Physics, Bahauddin Zakariya University, Multan

Circuit of Half Subtractor

Truth Table of Half Subtractor

Digital Electronics Laboratory, Department of Physics, Bahauddin Zakariya University, Multan

Equation of Half Subtractor