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INTRODUCTION
A ll of the basic components of the computer are tied together by communications paths
called buses. A computer bus is simply a parallel collection of conductors which carry
data and control signals from one unit to another. Any computer will have three major system
buses identified by the type of information which they carry. These are the address bus, the
data bus, and the control bus, as illustrated in Figure 1.
Figure 1:
System Buses
When the mP wishes to access a memory location or I/O element to perform a Read or Write
operation, it does so by placing the appropriate address code on its address pins (A0-AN) and
generating the proper control signals to perform the operation. Since the memory unit is nor-
mally composed of several memory chips (RAM and ROM), special decoding circuitry is re-
quired to select the proper IC and single out the proper memory location (or I/O device) that
the mP is trying to address.
One of the most important control signals in any mP based system is the system clock. This
signal provides the timing information around which all of the system’s activities take place.
Depending on the type of mP being used, the clock signals may be generated on the mP chip or
by special IC signal generators. Microprocessors with internal clock generators usually re-
quire that an external crystal, or RC network, be connected to its clock input pins.
Figure 2 depicts a distributed clock signal scheme. The clock generator chip (U1) produces a
5 MHz output signal when its F/C signal is high and an 8 MHz signal is derived from the 24
MHz oscillator (Y2) and the 5 MHz signal comes from the RC/crystal network ay X1-X2.
The chip also creates a 14.318 MHz output signal at the OSC output.
If flip-flops are cascaded, a binary counter is produced. Every succeeding flip-flop requires
two pulses from the previous f-f to produce a single output change. When you compare this
concept to a binary count table, as depicted in Figure 3, you discover that the elements of the
counter behave in exactly the same manner as the weighted positions of the count table.
There are a number of IC counters available on the market. Some of these, like the divied-
by-six counter in Figure 2, count strictly in binary, while others are modified to count in
BCD. To be used as a counter, the outputs of each f-f element are used. In contrast, to use the
counter as a frequency divider, only those outputs which provide the desired division factor
are used.
The control bus also carries the signals which enable selected memory or I/O elements for
Read and Write operations. These signals may range from a simple Read/Write line (R/W) to
a collection of signals such as Memory Read (MEMR), Memory Write (MEMW), I/O Read
(IOR) and I/O Write (IOW). These signals are used by the mP in conjunction with addresses
on the address bus to perform Read and Write operations at selected memory or I/O loca-
tions.
From the preceding discussions, it should be apparent that I/O devices are treated like mem-
ory locations in that they have addresses. In reality, each I/O device must have its own spe-
cific address. There are two methods by which the
computer can handle I/O addressing. In some computers,
the mP addresses I/O in the same manner as it does memory
locations. This is because the I/O devices are granted a por-
tion of the available address codes and the same control sig-
nals are used to Read and Write both I/O and memory
locations. This method of I/O addressing is referred to as
memory-mapped I/O. A typical memory map for a 64K
computer showing RAM, ROM and I/O address alloca-
tions is depicted in Figure 4.
SUPPORT DEVICES
Although the microprocessor is ultimately responsible for the operation of the system, a
great number of support devices are necessary to aid the mP in carrying out its various func-
tions. In addition to the basic digital logic gates (AND, OR, NAND, NOR and INVERTER gates)
depicted in Figure 5, the computer relies on a number of medium scale integration (MSI)
devices to perform many functions for the mP. The most basic of these MSI devices are
latches, registers, multiplexers, demultiplexers, and decoders.
Figure 5:
SSI Devices
Figure 6: Latch
Registers are simply multiple latches, like the one described in the previous section,
working together. An eight-bit register is shown in Figure 7. Registers can be found
inside intelligent IC’s, like microprocessors or smart controllers, or they can be dis-
crete IC’s used throughout the system. In smart IC’s, registers are used for temporary
storage of values inside of the device. A microprocessor will use the registers to hold
data values for the Arithmetic Logic Unit (ALU) and to hold address values that are
to be placed on the address bus. Data is placed on the D inputs in parallel and a com-
mon enable signal is used to latch the data to the Q outputs.
Multiplexers
Multiplexers (MUX’s) are devices which can accept digital logic levels or pulse train
signals on a number of different inputs and select ONE to be passed to a single output
line. Hence, the multiplexer is often referred to as a data selector. Which of the various
inputs is allowed to pass through to the output is determined by a binary code applied
to the multiplexer’s SELECT lines. This relationship is demonstrated in Figure 8.
The data present on Input-5 (I-5) passes through to the output because of the binary
coded 5 (101) on the select lines (S0 through S2). The designers of digital chips take
care to orient the relationship between the inputs and the select lines to the binary
number system. In other words, to select the logic level at any input for passage to the
output, simply apply its number (in binary code) to the Select lines.
Figure 7: Register
Demultiplexers
Demultiplexers (DEMUX’s) perform just the reverse function of the multiplexer.
Instead of selecting an input to be passed to an output, the DEMUX accepts a single
input and distributes the logic level, or digital pulse train, to a number of possible out-
puts, under the direction of the SELECT lines. This relationship is depicted in Figure
9, where a logic “1" at the input is passed to output O4, because of the binary 4 (1002)
at the SELECT lines. Notice that all other output pins are held low because they are
kept in their non-active state when they are not selected. Many commercially avail-
able demultiplexers use low-active output pins. With these devices, the Non-
Selected outputs will be held high and the Selected output will invert the logic level
present at the input. Therefore, when a low logic level is present at the input, the out-
put will produce a high logic level at the selected output, and visa-versa. Devices
with active low outputs are denoted on schematic diagrams by the presence of small
circles at their output pins.
Figure 9: Demultiplexer
Decoders
Decoders are digital devices which are very similar to
demultiplexers. However, instead of passing a logic
level from the input to a selected output, decoders use a
binary coded input to activate a single output, whose
number corresponds to the input code. This relation-
ship is shown in Figure 10, where a binary coded 6 is
applied to the input pins of the decoder and its number
6 output goes high. All other outputs are held low in
their non-active state. Like the demultiplexer, the de-
coder can also employ active-low outputs. With these
devices, all outputs are held high, except for the se-
lected output, which is low.
Figure 10: Decoder
Figure 11 shows a Decoder/Demultiplexer device being used for both applications. In part
(a) of the figure, all ENABLE pins are tied to enabling logic levels and the device is operating
as a decoder. In part (b) of the figure, the SELECT lines are used to select the desired output
and one of the ENABLE pins is used as the data input. The data is transmitted to the output by
using the data logic levels to alternately enable and disable the output. Thus, the input data is
actually recreated at the output by the enable/disable action of the ENABLE pin.
Figure 11:
Decoder/Demultiplexer