DIGITAL LOGIC TECHNOLOGY

BMT-264

Lab Instructor:

Engr. Muhammad Shan Saleem

Lab No. ____

Name: ____________________

Roll Number: ______________

Department of Bio-Medical Engineering & Technology

University of Engineering & Technology, Taxila

 LAB-03

EXPERIMENT No. 03
IMPLEMENTATION OF HALF ADDER AND FULL ADDER
PRE-LAB TASK

Objectives

• To build Half Adder circuit using gates.

• To obtain simplified expression of Full Adder.
• To build Full Adder circuit the simplified expression.

Introduction

All digital computers execute a variety of information-processing jobs. Among these basic tasks
are the various arithmetic operations. The most basic arithmetic operation is the addition of two
binary digits. The circuit that implements this binary addition is called H-alf Adder. The next
stage to this addition is the addition of three binary numbers. The circuitry for this addition is
called Full Adder.

Theory

Half Adder

Half Adder is a type of combinational logic circuit that produces the sum of two binary digits
(each of 1-bit length). This circuit has two inputs, say x and y, and two outputs i.e. sum and carry
abbreviated as SHA & CHA respectively. First, we will construct Truth Table of Half Adder as:

Inputs Outputs

X Y SHA = x΄y+xy΄ CHA = xy

0 0
0 1
1 0
1 1
Boolean function for the above-mentioned Truth Table is:
0 0
1 0
1 0
0 1

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 LAB-03

𝑆𝐻𝐴 = 𝑥 ′ 𝑦 + 𝑥𝑦 ′ = 𝑥 ⊕ 𝑦

𝐶𝐻𝐴 = 𝑥𝑦

Above mentioned Boolean expressions are implemented by logic gates as:

x y

SHA= x + y
(To LED)

CHA=x y
(To LED)

Full Adder

Full Adder is combination logic circuit that carry out the sum of three binary numbers, each of
1-bit length. Two of the binary input variables are x and y represent the two significant bits to be
added the third input z, represents the carry from previous lower significant position. Outputs of
Full Adder are Sum and Carry represented as S FA and CFA respectively. Now we will draw the
Truth Table of Full Adder.

Inputs Outputs
x Y z SFA CFA
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
First, we write Boolean expression for Sum of Full Adder.

𝑆𝐹𝐴 = 𝑥 ′ 𝑦 ′ 𝑧 + 𝑥 ′ 𝑦𝑧 ′ + 𝑥𝑦 ′ 𝑧 ′ + 𝑥𝑦𝑧

The above expression can be simplified using Boolean Postulates & theorems/k-map, so we get

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𝑆𝐹𝐴 = (𝑥 ′ 𝑦 + 𝑥𝑦 ′ ). 𝑧 + (𝑥 ′ 𝑦 + 𝑥𝑦 ′ ). 𝑧

𝑆𝐹𝐴 = (𝑥 ⊕ 𝑦) ⊕ 𝑧

Now we write Boolean expression for Carry of Full Adder.

𝐶𝐹𝐴 = 𝑥 ′ 𝑦𝑧 + 𝑥𝑦 ′ 𝑧 + 𝑥𝑦𝑧 ′ + 𝑥𝑦𝑧

Above expression is simplified as:

𝐶𝐹𝐴 = (𝑥 ′ 𝑦 + 𝑥𝑦 ′ ). 𝑧 + 𝑥𝑦

𝐶𝐹𝐴 = (𝑥 ⊕ 𝑦). 𝑧 + 𝑥𝑦

We implement simplified Boolean expressions of SFA & CFA as:

x y z

HA1 HA2

SFA = (x + y) + z
To LED

CFA = (x + y) z + xy
To LED

LAB SESSION

Equipment and Materials

➢ NI ELVIS II Workstation
➢ 7408 IC
➢ 7432 IC
➢ 7486 IC

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 LAB-03

Experimental Procedure

• Layout the circuit of Half Adder on the bread board.

• Apply VCC = +5V and Gnd to all ICs.
• Power on the NI ELVIS II Workstation trainer.
• Apply input through the logic switches available on the trainer and verify the truth table.
• Now layout the circuit of Full Adder on the bread board and verify the truth table.

Questions:

1. Can we implement the expressions of SFA and CFA using Basic Gates only?
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2. From the expression of SHA and CHA count the number of gates required to execute these
expressions using basic gates only.
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3. From the expression of SFA and CFA count the number of gates required to execute these
expressions using basic gates only.
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4. From the result of Question 3, give the no. of ICs required.
# of OR Gate ICs: _________________
# of AND Gate ICs: _________________
# of NOT Gate ICs: _________________

LAB REPORT

Discussion of Results

1. List the applications in which Full Adder is used.

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 LAB-03

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2. Draw the circuit of Full Adder using Basic Gates only.

Conclusion / Summary:

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