SECTION 6.

1: IMMEDIATE AND DIRECT ADDRESSING MODES

Immediate addressing mode

In this addressing mode, the operand is a literal constant. In immediate

addressing mode, as the name implies, the operand comes immediately after the

opcode when the instruction is assembled. Notice that immediate data is called a

literal in the PIC. This addressing mode can be used to load information into

WREG and selected registers, but not to any file register. The immediate address-ing mode is also used
for arithmetic and logic instructions. Examine the following

examples.

MOVLW Ox25 ;load 25H into WREG

SUBLW D1

621

;subtract WREG from 62

ANDLW B'01000000' ;AND WREG with 40H

We can use the EQU directive to access immediate data as shown below.

COUNT EQU Ox30

MOVLW COUNT ;WREG = 30h

Notice that we can also use immediate addressing mode to perform arithmetic and

logic operations on WREG only. For example, "ADDLW Ox2 5" adds value 25 to WREG

Direct addressing mode

As mentioned in Chapter 2, the 256-byte access bank file register is split

into two sections: The lower addresses, 00 to 7FH, are assigned to the general pur-pose registers, and
the upper addresses, F80-FFFH, to the SFR. The access bank

is the default bank when the PIC 18 is powered up. It is the minimum bank that all

PIC18 processors have. The MOVFF instruction also plays a role in choosing the
access bank. We will discuss that issue in Section 6.5 when we discuss bank

switching.

The entire data RAM file register can be accessed using either direct or

register indirect addressing modes. The register indirect addressing mode will be

discussed in the next section. In direct addressing mode, the operand data is in a

RAM memory location whose address is known, and this address is given as a part

of the instruction. Contrast this with immediate addressing mode in which the

operand data itself is provided with the instruction. While the letter "L" in the

instruction means literal (immediate), the letter "F" in the instruction signifies the

address of the file register location. See the example below, and note the letter F

in the instructions.

MOVLW Ox56

MOVWF Ox40

MOVFF Ox40,0x50

;WREG = 56H (immediate addressing mode)

;copy WREG into fileReg RAM location 40H

;copy data from loc 40H to SOH.

The last two instructions use direct addressing mode. If we dissect the

opcode we see that the addresses are embedded in the instruction, as shown in

Figure 6-1 a.

SECTION 6.2: REGISTER INDIRECT ADDRESSING MODE

We can use register direct or register indirect addressing modes to access

data stored in the general purpose RAM section of the file register. In the last sec-tion we showed how
to use direct addressing mode, which is also called register

direct. The register indirect addressing mode is a very important addressing mode

in the PIC 18. This topic will be discussed thoroughly in this section.
Register indirect addressing mode

In the register indirect addressing mode, a register is used as a pointer to

the data RAM location. In the PICI8, three registers are used for this purpose:

FSRO, FSRI, and FSR2. FSR stands for file select register and must not be con-fused with SFR (special
function register). The FSR is a 12-bit register allowing

access to the entire 4096 bytes of data RAM space in the PIC 18. We use LFSR

(load FSR) to load the RAM address. In other words, when FSRx are used as

pointers, they must be loaded first with the RAM addresses as shown below.

LFSR 0, Ox30

LFSR 1, Ox40

LFSR 2, Ox6F

;load FSRO with Ox30

;load FSRl with Ox40

;load FSR2 with Ox6F

Because FSRO, FSRl, and FSR2 are 12-bit registers they cannot fit into the

SFR address space unless they are split into pieces of an 8-bit size. That is exact-ly what PIC I 8 has done.
The FSR registers have the low-byte and high-byte parts

called FSRxL and FSRxH, as shown in the SFR table of Table 6-1. In Table 6-1

we see FSROL and FSROH, representing the low and high parts of the 12-bit FSRO

register. Note that the FSRxH is only 4-bit and the upper 4 bits are not used.

Another register associated with the register indirect addressing mode is the INDF

(indirect register). Each of the FSRO, FSRl, and FSR2 registers has an INDF reg-ister associated with it,
and these are called INDFO, INDFI, and INDF2. When we

move data into INDFx we are moving data into a RAM location pointed to by the

FSR. In the same way, when we read data from the INDF register, we are reading

data from a RAM location pointed to by the FSR. This is shown below.

LFSR 0, Ox30
MOVWF INDFO

;FSRO = 30H RAM location pointer

;copy contents of WREG into RAM

;location whose address is held by

;12-bit FSRO register

Advantages of register indirect addressing mode

One of the advantages of register indirect addressing mode is that it makes

accessing data dynamic rather than static, as with direct addressing mode.

Example 6-2 shows three cases of copying 55H into RAM locations 40H to 45H.

Notice in solution (b) that two instructions are repeated numerous times. We can

create a loop with those two instructions as shown in solution (c). Solution (c) is

the most efficient and is possible only because of the register indirect addressing

mode. In Example 6-2, we must use "INCF FSROL, F" to increment the pointer

because there is no such instruction as "INCF FSRO, F". Looping is not possible

in direct addressing mode, and that is the main difference between the direct and

register indirect addressing modes. For example, trying to send a string of data

located in consecutive locations of data RAM is much more efficient and dynam-ic using register indirect
addressing mode than using direct addressing mode. See

Example 6-3.

Example 6-2

Write a program to copy the value 55H into RAM memory locations 40H to 45H using

(a) Direct addressing mode.

(b) Register indirect addressing mode without a loop.

(c) A loop.

Solution:

(a)
MOVLW Ox55

MOVWF Ox40

MOVWF Ox41

MOVWF Ox42

MOVWF Ox43

MOVWF Ox44

(b)

MOVLW SSH

LFSR O,Ox40

MOVWF INDFO

INCF FSROL,F

MOVWF INDFO

INCF FSROL,F

MOVWF INDFO

INCF FSROL,F

MOVWF INDFO

INCF FSROL,F

MOVWF INDFO

(c)

COUNT EQU OxlO

MOVLW oxs

MOVWF COUNT

LFSR O,Ox40

MOVLW Ox55

Bl MOVWF INDFO
INCF FSROL,F

DECF COUNT,F

BNZ Bl

;load WREG with value SSH

;copy WREG to RAM location 40H

;copy WREG to RAM location 41H

;copy WREG to RAM location 42H

;copy WREG to RAM location 43H

;copy WREG to RAM location 44H

;load with value SSH

;load the pointer. FSRO = 40H

;copy w to RAM loc FSRO points

;increment pointer. Now FSRO =

;copy W to RAM loc FSRO points

;increment pointer. Now FSRO =

;copy W to RAM loc FSRO points

;increment pointer. Now FSRO =

;copy W to RAM loc FSRO points

;increment pointer. Now FSRO =

;copy W to RAM loc FSRO points

;location lOH for counter

;WREG = 5

;load the counter, Count = 5

to

41H
to

42H

to

43H

to

44H

to

;load pointer. FSRO = 40H, RAM address

;WREG = 55h value to be copied

;copy WREG to RAM loc SFRO points to

;increment FSRO pointer

;decrement the counter

;loop until counter = zero