1 InstructorMeterial Unit3 Introduction

M.
Tech(CSE)-Advanced Computer Architecture-CSE507
3.4. Main Memory:

3.4.1. Terms for Main memory:
Word length: CPU rarely read the individual bits, it always reads a group of bits this
group of bits of fixed length is called as Word. The number of bits in a word is called
Word length.
An n-bit word allows up to 2n different items to be represented.
Word size is typically a multiple of 8common word sizes being 8,16,32, and 64 bits.
Some instruction formats of Motorola 680X0 microprocessor series

Bit name illustration typical use
1 bit status flag. logic variable
8 byte Smallest addressable memory item
Binary –coded decimal digit pair
16 half word Shortest fixed point number .short address
(offset).Short instruction
32 Word Fixed or Floating point number .memory
address. instruction
64 Double word Long instruction .Double –precision
Floating point number
The number of bits in a word varies from the processor to processor. Each word in a
memory assigned with unique number, this number is called as “address”
3.4.2Memory performance parameters:
Symbol Definition Units Meaning
ta Access time Time Time to access a memory word
Time from strat of read to start

tc Cycle time Time
of next
K Block size Words Number of words per block
W Bandwidth Words/sec Word transmission rate
Time to access first of a

T1 Latency Time
sequence of words
Time access entire block from
tb1=t1 + k\w Block access time Time
start of read.
M.Rajasekhara Babu/Faculty/School of Computing Sciences/VIT University/Velloe-14

http://sites.google.com/site/mrajasekharababu/mtech09
M.Tech(CSE)-Advanced Computer Architecture-CSE507
• Latency: The time taken to complete an individual operations

• Throughput: The rate at which operations can be completed.
• Bandwidth: Total rate at which data can be moved between the processor and the
memory system.
3.4.3.Memory operations:
The memory operations READ and WRITE can be viewed as functions similar to
programming languages invoked by the CPU, with in and out parameters.
• READ (in: addr; out: word, completion signal)
On entry: MAR contains address to be read from.
On exit: completion signal is true and MDR contains word stored at addr, of size w
bits
• WRITE (in: addr, word; Out: completion-signal)
On entry: MAR contains address to be written to; MDR contains word of size w
bits.
On exit: completion –signal is true; word as been written to address addr.
• Completion signal: WAIT, ACKNOWLEDGE, READY or ACCEPT
3.4.4.The Memory Bus
In communicating with the memory system, the CPU must supply three types of information:
1. The address within memory to be accessed
2. The type of operation to be performed (read or write)
3. The data to be written (in the case of writes)
A group of wires called a "bus" provide the pathway over which this information can be
conveyed. In the most general case there is a separate address bus, data bus and control bus. The
maximum address that can be specified is determined by the width of the address bus, while the
maximum amount of data that can be transmitted
in a single transfer is determined by the width of the data bus. The control bus carries signals such
as a read command, a write command, data ready indicators, etc.

M Address bus
A
R
CPU Data bus

M Memory
D
R R/W
RDY
The memory address register (MAR) and memory data register (MDR) serve as the interface to
the respective buses and are used by the CPU to communicate with the memory unit. The MAR
specifies the address within memory to be accessed. The MDR (also sometimes called the
memory buffer register or MBR) contains data to be written to memory or receives data that are
read from memory. Basic Bus Operation and Timing Interaction between the CPU and memory
over the bus is coordinated and synchronized via a clock. This clock in many cases runs at a
much slower rate than the clock that drives the CPU due to the relatively slow speed of the
memory system as compared to the CPU. To perform a write to memory, the CPU must: supply
the memory address (via the MAR) supply the data to be written (via the MDR) issue a write
command by appropriately setting the R/W control line wait for the RDY signal from the memory
to determine when the write completes
To perform a read from memory, the CPU must: supply the address from which the data is to be
read issue a read command by appropriately setting the R/W control line wait for the RDY signal
from memory indicating that the data has been obtained transfer the data from the MDR into
some other internal register Each of these sets of operations is said to constitute a "bus

transaction" or "bus cycle". A bus cycle usually requires a number of clock cycles as illustrated
above:
An example of the timing for a read operation is shown below. Note that the RDY signal is used
to indicate when the requested data has been obtained by the memory and made available in the
MDR via the data bus. The access time for the memory can vary as a function of the type of
memory used. In the diagram below the data is available in clock cycle T3. However, if the
memory could not have the data ready at that time, an integral number of extra clock cycles
(called wait states or wait cycles) would have to be inserted to allow the memory additional time
to acquire the requested data. Thus the RDY signal prevents the CPU from attempting to use
invalid data (i.e. the contents of the MDR prior to the arrival of the actual requested data).
The double lines used to represent the address and data bus indicate the presence of multi-bit
information. These collapse to a single line when no valid information is present on the bus. Note
that control signals can be considered asserted when they are 0 (active low) or when they are 1
(active high). Signals that are active low
have a bar over their specifiers or may have a # appended (such as the RDY# signal or the Write
signal (R/W#) which indicates a read command when high but a write command when low.
3.4.5. Byte storage methods
Storage order: A small but important aspect of data representation is the way in which
the bits of a word are indexed.
Indexed convention for bits and bytes of a word
Byte3 byte2 byte1 byte 0

Most Least
Significant Significant
Bit bit
Where the right most bit is assigned the index 0and bits are labeled in increasing order
from right to left
The advantage of this convention is that when is word is interpreted as an unsigned
binary integer.
Lower order indexes corresponding to the numerically last significant and higher order
indexes corresponding to more significant.
Big –Endian: Is the convention Assigning most significant of byte to least address and
least significant of byte to highest address
For example, consider the 32-bit number, 0xDEADBEEF. Following the Big-Endian
convention, a computer will store it as follows:
Little Endian : Is the convention assigning most significant of byte to highest address
and least significant of byte to highest address.
For example, consider the 32-bit number, 0xDEADBEEF. Following the Little-Endian
convention, a computer will store it as follows:
The memory unit is specified by the number of words it contains and the number
of bits in each word. The address lines select one particular word. Each

word in memory is assigned an identification number called an address.

Addresses range from: 0 to 2b - 1 where b is the number of address lines
The term "word" in general refers to the smallest addressable unit of data in memory.
On some machines the smallest addressable unit is the 8-bit byte. On others, access to a
particular byte might require reading the word that contains the byte followed by
extracting the byte of interest. If the address of a multi-byte data item corresponds to the
low order bits within the item, memory is said to be addressed in a "little endian” fashion.
If, on the other hand, the address corresponds to the leading or most significant part of the
data item, the memory is said to be addressed in a "big endian" fashion.
The Intel x86 family and Digital Equipment Corporation architectures (PDP-11,
VAX, Alpha) are representatives of Little-Endian, while the Sun SPARC, IBM 360/370,
and Motorola 68000 and 88000 architectures are Big-Endians. Still, other architectures
such as PowerPC, MIPS, and Intel’s 64 IA-64 are Bi-Endian, i.e. they are capable of
operating in either Big-Endian or Little-Endian mode.
3.5. Types of Main memories: There are two most common semiconductor memories
• Random Access Memory (RAM)
• Read Only Memory (ROM)
3.5.1. RAM: Which contains individual words are directly accessed through wired –in
addressing logic.
It has one distinguishing characteristic i.e., it is possible both to read the data from the
memory and to easily and rapidly write new data into the memory. Both reading and
writing accomplished through the use of electrical signals.

And other characteristic is That is volatile RAM must be provided with a constant power
supply. If the Power is interrupted, then the data are lost. Thus, RAM can be used only as
temporary storage.
RAM Technology has divided into two technologies;
• Static RAM
• Dynamic RAM :
3.5.1.1. Dynamic RAM is made with cells that store data as charge on capacitors. The
presence or absence of charge is interpreted as binary 1 or 0. Because capacitors have a
natural tendency to discharge, dynamic RAMs require periodic charge refreshing to
maintain the stored data. The process of reading a DRAM cell destroys the information
stored there, thus requiring that the information be written back to restore it. Soon after
the power is turned off the charge on the capacitors dissipates hence the DRAMs are
volatile.
A DRAM memory cell uses a single transistor and a capacitor to store a bit of
data. Devices are reported to be in limited production which provide 256 Mbits of storage
in a single device. At the same period, CPUs with 10 million transistors in them are
considered state-of-the-art. Regularity is certainly a major contributor to this apparent
discrepancy. A DRAM is about as regular as it is possible to imagine any device could
be: a massive 2-D array of bit storage cells. In contrast, a CPU has a large amount of
irregular control logic.
A typical DRAM cell with a single MOSFET and a storage capacitor

3.5.1.2. Static RAM: In static RAMs binary values are stored using traditional flip-flop
logic-gate configurations. A static RAM holds its data as long as power is supplied to it.
Reading a cell obtains a copy of the data without destroying the original contents. A
dynamic RAM cell is simpler and hence smaller than a static memory cell. Thus, a
dynamic RAM is more dense (more cells per unit area) and less expensive than a

corresponding static RAM. On the other hand static RAMs have much shorter cycle times
than DRAMs. Consequently DRAMs tend to be favored for large memory requirements,
while SRAMs are used where speed is more critical as in cache memories.
Static RAM cells use 4-6 transistors to store a single bit of data. This provides faster
access times at the expense of lower bit densities. A processor's internal memory
(registers and cache) will be fabricated in static RAM. Because the industry has focussed
on mass-producing dynamic RAM in ever-increasing densities, static RAM is usually
considerably more expensive than dynamic RAM: due both to its lower density and the
smaller demand (lower production volumes lead to higher costs!).
Six-transistor RAM cell: With the addition of two control transistors it is possible to
create the 6-T cell, which has both the true and complemented values

Static RAM is used extensively for second level cache memory, where its speed is
needed and a relatively small memory will lead to a significant increase in performance.
A high-performance 1998 processor will generally have 512kB to 4Mbyte of L2 cache.
Since it doesn't need refresh, static RAM's power consumption is much less than dynamic
RAM, SRAM's will be found in battery-powered systems. The absence of refresh
circuitry leads to slightly simpler systems, so SRAM will also be found in very small
systems, where the simplicity of the circuitry compensates for the cost of the memory
devices themselves.
3.5.2. ROM: One major type of memory that is used in computer is called read-only
memory, or ROM for short. ROM is a type of memory that normally can only be read, as
opposed to RAM, which can be both read and written. There are two main reasons that
read-only memory is used for certain functions within the Computer:
Permanence: The values stored in ROM are always there, whether the power is on or
not. A ROM can be removed from the computer, stored for an indefinite period of time,

and then replaced, and the data it contains will still be there. For this reason, it is called
non-volatile storage. A hard disk is also non-volatile, for the same reason, but regular
RAM is not.
Security: The fact that ROM cannot easily be modified provides a measure of security
against accidental (or malicious) changes to its contents. We are not going to find viruses
infecting true ROMs, for example; it's just not possible. (It's technically possible with
erasable EPROMs, though in practice never seen.)
Applications:
ROM BIOS: Read-only memory is most commonly used to store system-level programs
that we want to have available to the computer at all times. The most common example is
the system BIOS program, which is stored in a ROM called (amazingly enough) the
system BIOS ROM. Having this in a permanent ROM means it is available when the
power is turned on so that the PC can use it to boot up the system. Remember that when
we first turn on the PC the system memory is empty, so there has to be something for the
PC to use when it starts up.
Types of ROM: While the whole point of a ROM is supposed to be that the contents
cannot be changed, there are times when being able to change the contents of a ROM can
be very useful. There are several ROM variants that can be changed under certain
circumstances; these can be thought of as "mostly read-only memory". ) The following
are the different types of ROMs with a description of their relative modifiability:
3.5.2.1. ROM: A regular ROM is constructed from hard-wired logic, encoded in the
silicon itself, much the way that a processor is. It is designed to perform a specific
function and cannot be changed. This is inflexible and so regular ROMs are only used
generally for programs that are static (not changing often) and mass-produced. This
product is analagous to a commercial software CD-ROM that we purchase in a store.
Each type has unique characteristics, but all types of ROM memory have two
Two things in common:
Data stored in these chips is non-volatile -- it is not lost when power is removed.
Data stored in these chips is either unchangeable or requires a special operation to
change.

A diode normally allows current to flow in only one direction and has a certain threshold,
known as the forward breakover, that determines how much current is required before the
diode will pass it on. In silicon-based items such as processors and memory chips, the
forward breakover voltage is approximately 0.6 volts. By taking advantage of the unique
properties of a diode, a ROM chip can send a charge that is above the forward breakover
down the appropriate column with the selected row grounded to connect at a specific cell.
If a diode is present at that cell, the charge will be conducted through to the ground, and,
under the binary system, the cell will be read as being "on" (a value of 1). Iif the cell's
value is 0, and there is no diode link at that intersection to connect the column and row.
So the charge on the column does not get transferred to the row.
3.5.2.2. PROM: This is a type of ROM that can be programmed using special equipment;
it can be written to, but only once. This is useful for companies that make their own

ROMs from software they write, because when they change their code they can create
new PROMs without requiring expensive equipment. This is similar to the way a CD-
ROM recorder works by letting you "burn" programs onto blanks once and then letting
you read from them many times. In fact, programming a PROM is also called burning,
just like burning a CD-R, and it is comparable in terms of its flexibility.
Creating ROM chips totally from scratch is time-consuming and very expensive in small
quantities. For this reason, mainly, developers created a type of ROM known as
programmable read-only memory (PROM). Blank PROM chips can be bought
inexpensively and coded by the user with a programmer.
PROM chips have a grid of columns and rows just as ordinary ROMs do. The difference
is that every intersection of a column and row in a PROM chip has a fuse connecting
them. A charge sent through a column will pass through the fuse in a cell to a grounded
row indicating a value of 1. Since all the cells have a fuse, the initial (blank) state of a
PROM chip is all 1s. To change the value of a cell to 0, you use a programmer to send a
specific amount of current to the cell. The higher voltage breaks the connection between
the column and row by burning out the fuse. This process is known as burning the
PROM.
3.5.2.3.
EPROM: An
EPROM is a
ROM that can
be erased and reprogrammed. A little glass window is installed in the top of the ROM
package, through which you can actually see the chip that holds the memory. Ultraviolet

light of a specific frequency can be shined through this window for a specified period of
time, which will erase the EPROM and allow it to be reprogrammed again. Obviously
this is much more useful than a regular PROM, but it does require the erasing light.
Continuing the "CD" analogy, this technology is analogous to a reusable CD-RW.
Working with ROMs and PROMs can be a wasteful business. Even though they are
inexpensive per chip, the cost can add up over time. Erasable programmable read-only
memory (EPROM) addresses this issue. EPROM chips can be rewritten many times.
Erasing an EPROM requires a special tool that emits a certain frequency of ultraviolet
(UV) light. EPROMs are configured using an EPROM programmer that provides voltage
at specified levels depending on the type of EPROM used.
Once again we have a grid of columns and rows. In an EPROM, the cell at each
intersection has two transistors. The two transistors are separated from each other by a
thin oxide layer. One of the transistors is known as the floating gate and the other as the
control gate. The floating gate's only link to the row (wordline) is through the control
gate. As long as this link is in place, the cell has a value of 1. To change the value to 0
requires a process called Fowler-Nordheim tunneling. Tunneling is used to alter the
placement of electrons in the floating gate. An electrical charge, usually 10 to 13 volts, is
applied to the floating gate. The charge comes from the column (bitline), enters the
floating gate and drains to a ground.
This charge causes the floating-gate transistor to act like an electron gun. The excited
electrons are pushed through and trapped on the other side of the thin oxide layer, giving
it a negative charge. These negatively charged electrons act as a barrier between the
control gate and the floating gate. A device called a cell sensor monitors the level of the
charge passing through the floating gate. If the flow through the gate is greater than 50
percent of the charge, it has a value of 1. When the charge passing through drops below
the 50-percent threshold, the value changes to 0. A blank EPROM has all of the gates
fully open, giving each cell a value of 1.
To rewrite an EPROM, you must erase it first. To erase it, you must supply a level of
energy strong enough to break through the negative electrons blocking the floating gate.

In a standard EPROM, this is best accomplished with UV light at a frequency of 253.7.

Because this particular frequency will not penetrate most plastics or glasses, each
EPROM chip has a quartz window on top of it. The EPROM must be very close to the
eraser's light source, within an inch or two, to
Work properly.
An EPROM eraser is not selective, it will erase the entire EPROM. The EPROM must be
removed from the device it is in and placed under the UV light of the EPROM eraser for
several minutes. An EPROM that is left under too long can become over-erased. In such
a case, the EPROM's floating gates are charged to the point that they are unable to hold
the electrons at all.
3.5.2.4. EEPROM: The next level of erasability is the EEPROM, which can be erased
under software control. This is the most flexible type of ROM, and is now commonly
used for holding BIOS programs. When you hear reference to a "flash BIOS" or doing a
BIOS upgrade by "flashing", this refers to reprogramming the BIOS EEPROM with a
special software program. Here we are blurring the line a bit between what "read-only"
really means, but remember that this rewriting is done maybe once a year or so,
compared to real read-write memory (RAM) where rewriting is done often many times
per second!
Though EPROMs are a big step up from PROMs in terms of reusability, they still require
dedicated equipment and a labor-intensive process to remove and reinstall them each time
a change is necessary. Also, changes cannot be made incrementally to an EPROM; the
whole chip must be erased. Electrically erasable programmable read-only memory
(EEPROM) chips remove the biggest drawbacks of EPROMs.
In EEPROMs:
* The chip does not have to removed to be rewritten.
* The entire chip does not have to be completely erased to change a specific portion of it.
* Changing the contents does not require additional dedicated equipment.
Instead of using UV light, you can return the electrons in the cells of an EEPROM to
normal with the localized application of an electric field to each cell. This erases the
targeted cells of the EEPROM, which can then be rewritten. EEPROMs are changed 1

byte at a time, which makes them versatile but slow. In fact, EEPROM chips are too slow
to use in many products that make quick changes to the data
stored on the chip.
Manufacturers responded to this limitation with Flash memory, a type of EEPROM that
uses in-circuit wiring to erase by applying an electrical field to the entire chip or to
predetermined sections of the chip called blocks. Flash memory works much faster than
traditional EEPROMs because it writes data in chunks, usually 512
bytes in size, instead of 1 byte at a time.
Flash memory is a type of EEPROM chip. It has a grid of columns and rows with a cell
that has two transistors at each intersection (see image below). The two transistors are
separated from each other by a thin oxide layer. One of the transistors is known as a
floating gate, and the other one is the control gate. The floating gate's only link to the
row, or wordline, is through the control gate. As long as this link is in place, the cell has a
value of 1. To change the value to a 0 requires
a curious process called Fowler-Nordheim tunneling.
Tunneling is used to alter the placement of electrons in the floating gate. An electrical
charge, usually 10 to 13 volts, is applied to the floating gate. The charge comes from the
column, or bitline, enters the floating gate and drains to a ground.
This charge causes the floating-gate transistor to act like an electron gun. The excited
electrons are pushed through and trapped on other side of the thin oxide layer, giving it a
negative charge. These negatively charged electrons act as a barrier between the control
gate and the floating gate. A special device called a cell sensor monitors the level of the
charge passing through the floating gate. If the flow through the gate is greater than 50
percent of the charge, it has a value of 1. When the charge passing through drops below
the 50-percent threshold, the value changes to 0. A blank EEPROM has all of the gates
fully open, giving each cell a value of 1.
The electrons in the cells of a Flash-memory chip can be returned to normal ("1") by the
application of an electric field, a higher-voltage charge. Flash memory uses in-circuit
wiring to apply the electric field either to the entire chip or to predetermined sections
known as blocks. This erases the targeted area of the chip, which can then be rewritten.

Flash memory works much faster than traditional EEPROMs because instead of erasing
one byte at a time, it erases a block or the entire chip, and then rewrites it.
Memory Type Category Erasure Write Mechanism Volatility
1.Random Access Read-write electrically Electrically Volatile

Memory (RAM) memory Byte –level
2.Read Only Read -only Not Possible Masks
Memory(ROM) Memory
3.Programmable
ROM(PROM)
4.Erasable PROM UV light, Non Volatile
(EPROM) Chip Level
5.Flash Memory Electrically, Electrically
Block-level
6.Electrically Read-only Electrically
Erasable ROM
3.6. Memory Cells organization: The memory cells in RAM or ROM are organized in a
one-dimensional or 2-Dimensional array.

• The memory block diagram contains 2M+N storage locations

• When a bit has been selected the set of sense amplifiers are used to read/write to
the memory locationMemory Cell Operation
• Horizontal rows are referred to as wordlines where the vertical lines are called
bitlines
Control
Control
Select
Data In
Cell
Cell
Select
Reading
Writing

Chip organization: Most of the semiconductor memories are packed in chips. Memory
chips may store information . There are several memory organization techniques used for
a chip and the most common of these are 2D and 21/2 D Organization.
RAM chip:
• RAM is better suited for communication with the CPU
• It has a bi-directional bus that allows the transfer of data either from memory to CPU
during read operation or from CPU to memory during a write operation.
• A bi-directional bus can construct from three state buffers.
• A three state buffer output can be placed one of three states
Logical 0
Logical 1
High impedance state: behaves like an open circuit, which means that output does
not carry a signal and has no logic significance.
• Typical RAM chip:

CS1
Chip select
CS2
Chip select2
RD 8 bit data
Read 128 x 8
RAM bus
WR
Write
AD7
• Capacity of memory 128 words of 8 bits per word

• This requires 7-bit address and an 8 bit bi-directional bus.
• The read and write specify the memory operations
• Two chips select control inputs are for enabling only when it is selected by
microprocessor.
CS1 CS2 RD WR Memory function State of data bus

The 0 0 x x Inbit High impedence unit
is in 0 1 x x Inbit High impedence
1 0 0 0 Inbit High impedence
1 0 0 1 Write Input data to RAM
1 0 1 x Read Output data from RAM
1 1 x x Inbit High impedence
operations only when CS1=1 and CS2=0 .The bar on the top of the second select variable
indicates that this input is enabled when equal to 0.
If the chip select inputs are not enabled,or if they are enabled .But the read or write inputs
are not enabled,the memory is inhibited and ts data bus is in aimpedence state.
A memory design problem that computer architect may encounter is the following
• Given that N x W –bit RAM IC denoted Mn,w are available for design of N1 x
W1 –bit RAM,
Where N1 >= N and \ or W1 >=W.

• A general approach is to construct a p x q array of the MN,W IC’s,

Where p= cN1/N
Where q= cW1/W
cX denotes the smallest integer grater than or equal to x.

There are two types of organization of N1 x W1 –bit RAM using N x W –bit Ram
• Increasing the word size of a RAM
• Increasing number of words stored in a RAM
Example : Consider the task of designing an N x 4W-bit Ram using N x W –bit IC’s
N1 = N W1 = 4W
4 N x W –bit IC’s required for
N=N W=W
N x 4W-bit RAM.
p= cN1/N = N/ N =1
Increasing the word size of a RAM by
q= cW1/W = 4W/W=4
a factor of four
Increasing the word size of a RAM by a factor of four
Data D
4w
2m x w 2m x w 2m x w 2m x w
RAM RAM RAM RAM
Address
CS
W Increasing
R

number of words by the factor of 4:
2m x w
RAM
2m x w
RAM
2m x w
RAM
2m x w
RAM
ROM chip:
• The design of computer system must calculate the amount of memory required for
the perticular application and assign it to either RAM or ROM
• The inter connection between memory and processor is then established from
knowledge of the size of memory needed and the type RAM and ROM chip

• Memory address map: Is a pictorial representaion of assigned address space for each
chip in the system
• Typical RAM chip
Chip select CS1
Chip select2 CS2

512 x 8 8 bit data
ROM bus
9-bit address
AD9
The design layout for increasing number of words or size of words with ROM IC’s is
similar to the above layout.
There is only one line ‘chip select’ with which we can read data from the ROM. No
separate read command line required for this ROM, because this ROM allows for only
read operation. No write operation can be performed over this ROM.
3.7. Error Detection and Correction codes: Computer as an electronic media,

therefore, there is a possibility of errors being introduced during the transmission of
signals. These errors may result from so, disturbance in transmission media or sometimes
because of external disturbances. Most of these errors result in change of a bit from 0 to 1
or 1to 0 .
There are two types of memory errors in RAM (especially DRAM) are "soft" errors due
to radiation-induced bit switching, and "hard" errors due to the unexpected deterioration
of a memory chip. Soft errors do not indicate lasting damage to the memory board, but
they do corrupt programs or data. Hard errors demand physical repairs. Single bit
memory failures are the most common. A hard single bit failure, such as that caused by a
completely dead chip can be corrected if each chip supplies only one bit of each word.
Error Detection And Correction (EDAC) memory is the most common level of protection

for minicomputers and mainframes whereas the cheaper parity protection is more
common in microcomputers.
One of the simplest error detection code which is used commonly is called Parity
bit.
Parity bit:A parity bit is an extra bit added with binary data such that it makes the
total number of 1’s in the data either odd or even.
For example ,in a 7 bit data 0110101 let us add an 8th bit which is a parity bit.If the added
parity bit is even parity bit then the value of this parity bit should be 0 as already four 1’s
are these in the 7 bit number.If we are adding an odd parity bit then it will be 1,since we
already have four 1 bits in the number and on adding 8 th bit(which is a parity bit) as 1
we are making total nuber of 1’s in the number (which now includes parity bit also)as
5,an add number.
Similarly in 001010101 parity bit for even parity is 1

Parity bit for odd parity is 0
But how does the parity bit detect an error ?we will discuss this issue in genral as a error
detection and correction system
For
transferring or storing N-bit data with error detection and or correction mechanism .a
error detection code os generated using a function(for example ,even parity bit generation

)at the sourse or storage end.The data as well as the error detection code is passed on to
the data destination wher once again error detection code is generated using the same
function on the data .The comparison of the generated and incoming error detection code
determines whether the error has occurred or not.In case error has occurred then an error
signal is generated and correction machanism (in case the error code is error detection
and correction code ,this step is not valid if parity bits are used) is applied on the data.In
case ,no error is detected then no correction ios needed by the corrector and data is sent as
it is.Sometimes ,it ios not possible to correct the erors .such conditions are reprted.
The parity bit is only an error detection code .The concept of parity bit has been later on
develped and error detection and correction code has been developed using more than on
parity bits.One such code is “Hamming error correcting cod”.
Hamming error correctiing code: This code was devised by Richard hamming at bell
laboratories.We will discuss these code with the help of Venn diagrams,for simplicity we
will confine only to 4 bit data.Figure shows the Venn diagram with the filled in data
bits which are filled in the intersectiin inner compartments.
B B
A A
0 0
1 0
0 1 1 0 1
C C
FIG-a FIG-b

B B
A A
0 1 0
1
1 1
0 0 0 0
0 0
Fig:c C FIG-d
C
The next step is to fill in the parity bits for these four data bit. The principle here is
that we add the parity bits such that the total number of 1’s in a circle is even (even
parity). Figure ---(b) is filled up using this rule. Please note that each of this circle
have even number of 1’s
After the data transfer, let is say ,we encounter a situation where one of the data bit is
changed from 1 to 0.Thus an error has occurred .This condition is shown in fig---©
.Please note except for the data bit no other bit has changed. How will this error be
detected and rectified .Fig—(d) shows the detection and rectification .The parity bit of
the two circles are indicating error of on bit , since two circles are indicating errors
,therefore ,the error lies at the intersection of these two circle. so, we have not only
recognized the error but also its souce. Thus in this case by changing the bit in error, from
0 to 1 we will rectify the error.
Now let us discuss a scheme for error correction and detection of single bit error in the
context of figure, for 8 bit words. the first question in this respect is : what should be the
length of code ? before answering this question we have to look into the comparison logic
of error detection .The error detection is done by comparing the two 1 bit error correction
detection and correction codes fed to the comparison logic bit by bit .Let us have a
comparison logic which produce a 0 if the compared bits are same or else it produce a
1.Therefore ,if similar position bits are same then we will fit 0 at that bit position, but if

there are different ,that is this bit position may point to some error, then this particular bit
position will be marked as 1.This way a match word call syndrome word is constructed.
This syndrome word is i bit long, therfore ,can represent 2'’ values or combinations. For
example, a 4 bit syndrome word can represent 2<4> =16 values which range from 0 to
15 as:
0000 0001 0010 0011 0101 0100 0110 0111

1000 1001 1010 1011 1101 1101 1110 1111
The value 0000 or 0 represent no error while the other values i.e., 2I –1 (for 4 bits
24-1=15) that is from 1 to 15) represent an error condition.Each of these 2I –1(or 15 for 4
bits) can be used torepresent an error of a perticular bit.Since ,the error can occur during
the transmission of N bit data plus I bit error correction code,therfore ,we need to have at
least N+I error values to represent them.Therefore ,the number of error correction bits
should be found from the following eqation
2I –1 > N+I
If we ate ssoming 8 bit word then we need to have

Similarly for 16 bit wird we need to have I=5
25 –1 –31 ,16+5=21
for 16 bit word we need to have 5 error correcting bits.
The next step in this connction will be to arrange the word and its 4 bit error correction
code in such a way that a perticular value of the syndrome word specifies an error ion a
uniqe bit( which may be data or error detection code ).The following arrangement of the
(N+I) bits si suggested.
Bit position 12 11 10 9 8 7 6 5 4 3 2 1
Data Bits 8 7 6 5 4 3 2 1
Correct bits 8 4 2 1

The above arrangement is derived on the basis that

• Syndrome word zero implies no error.
•
If syndrome word contains only one bit as it should be inferred that error has occurred
only in the parity bits, therefore ,no correction is needed in data .But how can
implement it? This can be implicated by assigning the check bit as 1st ,2nd ,4th and 8th
bit position.
•
In case more than one bit in syndrome word are set as the numerical value of the
syfdrome word should determine the bit position which is in error.
The arrangement shown in fig---------has an added advantage ,that is each bit position can
be calculated as a function of correction bit positions .Please note ,in case any one of the
correction bit has changed during data transmission , that implies any one of 1st of 2nd or
4th or 8th bit position data have altered, therefore the syndrome bit will be ooo1 if the data
at first bit position has changed, or 0010 if 2nd bit position has changed :or 0100 if data at
4 th bit position has changed ,or 1000 if data 8th bit position has changed. Thus the
proposed bit arrangement scheme of fig----- ,satisfies the second assumption for the bit
arrangement scheme. The next assumption in this regard is the value of syndrome word
should indicate the bit position which is in error ,that is ,if there is error in bit position 3 it
should change correction bits of bit position 1 and 2 and so on. Let us discuss how this
can be achieved.
Bit position in error Effected bit position of Comments

Syndrome
1 - - - 1 One bit position error
2 - - 2 - One bit position error
3 - - 2 - 1+2=3
4 - 4 - One bit position in error
5 - 4 - 1 4+1=5
6 - 4 2 - 4+2=6

7 - 4 2 1 4+2+1=7
8 8 - - - One bit position in error
9 8 - - 1 8+1=9
10 8 - 2 - 8+2=10
11 8 - 2 1 8+2+1=11
12 8 4 - - *+4=12
We are assuming that only one bit can be in error. The table given above indiacate that
the forst bit in syndrome word should be1 if any one of the 1st ,3rd,5th 7th and 11th bit
positions is in error, the second bit of syndrome word should be 1 if any one of the 2nd
3rd 6th 7th 10th and 11th or 12th bit positions is in error and the fourth bit of syndrome
word should be 1 if any of the 9th ,10th,11th,or 12th bit position is in error.
Since the 1st ,2nd 4th 8th bit position are occupied by correction bits or check bits at the
source ,therefore ,they should not be used for calculating check bits.
Based on the above facts ,the check bits should be calculated as :
Check bit =1 Even parity of (3rd ,5th, 7th,9th,& 11th bit position)
Check bit 2=Even parity of (3rd,6th ,7th,10th,11th bit position)
Check bit 3= Even parity of(3rd,6th,7th,12th bit position)
Check bit 4= Even parity of(9th,10th,11th,12th bit positions)
Or in other words(refer fig )

Check bit =1 Even parity of (data bits 1,2,4,5,7)
Check bit 2=Even parity of (data bits 1,3,4,6,7)
Check bit 3= Even parity of(data bits 2,3,4,8)
Check bit 4= Even parity of(Data bits 5,6,7,8)
This is called a single error correcting(SEC)code. Let us see an example of error
correction using this code.
Example: An 8 bit input word 01011011 on transmission is received as 01001011 how
the SEC code if used can rectify this error?
Solution: The SEC code for 8 bit word is of 4 bits

Check bit =1 Even parity of (1,1,1,1,1) =1

Check bit 2=Even parity of (1,0,1,0,1)= 1
Check bit 3= Even parity of(data bits 1,0,1,0)= 0
Check bit 4= Even parity of(Data bits (1,0,1,0)=0
The data received as 010011011
Check bit =1 Even parity of (1,1,1,0,1) =0
Check bit 2=Even parity of (1,0,1,0,1)= 1
Check bit 3= Even parity of(data bits 1,0,1,0)= 0
Check bit 4= Even parity of(Data bits (0,0,1,0)=1
Syndrome word is compare the received check bits to calculated check bits of received
data
0 0 1 1
(Ex-or) 1 0 1 0
---------------------------------------------
1 0 0 1
The syndrome word=1001 , which implies that 9th bit position in the received 12 bit
information is error.
The received data is 01001011
The correct data is 01011011
This is called a single error correcting (SEC) code.Let us see the example of error
correction using this code>

Input Word = 0101000000111001
C1 = M1⊕ M2⊕ M4 ⊕ M5⊕ M7⊕ M9 ⊕ M11 ⊕ M12 ⊕ M14 ⊕ M16

C2= M1⊕ M3⊕ M4 ⊕ M6⊕ M7⊕ M10 ⊕ M11 ⊕ M13 ⊕ M14 ⊕ M17
C3 = M2⊕ M3⊕ M4 ⊕ M8 ⊕ M9 ⊕ M10 ⊕ M11 ⊕ M15 ⊕ M16⊕ M17
C4 = M5⊕ M7⊕ M9 ⊕ M11 ⊕
C5 = M12⊕ M13 ⊕ M14 ⊕ M15 ⊕ M16⊕ M17


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M.

Tech(CSE)-Advanced Computer Architecture-CSE507

3.4. Main Memory:

Some instruction formats of Motorola 680X0 microprocessor series

Symbol Definition Units Meaning

ta Access time Time Time to access a memory word

Time from strat of read to start

K Block size Words Number of words per block

W Bandwidth Words/sec Word transmission rate

Time to access first of a

M.Rajasekhara Babu/Faculty/School of Computing Sciences/VIT University/Velloe-14

• Latency: The time taken to complete an individual operations

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CPU Data bus

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Byte3 byte2 byte1 byte 0

M.Rajasekhara Babu/Faculty/School of Computing Sciences/VIT University/Velloe-14

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word in memory is assigned an identification number called an address.

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A typical DRAM cell with a single MOSFET and a storage capacitor

M.Rajasekhara Babu/Faculty/School of Computing Sciences/VIT University/Velloe-14

M.Rajasekhara Babu/Faculty/School of Computing Sciences/VIT University/Velloe-14

M.Rajasekhara Babu/Faculty/School of Computing Sciences/VIT University/Velloe-14

M.Rajasekhara Babu/Faculty/School of Computing Sciences/VIT University/Velloe-14

M.Rajasekhara Babu/Faculty/School of Computing Sciences/VIT University/Velloe-14

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M.Rajasekhara Babu/Faculty/School of Computing Sciences/VIT University/Velloe-14

M.Rajasekhara Babu/Faculty/School of Computing Sciences/VIT University/Velloe-14

In a standard EPROM, this is best accomplished with UV light at a frequency of 253.7.

M.Rajasekhara Babu/Faculty/School of Computing Sciences/VIT University/Velloe-14

M.Rajasekhara Babu/Faculty/School of Computing Sciences/VIT University/Velloe-14

Memory Type Category Erasure Write Mechanism Volatility

1.Random Access Read-write electrically Electrically Volatile

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• The memory block diagram contains 2M+N storage locations

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• Capacity of memory 128 words of 8 bits per word

CS1 CS2 RD WR Memory function State of data bus

M.Rajasekhara Babu/Faculty/School of Computing Sciences/VIT University/Velloe-14

• A general approach is to construct a p x q array of the MN,W IC’s,

cX denotes the smallest integer grater than or equal to x.

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number of words by the factor of 4:

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Chip select CS1

Chip select2 CS2

3.7. Error Detection and Correction codes: Computer as an electronic media,

M.Rajasekhara Babu/Faculty/School of Computing Sciences/VIT University/Velloe-14

Similarly in 001010101 parity bit for even parity is 1

M.Rajasekhara Babu/Faculty/School of Computing Sciences/VIT University/Velloe-14

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M.Rajasekhara Babu/Faculty/School of Computing Sciences/VIT University/Velloe-14

0000 0001 0010 0011 0101 0100 0110 0111

If we ate ssoming 8 bit word then we need to have

M.Rajasekhara Babu/Faculty/School of Computing Sciences/VIT University/Velloe-14

The above arrangement is derived on the basis that

Bit position in error Effected bit position of Comments

M.Rajasekhara Babu/Faculty/School of Computing Sciences/VIT University/Velloe-14

Or in other words(refer fig )

M.Rajasekhara Babu/Faculty/School of Computing Sciences/VIT University/Velloe-14

Check bit =1 Even parity of (1,1,1,1,1) =1

M.Rajasekhara Babu/Faculty/School of Computing Sciences/VIT University/Velloe-14