Lecture-53

Mode 2: (Strobed Bidirectional bus I/O)

This functional configuration provides means for communicating with
a peripheral device on a single 8-bit I/O data bus in both directions,
i.e., for both transmitting and receiving data. Control and status lines
(handshake signals) are provided to handle the flow of data on the
I/O bus. Interrupt generation and enable/disable functions are also
available similar to mode-1. The mode-2 functional definitions are as
follows:
1. Only Group A can be programmed in mode-2.
2. It consists of an 8-bit bidirectional I/O port (PORT A) and a 5-bit
control port (PORT C).
3. Both input & outputs are latched in PORT A buffer.
4. Only 5-bits of PORT C (PC7-PC3) are used for generating
control signals and checking status of PORT A.
5. PORT B can be programmed independently either in mode-0 or
in mode-1.
Fig.9.22 shows an 8255A set up with PORT A on mode 2. The
control word to program GROUP A in mode-2 is
D7 D6 D5 D4 D3 D2 D1 D0
Mode Group A PA PCU Gp B PB PCL
1 1 X X X X X X
Group B may be programmed in either mode-0 or mode-1
independently.
Control Signal Definitions:
The functions of PORT C lines as determined by mode-2 are
discussed below:
 8
PA7-PA0
INTE 1
PC6 ACKA
F/F
PC7 OBFA

INTE 1
PC4 STBA
F/F
PC5 IBFA

RD

WR
PC3 INTRA

Fig.9.22 8255A Group A Programmed in Mode-2

OUTPUT Operation:
PC7 (OBF A): Output buffer full signal for PORT A. The OBF A output
will go low to indicate that the CPU has written data out to PORT A.
The OBFA will be set by the rising edge of WR input and reset by
ACK A input being low.
PC6 (ACK A): Acknowledge input signal for PORT A. A low on this
input informs the 8255A that the data from PORT A has been
accepted. The difference between ACK A in mode-1 and mode-2 is
that in mode-2 the output of the PORT A is normally in a tri-state
condition, so the ACK A signal enables the output buffer of PORT A
in addition to indicating that the external device has accepted the
PORT A data.
INTE F/F-1: The interrupt enable flip-flop INTE F/F-1 is associated
with OBF A. It is controlled by bit set/reset of PC6.
The timing diagram of 8255A Group A programmed in mode-2 for
output operation is shown in fig.9.23a.

INTRA

WR

OBFA

ACKA

PA7-PA0 Valid Data

Fig.9.23a Output Timing Waveform of Group A Programmed in Mode-2

Input Operation:
PC4 (STB A): Input strobe for PORT A. A low on this input loads data
into the input latch.
PC5 (IBF A): Input buffer full signal for PORT A. A high on this output
indicates that data has been loaded into the input latch.
INTE F/F-2: This interrupt enable flip-flop INTE F/F -2 is associated
with IBF A. It is controlled by bit set/reset of PC4.
PC3 (INTR A): Interrupt request output for port A. A high on this
output can be used to interrupt the CPU for both input and output
operations. When PC6 is set, this signal indicates that the data written
into port A by the CPU has been accepted by the external device.
When PC4 is set, this signal indicates that the data has been written
into PORT A by an external device. By proper control of PC4 and PC6
bits an interrupt driven bidirectional 8-bit data bus between the CPU
and a peripheral device or even another CPU can be established.

The timing diagram of 8255A Group A programmed in mode-2 for

input operation is shown fig.9.23b.

STBA

IBFA

INTRA

RD

PA7-PA0 Valid Data

Fig.9.23b Input Timing Waveform of Group A Programmed in Mode-2

Special Mode Combination Consideration:
There are several combinations of modes when not all of the
bits in port C are used for generating control signals or for checking
status. The remaining bits of PORT C can be used as follows:
If the remaining bits are programmed as inputs, all the input
lines can be accessed during a normal PORT C read. If the remaining
lines are programmed as outputs, bits of PORT C upper (PC7-PC4)
must be individually accessed using the bit set/reset function.
However, bits of PORT C lower (PC3-PC0) can be accessed using the
bit set/reset function or accessed as a threesome by writing into
PORT C. It is always better to output data on the remaining bits of
PORT C using bit set/rest function.

Reading PORT C Status:

In mode-0 PORT C is used to transfer data to or from the
peripheral device. However, when 8255A is programmed to function
in mode-1 or in mode-2, few lines of PORT C generates or accepts
handshaking signals with the peripheral device as explained earlier.
Normally, in mode-1 and in mode-2, data transfer takes place in
interrupt driven mode. But one can check the status of data port for
data transfer operation without using interrupt. 8255A does not have
separate status word register but reading the contents of PORT C
allows the programmer to test or verify the status of each peripheral
device and change the program flow accordingly. There is no special
instruction to read the status information from port C. A normal read
operation of PORT C is executed to perform this function. The format
of status word in different modes is given below:
Mode-1: Status word
Input configuration
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
I/O I/O IBFA INTEA INTRA INTEB IBFB INTRB
Group A Group B
Output configuration
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
OBFA INTEA I/O I/O INTRA INTEB OBFB INTRB
Group A Group B
Mode 2: Status word
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
OBFA INTE1 IBF INTE2 INTRA I/O I/O I/O