Introduction to FPGA

Guan-Lin Wu
Outline
z Introduction to PLD
z Introduction to FPGA
z FPGA Example – Altera Cyclone II
z Altera Quartus II
z Lab
World of Integrated Circuits

Full-Custom Semi-Custom User

ASICs ASICs Programmable

PLD FPGA
 Digital Logic
Digital Logic Function

Product AND (&)

3 Inputs Sum OR (|)

Black Box Truth Table SUM of PRODUCTS

Boolean Logic Minimisation

Connect Standard Logic Chips

Very Simple Glue Logic

FIXED Logic

Transistor Switches
 Programmable Logic
Devices PLDs
Un-programmed State
„ Different Types
„ SUM of PRODUCTS
Planes of
ANDs, ORs
„ Prefabricated

„ Programmble Links

„ Reconfigurable Logic Function

Inputs

ANDs Sums

OR

Programmed PLD
Product Terms
Sum of Products
How can we make a
“programmable logic”?
z SRAM-based
z Reconfigurable
z Track latest SRAM technology
z Volatile
z Generally high power
z Anti-fuse technique
z One-time programmable
z Non-volatile – security app.
 Complex PLDs

„ CPLDs
„ Programmable PLD Blocks

„ Programmable Interconnects

„ Electrically Erasable links

CPLD Architecture

Feedback Outputs
 Field Programmable Gate
Arrays FPGA
z Field Programmable Gate Array
z New Architecture
z ‘Simple’ Programmable Logic Blocks
z Massive Fabric of Programmable
Interconnects

Large Number of Logic Block ‘Islands’

1,000 … 100,000+
in a ‘Sea’ of Interconnects

FPGA Architecture
 Logic Blocks
z Logic Functions implemented in Lookup
Table LUTs
z Multiplexers (select 1 of N inputs)
z Flip-Flops. Registers. Clocked Storage
elements.
16-bit SR
16x1 RAM

a 4-input
LUT
b
y
c
mux
d flip-flop
q
e
clock
clock enable
set/reset

FPGA Fabric Logic Block

 Lookup Tables LUTs
z LUT contains Memory Cells to implement small
logic functions
z Each cell holds ‘0’ or ‘1’ .
z Programmed with outputs of Truth Table
z Inputs select content of one of the cells as output
3 Inputs LUT -> 8 Memory Cells

16-bit SR
16x1 RAM

a 4-input
LUT
b
3 – 6 Inputs c
y
mux
d flip-flop
q
e
clock
clock enable
set/reset

Static Random Access Memory

SRAM cells
Multiplexer MUX
 Logic Blocks
z Larger Logic Functions built up by
connecting many Logic Blocks together
 Clocked Logic
z Flip Flops on outputs. CLOCKED storage elements.
z Sequential Logic Functions (cf Combinational
Logic LUTs)
z Pipelines. Synchronous Logic Design
z FPGA Fabric driven by Global Clock (e.g. BX
frequency) 16-bit SR
16x1 RAM

a 4-input
LUT
b
y
c
mux
d flip-flop
q
e
clock
clock enable
set/reset

FPGA Fabric

Clock
Circuit Compilation
1. Technology Mapping

LUT

2. Placement
LUT
Assign a logical
LUT to a physical
? location.

3. Routing

Select wire segments

And switches for
Interconnection.
Routing Example
FPGA

Programmable Connections
Which Way to Go?
ASICs FPGAs

Off-the-shelf
High performance
Low development cost
Low power
Short time to market
Low cost in
high volumes Reconfigurability
Other FPGA Advantages

z Manufacturing cycle for ASIC is very costly,

lengthy and engages lots of manpower
z Mistakes not detected at design time have large
impact on development time and cost
z FPGAs are perfect for rapid prototyping of digital
circuits
z Easy upgrades like in case of software
z Unique applications
z reconfigurable computing
Major FPGA Vendors

SRAM-based FPGAs
z Xilinx, Inc.
Share over 60% of the market
z Altera Corp.
z Atmel
z Lattice Semiconductor

Flash & antifuse FPGAs

z Actel Corp.
z Quick Logic Corp.
FPGA Example –
Altera Cyclone II
Cyclone II EP2C20 Block
z Logic array – LUTs
z Block memory –
M4K blocks
z Embedded
Multipiers
z Input/output
Modules (IOEs)
z PLLs
Cyclone II EP2C20 Block

Embedded
Logic Array Multipliers

M4K Memory
Blocks I/O
Elements

Phase-Locked
Loops
Cyclone II EP2C20
z 18,752 LEs
z 52 M4K RAM blocks
z 240K total RAM bits
z 52 9x9 embedded multipliers
z 4 PLLs
z 16 Clock networks
z 315 user I/O pins
z SRAM Based volatile configuration
Logic Element
z 16 LEs forms a Logic Array Block (LAB)
z Normal mode
z Arithmetic mode
Logic Element
Logic Element
z Normal Mode – general logic operations
Logic Element
z Arithmetic Mode – adder, counter,
accumulators, comparator
Logic Array Blocks Structure
 Cyclone II Logic Array Block (LAB)
4
z 16 LEs LE1

Fast Local Interconnect

4
z Local Interconnect LE2
4
LE3
z LE carry chains Direct link 4
LE4 Direct link
interconnect
z Register chains to left
interconnect
to right

4
LE13
4
LE14
4
LE15
4
LE16
Row Interconnect Connections
z Direct link, R4, R24 interconnects
Column Interconnect
Connections
z Register chain, C4,
C16
Register Chain Interconnects
z LEs can be connected for
implementing fast adder,
counters, shift register
M4K RAM
Cyclone II I/O Features
z In/Out/Tri-state
z Different Voltages and I/O Standards
z PCI, PCI-X, LVDS I/O standard
z Flip-flop option
z Pull-up resistors
z DDR interface
z Series resistors
z Bus keeper
z Drive strength control
z Slew rate control
z Single ended/differential
Advance Architecture on
Modern FPGAs
More Guts
z Additional components
z Dedicated computation units
z Processor cores
z DSP blocks
Dedicate Arithmetic Blocks

QuickLogic

Altera
Xilinx
Processor Cores
Altera DE2-70