1

Department of Engineering
The Australian National University

ENGN3227 Analogue Electronics

Capacitance Meter

Abstract
The primary design objective of this project is to build an electronic cir-
cuit that can accurately measure the capacitance for ranges as low as 10 pF. A
technique using a voltage ramp is adopted due to its simplicity and accuracy
over other capacitance measuring schemes. The systematic design and imple-
mentation of the capacitance meter is discussed. The circuit design is verified
by performing Pspice simulations and extensive lab testing. PCB designing is
also presented for the capacitance meter.

Aastha Gupta < u2505865 >, Alex Cheng < u2554184 > &
Saba Latif< u4139263 >

24th October, 2006

2 1 INTRODUCTION

1 Introduction

Whenever a measurement of a quantity is performed that quantity is compared to

a reference quantity; and a ratio of the measured quantity to the reference quantity
is obtained as a dimension less number. Consider measuring a person’s height by
comparing his/her height to a meter ruler. The measurement is obtained as a number,
which is the ratio of the person to a calibrated meter ruler. The same applies to
the capacitance meter. To measure capacitance, stable and time invariant reference
components are required. There are several schemes that can be employed to measure
capacitance, such as voltage ramp method, RC timing method and resonant frequency
method.

For the purpose of this project, a voltage ramp method is adopted. The voltage
ramp method is chosen because of its accuracy and simplicity. This method involves
simple measurements of voltages; which are easier to measure than currents.
dV
The voltage ramp is given by dt
. The expression for current through capacitor is
given by:

dV
I=C (1)
dt

Where, I is the current through the capacitor C is the capacitance of the capacitor
and V is the voltage across the capacitor.

The Capacitance C is then determined by

dV
C = I/ (2)
dt

V
Where I = R

This remainder of this report is organised as follows. The detailed theory of the
circuit design is presented in Section II. The implementation of the circuit is discussed
in Section III. Results are presented in Section IV. Finally conclusions are drawn in
Section V.
 3

Figure 1: Voltage Ramp Circuit

2 Theory
The key concept of the capacitance meter circuit design is to use Eq. (1) to measure
the capacitance over a very wide range, from picofarads to thousands of microfarads.
The voltage ramp circuitry is utilised to measure the rate of change of voltage across
the capacitor. The current is measured by adding a load resistor to the circuit. Using
this technique, capacitances down to about 10 pF can be measured. For higher values
of capacitances, a simple RC timing method is used to determine the capacitance.
The RC timing method uses exactly the same circuitry as the voltage ramp method.
A Microcontroller is used to automatically determine the appropriate technique to
use, and to output values on the digital display.
This section of the report systematically explains the design of the capacitance
meter. The electronic circuit can be broken down into three main sections:

1. Analogue Voltage Ramp

2. Analogue Measurement

3. Digital Measurement and Control

2.1 Analogue Voltage Ramp

The voltage ramp circuit is shown in Figure 1.

4 2 THEORY

Figure 2: Analog measurement section added to the voltage ramp circuit

dVout
The voltage ramp dt
is determined by the values of the reference capacitor Cref
and reference resistor Rref . A load resistor RL is added in order to measure the output
of the voltage ramp circuit Vout . The plot of the voltage ramp output Vout waveform is
shown in figures from Section C.1 (lab testing) and Appendix B (Pspice simulation).

2.2 The analogue measurement

The circuit with the analogue measurement section is shown in Figure 2. From the
figure, we can see that the analogue measurement section consists of FETs. The test
capacitor Cmeas (capacitance to be measured) is in between the voltage ramp circuit
and analogue measurement section. At this point, it is important to note that the
voltage ramp output Vout and the voltage Vmeas across Cmeas are not the same.
dVout
For an accurate measurement, a linear voltage ramp or constant dt
is required.
dVout
Therefore, dt
should be independent of temperature and time. For a constant
dVout
dt
, Cref , Rref and Vref should be constant. For this circuit, the capacitance range
dVout
of interest is Cmeas = 10−12 to 10−4 F. Therefore, dt
= 103 , 104 , 105 is appropriate,
with RL not less than 1KΩ. The FETs Q2 to Q6 determine the range of the test
capacitor Cmeas that can be measured using this circuit.
As mentioned previously, Vout and Vmeas are not the same. It means that the
2.3 Digital measurement and control 5

Figure 3: Block diagram of voltage ramp and ADC for the measurement of Vmeas

rate of change of voltage across Cmeas does not remain constant and it changes from
dVout dVmeas
dt
(voltage ramp) to dt
. The value of Vmeas is measured using an analogue to
digital convertor (ADC). Depending on which FETs out of Q2 to Q6 are closed the
microcontroller will determine the capacitance. Figure 3 shows the block diagram of
the voltage ramp circuit and ADC, with the load resistor Rs .
dVmeas
In order to measure Cmeas using Eq. (1), we need the value of dt
. It is hard
dVmeas
to measure dt
directly from the circuit, but it can be determined accurately by
dVout
equating it to dt
. This is achieved by performing a number of iterations using an
ADC. The PIC18F4620 (micro-controller) implements this process and achieves the
target 1% accuracy.

2.3 Digital measurement and control

The digital measurement section consists of a microcontroller with an internal ADC.

The ADC measures Vmeas and feeds the digital input to the micro-controller. The
dVout dVmeas
micro-controller then compares the value of voltages corresponding to dt
and dt
.
Based on this comparison, micro-controller signals the digital to analogue convertor
(DAC) to put a compensating voltage on Cmeas , as illustrated by Figure 4.
The comparison is performed by an iterative process, which is implemented by
a convergence algorithm. The convergence algorithm is summarized in the following
steps:

1. Set some initial value of voltage (Vini ) on Cmeas

2. Measure Vmeas (Vs1 )

6 2 THEORY

Figure 4: Circuit added with Digital measurement and control section

3. Start the iterative cycle

4. Disable DAC, set to 0V 5. Measure Vmeas (Vs2 )

5. If Vs2 <Vs2 , increase Vini and go to step 3; else if Vs1=Vs2 go to step 7.

6. End

By the end, the two values are the same, ie. dV

dt
= dVdtC , and hence the convergence
has been achieved. The waveforms illustrating the convergence algorithm are shown
in Figure 5.

2.4 Integrated Circuit design

The individual sections of the circuit, as explained in Sections 2.1, 2.2 and 2.3 are
combined together in one integrated circuit design. Please see Figure D.BLAH (in Ap-
pendix D) for the assimilated circuit design of the capacitance meter. This schematic
was made using Eagle and was used for further PCB implementation. From the
figure, it can be seen that some additional components have been added. These ad-
 7

Figure 5: Waveforms illustrating the convergence algorithm

ditional components are for enhancing the circuit performance and accuracy. These
components are listed below:

1. Isolating buffers.

2. Capacitors C10 to C11 for stabilizing the power rail.

3. LCD for displaying the digital measured output.

4. Potentiometer R18 for adjusting the contrast of the LCD.

5. Power saving opamp.

3 Implementation
The implementation of the circuit has been divided into 4 stages. Stage I and II verify
the performance of the analogue circuit to generate voltage ramp and output corre-
8 3 IMPLEMENTATION

sponds to the measured capacitance Cmeas . Stage III verifies the functionality of the
digital control and display circuit. Finally Stage IV is the final PCB implementation.
The circuits from Stage I, II and III are built separately, and are not expected to
reach full operational capability until implemented on final PCB.

3.1 Components Selection

Components used in this project are selected based on two criteria, i.e. performance
and availability. Chips in DIP packages are preferred because it is easier to implement
them as compared to the surface mount components. A DIP package also allows the
use of DIP sockets which makes replacing damaged components much easier.

• Opamp This circuit requires opamps with high sensitivity, high slew rate and
low noise to generate a linear voltage ramp and to act as buffer at the output.
These qualities are essential for accurate measurement of capacitance. The
Texas Instruments OPA350 was selected for this project. The one used in this
project is an OPA2350 chip in DIP-8 package. It consists of two opamps in one
chip package. The data sheet is provided in Appendix D1

• DAC A 12 bit DAC with internal reference from Texas Instruments is used.
This is a surface mount chip.

• Microcontroller PIC 18F4620 from Microchip Technology is the selected mi-

crocontroller. It comes in 40pin PDIP package. This chip has 8 bit processing
core with a 10 bit ADC.

• LCD 16 characters x 2 line LCD, generic type

3.2 Pspice simulation

Pspice simulations were performed for stage I and II to verify the functionality of the
analogue circuit before physically implementing the circuit. A 30% duty cycle, using
a pulse generator was used. The schematics for Stage I and II are shown in Appendix
B. For the simulation, the values of Rref = 10K, Cref = 100nF. The values of these
3.3 Circuit Implementation 9

dVout
reference components give dt
= 103 . The load resistor Rs = 10K is used. The
schematic for stage I and II is shown in Figure 10. The simulation results can also be
found in Appendix B.

Figure 6: Stage I and II implementation

3.3 Circuit Implementation

The internal electrical connections in breadboards are usually not very accurate and
degrade the performance of the circuit. So,because of the sensitive nature of this
measurement circuit, we opted to use prototype boards instead of breadboards for
stage I, II and III implementation.
Stage I and II were implemented on one prototype board, as shown in the pho-
tographs that are provided in Appendix A.

3.3.1 Stage I

Voltage is measured across RL to observe the generated voltage ramp waveform from
the integrator circuit. The MOSFET is controlled with a 5V square wave at 50Hz
with a 30% duty cycle.
Three values of dVout dt were tested using different Rref and Cref combination as
summarised in Table 1. In order to see the effect of RL on the linearity of the voltage
ramp, each voltage ramp is tested with three RL values of, 10KΩ, 1KΩ and 250Ω,
10 3 IMPLEMENTATION

dVout
dt
Rref Cref
3
10 10K 100nF
104 10K 10nF
105 10K 1nF
dVout
Table 1: Values of dt
for different combinations of Rr ef and Cr ef

3.3.2 Stage II

Stage II tests the ability of the circuit to measure capacitance of the test capacitor
Cmeas . As it was observed that RL does not have an effect, it is removed from the
circuit and the voltage across Rs is measured.
10pf and 100nF capacitors were tested with Rs = 1M Ω and Rs = 10kΩ with
dVout dVout
dt
= 104 and dt
= 103 respectively.

3.3.3 Stage III

Stage III is built on a separate prototype board. It demonstrates the input/output

capability and the display function of the microcontroller. This circuit consist of a
start button, 0-5V variable voltage input, microcontroller, LED on designated output
pins and a LCD display. The circuit also serve as a debugging board when writing
programs. Stage III of implementation demonstrates the ability of the microcontroller
to control MOSFETS correspond to the selection of measurable capacitance range.
It also demonstrates the ADC and display capability. The microcontroller is pro-
grammed with assembly language in MPLAB. The compiled program is sent to the
microcontroller with Ponyprog through serial port. A photograph of this implemen-
tation is provided in Appendix A.

3.3.4 Stage IV

The first step towards PCB implementation is to design the PCB layout for the circuit
using Eagle software. The Eagle design for the board can be found in Figure 26 in Ap-
pendix D. Due to the complexity of the circuit, it was chosen to design a double-sided
PCB layout. Compactness and proximity of components were other considerations
for this choice. The circuit was designed using the available options for double-sided
 11

PCBs in Eagle. A PCB 7cm×7cm in size is obtained as a result of the Eagle design
process. The PCB design is then sent to PCB manufacturers for fabrication.
In stage IV, components are then soldered onto the received PCB board and the
circuit measures the capacitance and displays it on the LCD screen when the start
button is pressed.

4 Results
4.1 Stage I

From Stage 1 implementation, a linear voltage ramp was obtained. Results were
consistent for the different values of Rref and Cref tested. The effect of the value of
RL was found to be negligible on the circuit. Figures obtained from simulations and
lab testing are shown in Appendix B and C respectively.

4.2 Stage II

Result from the Stage II implementation indicate the analogue circuit was able to
detect and measure the measure capacitance accurately. For a Cmeas = 100nF , Rref =
dVout dVmeas
10KΩ and Cref = 100nF , i.e dt
≈ dt
= 103 and Rs = 10kΩ; Vmeas = 1V was
obtained. Thus, using Eq.( 1), we get,

Vmeas dVout
Cmeas = / (3)
Rs dt

1V
Cmeas = /103 = 100nF (4)
10k

Hence, the measured capacitance corresponds to the tested value, and the capacitance
meter works accurately. Waveforms for the lab testing can be found in Appendix C,
and it can be seen that Figure 23 for Cmeas = 100nF gives a Vmeas = 1V matches to
the simulations from Figure 10 in Appendix B. Lab testing waveforms for the other
test capacitance values are also shown in Appendix C.
12 5 CONCLUSIONS

4.3 Stage III

Testing of the microcontroller, showed that upon feeding a simulated input into the
ADC, a digital display onto the LCD was obtained. In order to test the real input
from the analog circuit, PCB implementation was required.

4.4 Stage IV

Unfortunately, due to a manufacturing error in the received PCB, we were not able
to test the digital implementation of the circuit. The polygon planes (copper plates/
reference ground) in the received PCB were missing and did not correspond with
the Eagle design specifications (Appendix D). One option to fix this problem was
to connect another copper plate manually by drilling holes through the PCB. This
approach is impractical and error prone. Furthermore, with the time limit constraints,
this option was not implemented.

5 Conclusions
This Analogue electronics project focussed on measuring capacitance using the voltage
ramp method. The theory of the analog and digital design of the capacitance meter
circuit has been explained in detail. The implementation consisted of four stages as
described in this report. The results from Stage I and II implementation indicate that
the circuit is capable of detecting and measuring capacitances accurately with values
as low as 10pF. Stage III results also showed a successful implementation of the digital
and control circuitry. The testing results obtained are in an excellent agreement with
the Pspice simulations. Thus, the accurate results obtained verify the validity of the
voltage ramp technique for capacitance measurement.
 13

A Photographs of assembled prototype board

Figure 7: Stage I & II Prototype board implementation

Figure 8: Stage III Prototype board implementation

14 B PSPICE IMPLEMENTATION

B Pspice Implementation

Figure 9: Stage I implementation

Figure 10: Stage II implementation

 15

C Lab Testing
C.1 Stage I

dVout
Figure 11: dt
= 103 , Rref = 10kΩ, Cref = 100nF , RL = 0Ω

dVout
Figure 12: dt
= 104 , Rref = 10kΩ, Cref = 10nF , RL = 0Ω
16 C LAB TESTING

dVout
Figure 13: dt
= 105 , Rref = 10kΩ, Cref = 1nF , RL = 0Ω

dVout
Figure 14: dt
= 103 , Rref = 10kΩ, Cref = 100nF , RL = 10kΩ

dVout
Figure 15: dt
= 104 , Rref = 10kΩ, Cref = 10nF , RL = 10kΩ
C.1 Stage I 17

dVout
Figure 16: dt
= 105 , Rref = 10kΩ, Cref = 1nF , RL = 10kΩ

dVout
Figure 17: dt
= 103 , Rref = 10kΩ, Cref = 100nF , RL = 1kΩ

dVout
Figure 18: dt
= 104 , Rref = 10kΩ, Cref = 10nF , RL = 1kΩ
18 C LAB TESTING

dVout
Figure 19: dt
= 105 , Rref = 10kΩ, Cref = 1nF , RL = 1kΩ

dVout
Figure 20: dt
= 103 , Rref = 10kΩ, Cref = 100nF , RL = 250Ω

dVout
Figure 21: dt
= 104 , Rref = 10kΩ, Cref = 10nF , RL = 1kΩ
C.2 Stage II 19

C.2 Stage II
20 C LAB TESTING

dVout
Figure 22: dt
= 105 , Rref = 10kΩ, Cref = 1nF , RL = 1kΩ

dVout
Figure 23: dt
= 103 , Rref = 10kΩ, Cref = 100nF , RL = 0Ω, Rs = 10kΩ, Ct =
100nF
 21

dVout
Figure 24: dt
= 104 , Rref = 10kΩ, Cref = 10nF , RL = 0Ω, Rs = 1M Ω, Ct = 10pF

D EAGLE PCB Layout Design

22 D EAGLE PCB LAYOUT DESIGN

Figure 25: Eagle Schematic

 23

Figure 26: Eagle Board

24 E DATA SHEETS

E Data Sheets
The data sheet of the Opamps, microcontroller and DAC are attached on the following
pages.