INTRODUCTION

In a dynamic CMOS inverter the output is taken across a capacitor known as load capacitance. The
load capacitance is defined as the gate capacitance of the driven gate plus the capacitance of the
interconnect plus the drain-source capacitance of the driving device.The node capacitance has to
be charged or discharged each time a transition occurs[1].

Figure 1: Dynamic CMOS inverter configuration[1].

The drain current discharges through the capacitor according to the equation 1 which gives the
capacitance required to allow the switching.
𝛥𝑉0
ID = - CL (1)
𝛥𝑡

Arranging equation 1 to obtain the load capacitance

𝛥𝑡
CL = -ID 𝛥𝑉 (2)
0

EXPERIMENTS
Design a CMOS inverter loaded by another CMOS. What should the command for the
equation part be?
 Figure 2: Dynamic CMOS inverter design from microwind2
In figure 2, it can be seen that a CMOS inverter is loaded by another CMOS inverter obtained
using the equation for the command [out = in].
Simulate the design using a step input rise and fall time waveform (i.e. tr/f=0.01ns), and
make tlow/high=2ns.

Figure 3: Assigning a clock to the dynamic inverter.

In figure 3, it can be seen that the clock was added to the dynamic inverter with a step input rise
and fall time at 0.01ns with time low and time high at 2ns respectively. The design was
simulated without fatal error.

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Draw the voltage transfer function.

Figure 4: Voltage transfer function for a dynamic inverter

In figure 4, it can be seen from the voltage transfer function that for low input voltages give high
outputs and high inputs voltages give low output voltages at the output.
Draw time vs. output current and voltage.

Figure 5; Time vs Output Current and Voltage waveforms

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In figure 5, it can be seen that there is a variation of time with respect to the current for a
dynamic inverter with a maximum current at 0.920mA and a maximum voltage of 5v.
Calculate the capacitance of the output node of the first inverter.
𝛥𝐼×𝛥𝑡
Using the formula CL = 𝛥𝑉
where CL is capacitance
𝛥𝑉change in voltage
ΔI change in current
Δt change in time
From figure 6 Δt = 0.157ns
𝛥𝑉 = (4.227V-1.545V
ΔI = 0.920mA

𝛥𝐼×𝛥𝑡 0.920×10−3 𝐴×0.159×10−9 𝑆

Then for CL = 𝛥𝑉
= (4.227𝑉−1.545𝑉)

CL = 55fF

Figure 6: Capacitance approximation values for dynamic inverter.

In figure 7, it can be seen that the system

capacitance value for the dynamic inverter is
63.93Ff which is near the calculated value of
55fF using the approximated values in figure
6.

Figure 7: System capacitance value for a dynamic inverter

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Measure the delay time and calculate the maximum frequency of operation.

Figure 8: Propagation delay graph for dynamic inverter

In figure 8, it can be seen that there are two propagation delay times for a dynamic inverter. That
is the propagation delay from high to low (tpHL = 159ps ) and the propagation delay from low to
high (tpLH = 141ps). Considering the highest value to be the propagation delay for the entire
CMOS inverter therefore the propagation delay is 159ps.
Maximum frequency of operation
In figure 8, it can be seen that there is equal time of 0.7ns for the rising time(tr) and falling time
(tf)
1 1
Maximum Frequency = 𝑡 ≅ (3)
𝑟 +𝑡𝑓 𝑡𝑟 ×𝑓𝑎𝑐𝑡𝑜𝑟

1
=(0.7×10−9 )×2 where the factor lies between 2 to 3

= 714MHz
Calculate the power consumption. Use a linear approximation at the current waveform.

Using figure 9 below, Power consumption = Pavg

Pavg = Vavg × Iavg (4)
𝑇
= Vdd × ∫0 𝐼 𝑑𝑡
𝑙𝑒𝑛𝑔𝑡ℎ×𝑤𝑖𝑑𝑡ℎ
= Vdd × Using the approximation method
𝛥𝑡
5𝑣 ×1.293 × 10−3 𝐴 ×0.254 ×10−9 𝑆
= 2.120×10−9 𝑆
= 0.77mW

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 = 770µW

Figure 9: Current waveform for the approximation method

Repeat steps 2 to 6 for a single inverter and compare the results to the results obtained using
the inverter chain.

Figure 10: Assigning a clock to the single inverter

In figure 10, it can be seen that the clock was added for the single inverter with a step input rise
and fall time at 0.01ns with time low and time high at 2ns respectively. The design was simulated
without fatal error.

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Voltage transfer function for single inverter

Figure 11: Voltage transfer function for a single inverter

In figure 11, it can be seen from the voltage transfer function of a single inverter that for low input
voltages give high outputs and high inputs voltages give low output voltages at the output.

Figure 12; Time vs Output Current and Voltage waveforms for a single inverter

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In figure 12, it can be seen that there is a variation of time with respect to the current for a single
inverter with a maximum current at 2.00mA and a maximum voltage of 5v.
Calculating the capacitance for a single inverter
𝛥𝐼×𝛥𝑡
Using the formula CL = 𝛥𝑉
where CL is capacitance
𝛥𝑉change in voltage
ΔI change in current
Δt change in time
From figure 13, Δt = 0.140ns
𝛥𝑉 = 5V
ΔI = 1.293mA

𝛥𝐼×𝛥𝑡 1.293×10−3 𝐴×0.140×10−9 𝑆

Then for CL = 𝛥𝑉
= (5𝑉)

CL = 36fF

Figure 13: Capacitance approximation values for a single inverter.

Figure 14: System capacitance value for a single inverter

In figure 14, it can be seen that the system capacitance value for a single inverter is 34.94fF
which is near the calculated value of 36fF using the approximated values in figure 13.

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Propagation delay for a single inverter and maximum frequency

Figure 15: Propagation delay graph for a single inverter

In figure 15, it can be seen that there are two propagation delay times for a single inverter. That is
the propagation delay from high to low (tpHL = 111ps ) and the propagation delay from low to
high (tpLH = 99ps). Considering the highest value to be the propagation delay for the entire CMOS
inverter therefore the propagation delay is 111ps.
Maximum frequency of operation
In figure 15, it can be seen that there is equal time of 0.4ns for the rising time(tr) and falling time
(tf)
1 1
Maximum Frequency = 𝑡 ≅
𝑟 +𝑡𝑓 𝑡𝑟 ×𝑓𝑎𝑐𝑡𝑜𝑟

1
=(0.4×10−9 )×2 where the factor lies between 2 to 3

= 1.25GHz
Calculate the power consumption using approximation at the current waveform
Using figure 12; Pavg = Vavg × Iavg
𝑇
= Vdd × ∫0 𝐼 𝑑𝑡
(2×10−3 𝐴×0.123×10−9 𝑆)
= 5V× A ( Current obtained by approximation )
(4.1×10−9 𝑆)

= 0.3mW
= 300µW

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Design a CMOS inverter loaded with 6 inverters.

Figure 16: CMOS inverter loaded with 6 inverters

In figure 16, it can be seen that a single inverter can be loaded with more 6 inverters using the
microwind2 simulation software.
Voltage transfer function for CMOS inverter loaded with 6 inverters

Figure 17: Voltage transfer function for CMOS inverter loaded with 6 inverters
In figure 17, it can be seen from the voltage transfer function for CMOS inverter loaded with 6
inverters that for low input voltages give high outputs and high inputs voltages give low output
voltages at the output with a power at 71v/v

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Voltage and Current waveforms against time for CMOS inverter loaded with 6 inverters

Figure 18: Voltage and Current waveforms against time for CMOS inverter loaded with 6 inverters
In figure 18, it can be seen that there is a variation of time with respect to the current and voltage
for a CMOS inverter loaded with 6 inverters with a maximum current at 3.65mA and a maximum
voltage of 5v.
System capacitance value for a CMOS inverter loaded with 6 inverters

Figure 19: System capacitance value for a CMOS inverter loaded with 6 inverters
In figure 19, it can be seen that the system capacitance value for a CMOS inverter loaded with 6
inverters is 280.71fF which is a very high value compared to when using a single inverter and a
dynamic inverter.

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CONCLUSION

It has been discovered from the experiment that the more the number of inverters in a circuit, the
slower the circuit become, for example using a single inverter the delay was 111ps. while the
dynamic inverter had a propagation delay of 159ps.
The capacitance of CMOS circuit increases with the increase in the number of inverters in the
circuit. For single inverter (36fF), dynamic inverter (55fF) and CMOS inverter loaded with six
inverters (280.71fF). However there is a small variation between the calculated capacitance values
and the system values due to the approximation method used.
The maximum frequency of operation also increases with the reduced number of the inverters in a
given circuit. Single inverter circuit (1.25GHz) and the dynamic inverter circuit (714MHz).
Power consumption also increases with the increasing number of inverters in a given CMOS
circuit.

REFERENCES
[1] S. Andreas, Class Lecture, “Introduction to CMOS VLSI Design.” School of Electronic and
Electrical Engineering, Technological University of Dublin.

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