UNIT-III

SEQUENTIAL LOGIC CIRCUITS

Part-B
1. With neat diagrams discuss about Static Latches and registers.(16m)
2. With neat diagrams discuss about dynamic latches and registers.(16m)
3. Explain about the pipelining concepts used in sequential circuits.(16m)
4. Explain about the various approaches to optimize the pipelining in sequential circuits.(8m)
5. Discuss about the timing issues in sequential circuits.(8m)
6. Discuss about the clock strategy and clock distribution in sequential circuits.(8m)
7. Describe in detail about memory architectures and its building blocks.(16m)

UNIT –IV
DESIGNING ARITHMETIC BULIDING BLOCKS
Part-B

1. Discuss the data paths in digital processor architectures. (6m)

2. Describe ripple carry adder and derive the worst case delay with example.(16m)
3. Discuss about array multiplier/carry save multiplier/booth multiplier/Wallace Tree
multiplier(16m)
4. Describe the Carry Look ahead adder/Carry Bypass and Carry select adder.(16m)
5. Discuss about the Speed and area trade off.(6m)
6. Discuss about Logarithmic Shifter and Barrel Shifter (12m)

Unit-V
IMPLEMENTATION STRATEGIES

Part-B
1. Explain about ASIC design flow.(10m)
2. Explain the types of ASIC or Discuss about Full Custom and Semi Custom ASIC.(16m)
3. Explain about the FPGA building block architectures - XC4000.(16m)
4. Discuss about the cell libraries used in ASIC design.(8)
5. Discuss about the Interconnect routing procedures and its types in FPGA.(16m)