Design Guidelines for LTCC 2007/01

LTCC
Low Temperature Co-fired Ceramic

Design Rule

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 Design Guidelines for LTCC 2007/01

*This guideline is applicable to LTCC substrates manufactured at Hirai Seimitsu Kogyo Corporation.
*This guideline provides you the general information. Please feel free to contact us for the detail or
further information. We will be able to provide you further information depending on your individual request.
*All figures in this guideline indicate minimum values unless specified.

1. PROCESS
1-1. CAD System
Data Format
Gerber、DXF、AutoCAD（AUTO DESK）

1-2. MANUFACTURING PROCESS

· GREEN SHEET

· VIA HOLE FORMATION

· VIA FILL

· SCREEN PRINTING

· CASTELLATION, CAVITY FORMATION

· LAMINATION

· SCORE LINE = HALF CUT

· SINTERING

· PLATING

· SCRIBE LINE

· INSPECTION

· SHIPMENT

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 Design Guidelines for LTCC 2007/01

2. MATERIAL PROPERTY

2-1. GLASS CERAMIC MATERIAL

MATERIAL GCS71 GCS60 GCS170 GCS50
Coefficient of Thermal Expansion
5.5 5.5 6.3 -
[10-6/K]
Thermal
[W/m ・K] 3.2 2.8 - -
conductivity

Specific Heat [J/g ・K] 0.66 - - -

Young’s Modulus [GPa] 65 50 - -

Bending Strength [MPa] 280 240 200 -

@1MHz, R.T. 7.1 6.0 18.3 5.0

Dielectric Constant
@10 GHz, R.T. 7.1 6.0 18.3 5.0

@1MHz, R.T. 0.003 0.001 0.003 0.001

Dielectric Loss
@10 GHz, R.T. 0.005 0.001 0.006 0.001

Volume Resistivity [Ω ・cm] >1014 >1014 >1014 >1014

※Numbers shown above is not absolute and guaranteed value.

※“GCS170” and ”GCS50” is the materials to be embedded in “GCS71”.

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2-2. CONDUCTOR

Co-fire Electroless Plating *2

Conductor Type
Ag Ag/Pd Au*3

Volume Resistance [μΩ cm] 3.0 5.0 3.0

0.50
Conductor Thickness [μm] 15±5 *1 15±5 *1 ≧0.10
±0.20
Bondability × × Ο ◎

Resistance to Solder × Ο ◎ ◎

Solderability × × ◎ ◎

*1: Above value is based on standard Ag plating thickness. Consultation is individually required.
*2: Electroless Plating = Ni/Au
*3: Characteristics of plating are qualitative evaluation.

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3. Basic Outline

3-1. Substrate Size

Item Std Adv.

a Basic Outline [mm] 60 ~120

b Border Width [mm] 5.0 3.0

Dimensional Accuray [%] ±0.5 ±0.2

Warpage [%] ±0.3 ±0.1

*Border width b is subject to change. It depends on the substrate thickness.

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3-2. Cavity Size

c d
e
f
g

Item Std Adv.

c Substrate edge to Cavity [μm] 500 300

d Cavity Step Width [μm] 500 300

e Cavity depth [μm] 160~1000 80

f Layer Thickness [μm] 80 40
g Base Thickness [μm] 400 160
Thickness accuracy [%] ±10.0 ±5.0

Cavity size accuracy [%] ±2.0 ±1.0

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4. Design Rule
4-1. Wire Bonding Pad

B
A
a b

Item Std Adv.

a Pad Width [μm] 150 100

b Pad Space [μm] 100 50

c Pad to Cavity [μm] 100 0

A Pad Pitch accuracy [%] ±0.5 ±0.2

Pad Pitch accuracy

B (Outer to outer)
[%] ±0.6 ±0.3

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4-2. Flip Chip Pad

a b

Flip Chip Pad

Via

Item Std Adv.

a Pad Diameter [μm] 150 100

Pad Size Accuracy [%] ±20 ±10

b Pad Pitch [μm] 300 200

Pad Pitch Accuracy [%] ±0.5 ±0.2

c Via Diameter [μm] 100 80

Distance Between Pads
d (Right end to Left end)
[%] ±0.6 ±0.3

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4-3. SMD Pad

a b c

Item Std

a Pad Size [μm] 200

Pad Size Accuracy [%] ±10

b Pad Spacing [μm] 200

c Pad edge to Substrate edge [μm] 200

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4-4. Overgraze = Over Coat Glass (O.C.G.)

a b c d

Over Coat Glass

Item Std

a Pad edge to O.C.G edge [μm] 100

b Pattern width [μm] 150

c Spacing (Slit) [μm] 150

d Substrate edge to O.C.G [μm] 200

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4-5. Exposed Signal Conductor

b
a c d f
Cavity

i
e
k l
Castellation

Item Std Adv.

a Via Hole Diameter [μm] 100 80

b Via Hole Cover Diameter [μm] 150 100
c Via Hole Pitch [μm] 300 200
d Via Cover to Line [μm] 100 70
e Via Cover to Substrate Edge [μm] 400 300

f Via Cover to Cavity Edge [μm] 200 100

g Line Width [μm] 100 50
h Line Spacing [μm] 100 50
i Line to Substrate Edge [μm] 300 200
j Line to Cavity Edge [μm] 200 100
k Castellation to Line [μm] 300 200
l Castellation to Via Cover [μm] 300 200

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4-6. Buried Signal Conductor

b
a c d f
Cavity

i
e
k l
Castellation

Item Std Adv.

a Via Hole Diameter [μm] 100 80

b Via Hole Cover [μm] 150 100

c Via Hole Pitch [μm] 300 200
d Via Cover to Line [μm] 100 70

e Via Cover to Substrate Edge [μm] 400 300

f Via Cover to Cavity Edge [μm] 200 100

g Line Width [μm] 100 50
h Line Spacing [μm] 100 50
i Line to Substrate Edge [μm] 300 200
j Line to Cavity Edge [μm] 200 100
k Castellation to Line [μm] 300 200
l Castellation to Via Cover [μm] 300 200

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4-7. Ground Plane / Power

b c f
a c d e

h
Cavity
g

Item Std Adv.

a Via Hole Diameter [μm] 100 80

b Via Hole Cover Diameter [μm] 150 100

With via in upper layer [μm] 200 150

c Isolation Gap
Without via in upper layer [μm] 150 100

d Solid Plane [μm] 100 80

e Substrate Edge to Ground Plane [μm] 300 200

f Substrate Edge to Via Cover [μm] 300 200

g Cavity Edge to Ground Plane [μm] 300 200

h Cavity Edge to Via Cover [μm] 300 200

4-8. Castellation

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c d

a
b

Item Std Adv.

a Castellation Via [μm] 400 250

b Conductor Diameter [μm] a + 300 a + 200

c Space [μm] 600 300

D Castellation to Ground Plane [μm] 200 150

e Depth [μm] <a <a

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5. Embedded Components
5-1. Inductor
e
a b b d

Item Std Adv.

a Line Width [μm] 100 50

b Line Spacing [μm] 100 50

c Line to Substrate Edge [μm] 300 200

d Via Hole Diameter [μm] 100 80

e Via Hole Cover Diameter [μm] 150 100

f Via Cover to Substrate Edge [μm] 300 200

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5-2. Capacitor

a b

Item Std

a Capacitor Size [mm] ~ 5.0

b Spacing [mm] >a

c Distance among each Layers [μm] 40 ~

*Maximun Conductor Coverage is 50% for Substrate Area.

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5-3. Resistors
Ohms per Square
Ink
(Ω/□)
R001 50
R002 100
R003 1k
R004 10k
R005 100k

＊Manufacturing tolerance : Std. ±30% Adv. ±20%

Typical Layout a

b c

f e d Resistor Barrier Conductor

Item Maximum Minimum

a Resistor Length [mm] 2.0 0.3

b Resistor Width [mm] 2.0 0.3
c Barrier Width [mm] b + 0.2
D Overlap of R and B [μm] 100
Spacing-Resistor to
E Conductor
[μm] 100

F Overlap of B and P [μm] 100

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6. Score line
6-1. Half Cut Line
a
b

Type A（One Side） Type B(Both Side)

c c
d
d c
e

Item Std Adv.

a Length [mm] 60 ~ 120

b Width [mm] t×3 t×2

Width Accuracy [%] ±0.5 ±0.2

Burr after Braking *1 [mm] t × 03

c Depth *2 [mm] 0.2 ~ 0.6 0.1 ~ 1.0

d Remainder *2 [mm] t × 0.5

e Offset [μm] 80

*1.Figures depend on how you break. Numbers shown above is only for reference.
*2. We have priority over Remainder(d) than Depth(c)

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6-2. Scribe Line

a
b

Item Std Adv.

A Length [mm] 60 ~ 120

B Width [mm] t×4 t×3

Width Accuracy [%] ±0.5 ±0.2

Burr after Breaking *1 [mm] t × 0.4

*1. Figures depend on how you break. Numbers shown above is only for reference.

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