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VLSI
EC 304
ES . I N
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AdarshTKS
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EC 304 VLSI ADARSH K S

Module Aims
 IC Fabrication Technology,
 CMOS IC Fabrication Sequence,
 CMOS inverters,
 Design rules,
 Static CMOS Design,
ES . I N
 Dynamic CMOS circuits,
N O T


KTU
Pass transistor,
Read Only Memory,
 Random Access Memory,
 Sense amplifiers,
 Adders, multipliers,
 Testing of VLSI circuits

Learning Outcomes
• The students will be able to design and

analyse various MOSFET and CMOS logic
circuits S . I N
T U N OTE
K

Reading List
1. John P Uyemura, Introduction to VLSI Circuits
and Systems, Wiley India, 2006
2. S.M. SZE, VLSI Technology, 2/e, Indian Edition,
McGraw-Hill,2003 OTES.IN
K T U N

Why VLSI?
• Integration improves the design
– Lower parasitics = higher speed
– Lower power consumption
– Physically smaller S . I N
U N O TE
• KT manufacturing cost -
Integration reduces
(almost) no manual assembly

Module 1
Fabrication Technology
• Oxidation
•Photolithography
ES . I N
•Etching
N O T
•Ion Implantation
•Diffusion KTU
•Deposition

VLSI Applications
• VLSI is an implementation technology for electronic circuitry - analogue or
digital
• It is concerned with forming a pattern of interconnected switches and
gates on the surface of a crystal of semiconductor
• Microprocessors
ES . I N
– personal computers
N O T
– microcontrollersKTU
• Memory - DRAM / SRAM
• Special Purpose Processors - ASICS (CD players, DSP applications)
• Optical Switches
• Has made highly sophisticated control systems mass-producable and
therefore cheap

Moore’s Law
• Gordon Moore: co-founder of Intel
• Predicted that the number of transistors per
chip would grow exponentially (double every
18 months) E S . I N
U N O T
K T
• Exponential improvement in technology is a
natural trend:
– e.g. Steam Engines - Dynamo - Automobile

The Cost of Fabrication
• Current cost $2 - 3 billion

• Typical fab line occupies 1 city block, employees a
few hundred employees
• Most profitable period is first
E 18
S . I N
months to 2
years N O T
KTU
• For large volume IC’s packaging and testing is
largest cost
• For low volume IC’s, design costs may swamp
manufacturing costs

Technology Background
ES . I N
N O T
KTU

What is a Silicon Chip?
• A pattern of interconnected switches and gates on the surface of a crystal
of semiconductor (typically Si)
• These switches and gates are made of
– areas of n-type silicon
– areas of p-type silicon
areas of insulator ES . I N
–
U N O T
–
•
T
lines of conductor (interconnects) joining areas together
K
Aluminium, Copper, Titanium, Molybdenum, polysilicon, tungsten
• The geometryof these areas is known as the layout of the chip
• Connections from the chip to the outside world are made around the edge
of the chip to facilitate connections to other devices

Switches
• Digital equipment is largely composed of switches
• Switches can be built from many technologies
– relays (from which the earliest computers were built)
– thermionic valves
– transistors
S . I N
E the following:
• The perfect digital switchN
U O T
would have
– switch instantly K T
– use no power
– have an infinite resistance when off and zero resistance when on
• Real switches are not like this!

Semiconductors and Doping
• Adding trace amounts of certain materials to semiconductors
alters the crystal structure and can change their electrical
properties
– in particular it can change the number of free electrons or holes
• N-Type
– semiconductor has free electrons
– dopant is (typically) phosphorus, arsenic, antimony
• P-Type E S . I N
semiconductor has freeU N O
holes
T
–
– T
K boron, indium, gallium
dopant is (typically)
• Dopants are usually implanted into the semiconductor using
Implant Technology, followed by thermal process to diffuse the
dopants

IC Technology
• Speed / Power performance of available
technologies
• The microelectronics evolution
E S . I N
• SIA Roadmap N O T
K T U
• Semiconductor Manufacturers 2001 Ranking

Metal-oxide-semiconductor (MOS) and
related VLSI technology
• pMOS
• nMOS . I N
O T ES
• CMOS KTU N
• BiCMOS
• GaAs

Basic MOS Transistors
• Minimum line width
• Transistor cross section
• Charge inversion channel
E S . I N
• Source connected U to
N O T
substrate
K T
• Enhancement vs Depletion mode devices
• pMOS are 2.5 time slower than nMOS due to
electron and hole mobilities

• Silicon of extremely high purity
– chemically purified then grown into large crystals
• Wafers
– crystals are sliced into wafers
wafer diameter is currently 150mm, 200mm, 300mm
–
ES . I N
– wafer thickness <1mm
N O T
–
K TU
surface is polished to optical smoothness
• Wafer is then ready for processing
• Each wafer will yield many chips
– chip die size varies from about 5mmx5mm to 15mmx15mm
– A whole wafer is processed at a time

• Different parts of each die will be made P-type
or N-type (small amount of other atoms
intentionally introduced - doping -implant)
• Interconnections are OmadeE S . I
with Nmetal
U N T
T
K is typically SiO2. SiN is also
• Insulation used
used. New materials being investigated (low-k
dielectrics)

• nMOS Fabrication
• CMOS Fabrication
– p-well process
– n-well process ES . I N
U N O T
K T
– twin-tub process

• All the devices on the wafer are made at the same time
• After the circuitry has been placed on the chip
– the chip is overglassed (with a passivation layer) to protect it
– only those areas which connect to the outside world will be left uncovered
(the pads)
The wafer finally passes to a test station E S . I N
•
U N O T
–
chip K T
test probes send test signal patterns to the chip and monitor the output of the
• The yield of a process is the percentage of die which pass this testing
• The wafer is then scribed and separated up into the individual chips. These
are then packaged
• Chips are ‘binned’ according to their performance

CMOS Technology
• First proposed in the 1960s. Was not seriously considered until the severe
limitations in power density and dissipation occurred in NMOS circuits
• Now the dominant technology in IC manufacturing
• Employs both pMOS and nMOS transistors to form logic elements
The advantage of CMOS is that its logic elements draw significant current
•
ES . I N
N O T
only during the transition from one state to another and very little current
•
KTU
between transitions - hence power is conserved.
In the case of an inverter, in either logic state one of the transistors is off.
Since the transistors are in series, (~ no) current flows.
• See twin-well cross sections


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