A Simple Vending Machine: VLSI Design and Embedded System (VDES) - 2015

Summer Training programme
on
VLSI Design and Embedded System (VDES) - 2015
A SIMPLE VENDING MACHINE
Submitted by
MAYANK PRATAP SINGH
1
TABLE OF CONTENTS
No Content Pg. No
1 Acknowledgement 3
2 Introduction 4
3 History 4
4 EDA TOOL Used: XILINX ISE 8.2i 5
5 Theory 5
6 FSM Design Steps 6
7 State Diagram 6
8 Design Description/ Specifications 6
9 State table 7
10 Verilog Code 8
11 RTL Schematic 12
12 Output Waveform 13
13 Present scenario in India 14
2
ACKNOWLEDGEMENT
It gives me a great sense of pleasure to present the mini project of VLSI Design lab undertaken
during summer training programme on VLSI Design and Embedded System (VDES)-2015 at
Cetpa Infotech Lucknow. I owe special debt of gratitude to Dr. Haranth Kar (Head of the
Electronics and Communication Department), Dr. Arvind Kumar, Dr. Manish Tiwari, Dr. Sanjeev
Rai, Dr. Santosh Kumar Gupta, for their constant support and guidance throughout the course of
our work. Their sincerity, thoroughness and perseverance have been a constant source of
inspiration for us.
I also take the opportunity to acknowledge the contribution of VDES Lab Trainer Team, CETPA
Infotech Lucknow, for their full support and assistance during the development of this project.
MAYANK PRATAP SINGH
3
INTRODUCTION
A vending machine is a machine that dispenses items such as snacks, beverages, alcohol, cigarettes,
lottery tickets to customers automatically, after the customer inserts currency or credit into the
machine. The first modern vending machines were developed in England in the early 20th century
and dispensed postcards. The first modern vending machines were developed in England in the early
20th century and dispensed postcards.
Fig.no.01--A SIMPLE VENDING MACHINE
4
HISTORY
The earliest known reference to a vending machine is in the work of Hero of Alexandria, a first-
century AD Greek engineer and mathematician. His machine accepted a coin and then dispensed
holy water.[1] When the coin was deposited, it fell upon a pan attached to a lever. The lever
opened a valve which let some water flow out. The pan continued to tilt with the weight of the
coin until it fell off, at which point a counterweight snapped the lever up and turned off the
valve.
The first modern coin-operated vending machines were
introduced in London, England in the early 1880s, dispensing postcards. The machine was
invented by Percival Everitt in 1883 and soon became a widespread feature at railway stations
and post offices, dispensing envelopes, postcards, and notepaper. The Sweetmeat Automatic
Delivery Company was founded in 1887 in England as the first company to deal primarily with
the installation and maintenance of vending machines.
5
EDA TOOL USED: XILINX ISE 8.2i
Xilinx, Inc. is an American technology company, primarily a supplier of programmable logic

devices. It is known for inventing the field programmable gate array (FPGA) and as the first
semiconductor company with a fabless manufacturing model. Founded in Silicon Valley in 1984,
the company is headquartered in San Jose, California, with additional offices in Longmont,
Colorado; Dublin, Ireland; Singapore; Hyderabad, India; Beijing, China; Shanghai, China;
Brisbane, Australia and Tokyo, Japan. Major FPGA product families include Virtex (high-
performance), Kintex (mid-range) and Artix (low-cost), and the retired Spartan (low-cost) series.
Major computer software includes Xilinx ise and vivado design suit.
THEORY
For implementing a simple vending machine, the concept of finite state machnism (FSM) can be
used. There are two types of state machines:
1. MOORE: In a moore machine the output state is totally dependent on the present
state. The diagram shows the information.
Fig. no. 02--MOORE FSM
2. MEALY: In a mealy machine the output depends on the input as well as the present
state.
6
Fig. no. 03--MEALY FSM
FSM DESIGN STEPS
1. Obtain the specifications of the desired circuit

2. Derive the states of the machine and develop a state diagram:
(a) Should show all possible states.

(b) Provide the conditions for which the circuit moves from one state to the next.
3.Develop the state table from the state diagram.
4.Decide on the number of state variables needed to represent all states.
(a)Minimize the number of states if possible.
5. Implement the design.
7
STATE DIAGRAM
Fig. no.04--STATE DIAGRAM OF A SIMPLE VENDING MACHINE
8
Design Description/Specifications
• Vending Machine INPUTS
• The machine takes coins

• C1: 5 cents
• C2:10cents
• C3:15cents
• The machine can dispense: v1:15 cents
v2:20cents
v3:25cents
• The machine has a Coin Return button (Cr)

• Only one input may be active at a time
• A product can be dispensed in one clock cycle
• If more than 25 cents is inserted, the money is automatically returned
• If no inputs are active, the state machine stays in the current states
OUTPUTS:
• cro: Coin Return Out (all money in the machine):cr0
• 1st item dispend:v10
• 2nd item dispend:v20
• 3rd item dispend:v30
• Coin returned:C10, c20 ,c30
9
STATE TABLE
TABLE NO.-01
10
VERILOG CODE
module vendmach(clk,rst, cr,c1,c2,c3,v1,v2,v3, s, cro,c1o,c2o,c3o,v1o,v2o,v3o);

input clk,rst;
input cr,c1,c2,c3,v1,v2,v3;
output reg[3:0] s;
output reg cro,c1o,c2o,c3o,v1o,v2o,v3o;
reg [3:0] ns;
initial begin s=0;
ns=0;
cro=0;
c1o=0; c2o=0;c3o=0;v1o=0;v2o=0;v3o=0; end
parameter [3:0]A=4'b0000;
parameter [3:0]B=4'b0001;
parameter [3:0]C=4'b0010;
parameter [3:0]D=4'b0011;
parameter [3:0]E=4'b0100;
parameter [3:0]F=4'b0101;
parameter [3:0]G=4'b0110;
parameter [3:0]H=4'b0111;
parameter [3:0]I=4'b1000;
parameter [3:0]J=4'b1001;
always @(posedge clk)

begin
if(rst)
begin
s<=A;
if(s!=A)
cro<=1;
end
else
begin
case({s})
A: if(cr==0 && c1==0 && c2==0 && c3==0 && v1==0 && v2==0 && v3==0)
begin s<=A;
cro<=0;c1o<=0; c2o<=0;c3o<=0;v1o<=0;v2o<=0;v3o<=0;end
else if(cr==0 && c1==1 && c2==0 && c3==0 && v1==0 && v2==0 && v3==0)
begin s<=B;
11
else if(cr==1 && c1==0 && c2==0 && c3==0 && v1==0 && v2==0 && v3==0)
begin s<=C;
else if(cr==0 && c1==0 && c2==1 && c3==0 && v1==0 && v2==0 && v3==0)
begin s<=D;
else if(cr==0 && c1==0 && c2==0 && c3==1 && v1==0 && v2==0 && v3==0)
begin s<=G;
<=0;c1o<=0; c2o<=0;c3o<=0;v1o<=0;v2o<=0;v3o<=0;end
B: if(cr==0 && c1==0 && c2==0 && c3==0 && v1==0 && v2==0 && v3==0)
begin s<=B;
cro<=0;c1o<=0; c2o<=0;c3o<=0;v1o<=0;v2o<=0;v3o<=0; end
else if(cr==1 && c1==0 && c2==0 && c3==0 && v1==0 && v2==0 && v3==0)
begin s<=C;
if(cr==0 && c1==1 && c2==0 && c3==0 && v1==0 && v2==0 && v3==0)
begin s<=D;
if(cr==0 && c1==0 && c2==1 && c3==0 && v1==0 && v2==0 && v3==0)
begin s<=E;
else if(cr==0 && c1==0 && c2==0 && c3==1 && v1==0 && v2==0 && v3==0)
begin s<=B;
C: begin s<=A;cro<=1; c1o<=0; c2o<=0; c3o<=0; v1o<=0; v2o<=0; v3o<=0; end

D: if(cr==0 && c1==0 && c2==0 && c3==0 && v1==0 && v2==0 && v3==0)
begin s<=D;
else if(cr==1 && c1==0 && c2==0 && c3==0 && v1==0 && v2==0 && v3==0)
begin s<=C;
else if(cr==0 && c1==1 && c2==0 && c3==0 && v1==0 && v2==0 && v3==0)
begin s<=E;
else if(cr==0 && c1==0 && c2==1 && c3==0 && v1==0 && v2==0 && v3==0)
begin s<=F;
else if(cr==0 && c1==0 && c2==0 && c3==1 && v1==0 && v2==0 && v3==0)
begin s<=D;
12
E: if(cr==0 && c1==0 && c2==0 && c3==0 && v1==0 && v2==0 && v3==0)
begin s<=E;
else if(cr==1 && c1==0 && c2==0 && c3==0 && v1==0 && v2==0 && v3==0)
begin s<=C;
if(cr==0 && c1==1 && c2==0 && c3==0 && v1==0 && v2==0 && v3==0)
begin s<=F;
else if(cr==0 && c1==0 && c2==1 && c3==0 && v1==0 && v2==0 && v3==0)
begin s<=G;
else if(cr==0 && c1==0 && c2==0 && c3==1 && v1==0 && v2==0 && v3==0)
begin s<=E;
else if(cr==0 && c1==0 && c2==0 && c3==0 && v1==1 && v2==0 && v3==0)
begin s<=I;
F: if(cr==0 && c1==0 && c2==0 && c3==0 && v1==0 && v2==0 && v3==0)
begin s<=F;
else if(cr==1 && c1==0 && c2==0 && c3==0 && v1==0 && v2==0 && v3==0)
begin s<=C;
else if(cr==0 && c1==1 && c2==0 && c3==0 && v1==0 && v2==0 && v3==0)
begin s<=G;
else if(cr==0 && c1==0 && c2==1 && c3==0 && v1==0 && v2==0 && v3==0)
begin s<=F;
else if(cr==0 && c1==0 && c2==0 && c3==1 && v1==0 && v2==0 && v3==0)
begin s<=F;
else if(cr==0 && c1==0 && c2==0 && c3==0 && v1==1 && v2==0 && v3==0)
begin s<=I;
else if(cr==0 && c1==0 && c2==0 && c3==0 && v1==0 && v2==1 && v3==0)
begin s<=J;
G: if(cr==0 && c1==0 && c2==0 && c3==0 && v1==0 && v2==0 && v3==0)
begin s<=G;
13
else if(cr==1 && c1==0 && c2==0 && c3==0 && v1==0 && v2==0 && v3==0)
begin s<=C;
else if(cr==0 && c1==1 && c2==0 && c3==0 && v1==0 && v2==0 && v3==0)
begin s<=G;
else if(cr==0 && c1==0 && c2==1 && c3==0 && v1==0 && v2==0 && v3==0)
begin s<=G;
if(cr==0 && c1==0 && c2==0 && c3==1 && v1==0 && v2==0 && v3==0)
begin s<=G;
else if(cr==0 && c1==0 && c2==0 && c3==0 && v1==1 && v2==0 && v3==0)
begin s<=I;
else if(cr==0 && c1==0 && c2==0 && c3==0 && v1==0 && v2==1 && v3==0)
begin s<=J;
else if(cr==0 && c1==0 && c2==0 && c3==0 && v1==0 && v2==0 && v3==1)
begin s<=H;
H:begin s<=A; cro<=0;c1o<=0; c2o<=0;c3o<=0;v1o<=0;v2o<=0;v3o<=1; end

I:begin s<=A; cro<=0;c1o<=0; c2o<=0;c3o<=0;v1o<=1;v2o<=0;v3o<=0; end
J:begin s<=A; cro<=0;c1o<=0; c2o<=0;c3o<=0;v1o<=0;v2o<=1;v3o<=0; end
default:s<=A;
endcase
end
end
endmodule
14
RTL SCHEMATIC
Fig. no. 04--RTL SCHEMATIC OF SIMPLE VENDING MACHINE
15
Fig. no. 05-- RTL SCHEMATIC OF SIMPLE VENDING MACHINE
16
OUTPUT WAVEFORM
Fig. no. 06--OUTPUT WAVEFORM
17
PRESENT SCENARIO IN INDIA
Vending machines are not very common in India and are usually found only in major cities or
along some national highways. Seaga India, a 100% subsidiary of the Seaga Group of USA, is
the pioneer for bringing the concept of vending machines to India. Seaga India's machines are
being used by the Delhi Metro, the state government, IT parks, factories, BPO, etc.
Vending machines are used to sell snacks, beverages, condoms, public transit tickets, jewelry,
and change for currency notes.
Several reasons have been attributed to the lack of success of vending machines in India. The
availability of cheap labor makes operating stores or kiosks economical; customers lack of
technical knowledge and feel uneasy using vending machines; a lack of machines that accept a
wide variety of payment methods; vandalism, rough use, and poor maintenance of the
machines. However, vending machines are relatively new in India and analysts believe that
usage will rise.
18

A Simple Vending Machine: VLSI Design and Embedded System (VDES) - 2015

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

A Simple Vending Machine: VLSI Design and Embedded System (VDES) - 2015

Uploaded by

Copyright:

Available Formats

Summer Training programme

VLSI Design and Embedded System (VDES) - 2015

A SIMPLE VENDING MACHINE

MAYANK PRATAP SINGH

4 EDA TOOL Used: XILINX ISE 8.2i 5

6 FSM Design Steps 6

8 Design Description/ Specifications 6

13 Present scenario in India 14

inspiration for us.

MAYANK PRATAP SINGH

Fig.no.01--A SIMPLE VENDING MACHINE

Xilinx, Inc. is an American technology company, primarily a supplier of programmable logic

Fig. no. 02--MOORE FSM

FSM DESIGN STEPS

1. Obtain the specifications of the desired circuit

(a) Should show all possible states.

Fig. no.04--STATE DIAGRAM OF A SIMPLE VENDING MACHINE

• Vending Machine INPUTS

• The machine takes coins

• The machine has a Coin Return button (Cr)

module vendmach(clk,rst, cr,c1,c2,c3,v1,v2,v3, s, cro,c1o,c2o,c3o,v1o,v2o,v3o);

always @(posedge clk)

C: begin s<=A;cro<=1; c1o<=0; c2o<=0; c3o<=0; v1o<=0; v2o<=0; v3o<=0; end

H:begin s<=A; cro<=0;c1o<=0; c2o<=0;c3o<=0;v1o<=0;v2o<=0;v3o<=1; end

Fig. no. 04--RTL SCHEMATIC OF SIMPLE VENDING MACHINE

Fig. no. 06--OUTPUT WAVEFORM

You might also like