1402
6, JUNE 2007
Two-Dimensional Analytical Threshold Voltage and
Subthreshold Swing Models of Undoped Symmetric
Double-Gate MOSFETs
Hamdy Abd El Hamid, Jaume Roig Guitart, and Benjamin Iñíguez, Senior Member, IEEE
Abstract—We have developed analytical physically based mod-
els for the threshold voltage [including the drain-induced barrier
lowering (DIBL) effect] and the subthreshold swing of undoped
symmetrical double-gate (DG) MOSFETs. The models are derived
from an analytical solution of the 2-D Poisson equation in which
the electron concentration was included. The models for DIBL,
subthreshold swing, and threshold voltage roll-off have been veri-
fied by comparison with 2-D numerical simulations for different
values of channel length, channel thickness, and drain–source
voltage; very good agreement with the numerical simulations has
been observed.
Index Terms—Device modeling, double gate (DG), downscaling,
drain induced barrier lowering (DIBL), MOSFET, subthreshold
swing, threshold voltage.
I. INTRODUCTION
T HE DOUBLE-GATE (DG) architecture is one of the
MOSFET structures with the highest potential for the scal-
ing to dimensions below 45 nm [1]–[5] according to the require-
ments of the silicon roadmap in 2016 [6] and beyond. The
downscaling of device dimensions improves the IC perfor-
mance in digital and RF applications as well as the cost.
However, the 2-D electrostatic effects become relevant as the
channel is aggressively scaled down and may limit the perfor-
mance of scaled down MOSFETs, including, of course, DG
MOSFETs. When the channel length shrinks down, the elec-
trostatic controllability of the gate over the channel decreases
due to the increased charge sharing from source/drain [7].
The main short channel effects are the threshold voltage roll-
off (due to charge sharing), the degradation of the subthreshold
swing, and the drain induced barrier lowering (DIBL) effect.
As a result, the OFF-state current increases, and the ON–OFF
current ratio is degraded, and therefore, the device performance
is worsened.
Manuscript received October 11, 2006; revised March 6, 2007. This work
was supported by the Ministerio de Ciencia y Tecnología under Project
TEC2005-06297/MIC, by the European Commission under Contract 506844
(“SINANO”) and Contract 506653 (“EUROSOI”), and by the Distinction of
the Catalan Government for the Promotion of University Research. The review
of this paper was arranged by Editor C. McAndrew.
H. A. El Hamid and B. Iñíguez are with the Departament d’ Enginyeria
Electrònica, Elèctrica i Automàtica, Universitat Rovira i Virgili, 43007
Tarragona, Spain.
J. Roig Guitart is with the Laboratoire d’Analyse et d’Architecture des
Systèmes/Centre National de la Recherche Scientifique, 31077 Toulouse
Cedex 4, France.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2007.895856
0018-9383/$25.00 © 2007 IEEE
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO.
Compact and accurate models of the threshold voltage, which
are the DIBL and the subthreshold swing for DG MOSFETs,
are needed in order to facilitate and extend the use of these
devices in integrated circuits. However, a fully 2-D analyti-
cal threshold voltage and subthreshold swing models for DG
MOSFETs, and particularly for undoped devices, are still miss-
ing. Chen et al. [8] developed a 2-D model for the threshold
voltage roll-off of DG undoped devices, but that model did not
include DIBL effects. Kranti et al. [9], Chen et al. in [10],
and Suzuki et al. [11], [12] presented models that accounted
for the DIBL effect, but the devices considered were doped,
and the effect of the mobile charge density was neglected. It
has to be remarked that undoped DG MOSFETs show better
performances than doped ones because of their higher mobility.
In undoped devices, the effect of the mobile charge density
cannot be neglected in the near-threshold regime. It was shown
by Francis et al. [13] that even in doped DG MOSFETs, in
order to apply standard methods of threshold voltage extraction,
volume inversion should be considered when deriving a suitable
expression of the threshold voltage. Therefore, there is a press-
ing need to develop an analytical threshold voltage model based
on a solution of the 2-D Poisson’s equation which includes the
carrier concentration term.
The model by Munteanu et al. [14] addresses the DIBL
effect in a DG MOSFET but requires iterations to obtain the
expression of the electrostatic potential, from which a threshold
voltage equation can be derived; on the other hand, this model is
only valid for very thin Si films since it assumes a longitudinal
field that does not change along the depth of the film. Besides,
it is also based on using an expression of the quasi-Fermi
potential below threshold which was derived only for bulk
MOSFETs but which is adapted to DG silicon-on-insulator
(SOI) MOSFETs using fitting parameters; the geometry depen-
dence of them are not clear.
Liang and Taur [15] presented a 2-D analytical solution for
the short-channel effects in undoped DG MOSFET; the mobile
charge was neglected to solve the 2-D Poisson’s equation. This
approximation is valid well below threshold (the regime in
which the model of [15], the threshold voltage roll-off, DIBL,
and subthreshold slope are calculated], but near the threshold,
the mobile charge has an effect on the electrostatic potential.
On the other hand, no explicit model for the threshold voltage
is given in [15].
In this paper, we present 2-D models for the threshold
voltage (including the DIBL effect) and subthreshold swing
EL HAMID et al.: TWO-DIMENSIONAL THRESHOLD VOLTAGE AND SUBTHRESHOLD SWING MOSFETs 1403

Fig. 1. Symmetrical DG MOSFET considered in this paper. (a) 3-D device structure. (b) Cross section.

of a symmetric undoped DG MOSFET including the effect of The channel is undoped (∼ = 1016 cm−3 ), the n+ source and
the mobile charge density. The dependences of channel length, drain are highly doped. All calculations have been done at room
thickness, and drain–source voltage are accounted for. temperature.
We have used an appropriate definition of the threshold The channel electrostatics is governed by the Poisson equa-
voltage for these devices. In bulk MOSFET, it is usually defined tion. If the device is undoped
as the gate voltage at which the surface potential is equal to
q
two times the Fermi potential [16]. Nevertheless, this definition ∇2 φ(x, y) = n (1)
εsi
is not adequate for DG MOSFETs (particularly for undoped
devices), where the inversion and the accumulation take place in where φ is the electrostatic potential referenced to the Fermi
the whole film. The threshold voltage can be instead defined as level in the source [3], [4], the electron density is given as
the gate voltage at which the minimum sheet density of carriers
Qinv reaches a value QTH that can be identified as the onset of n = ni e(φ−φF )/VT (2)
the turn-on condition [8], [17].
We observed a very good agreement with 2-D numerical where ni is intrinsic electron density in silicon, VT is the
simulations of the threshold voltage and the subthreshold swing thermal voltage, and φF is the nonequilibrium quasi-Fermi
for different values of channel lengths and thickness and from level referenced to the Fermi level in the source, satisfying the
low to high drain–source voltage values. The structure of this following boundary conditions:
paper is the following: Section II addresses the derivation of the
φF (0, y) = 0 (3)
potential model from an analytical solution of the 2-D Poisson’s
equation. In Section III, we derive an expression of the location φF (L, y) = VDS (4)
of the minimum potential. In Section IV, the development of the
threshold voltage model, using the value of the minimum poten- where VDS is the drain voltage. The boundary conditions for φ
tial, is presented, and its dependence with the silicon thickness, are given as
channel length, and drain–source voltage is compared with

∂φ(x, y)


2-D numerical simulation results (using DESSIS–integral of Cox (VGS − φMS − φ(x, y = t0 )) = − εSi (5)
squared error). Conclusions are summarized in Section V. ∂y
y=t0
φ(0, y) = Vbi (6)

II. POTENTIAL MODEL DERIVATION φ(L, y) = Vbi + VDS (7)

Fig. 1 shows the cross section of the symmetrical where VGS is the gate voltage, φMS is the gate work func-
DG-MOSFET considered in this paper. We have assumed a tion referenced to intrinsic silicon, Vbi is the built-in voltage
DG-MOSFET with Si–SiO2 interface parallel to (100) plane. given as approximately 0.6 V, and t0 is half the Si thickness
1404 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 6, JUNE 2007

t0 = tSi /2. Assuming drift-diffusion transport, the drain– φ1 (x, y) is the solution of the residual 2-D Poisson’s equation:
current can be written as
q  
∇2 φ1 (x, y) = ni eφ0 (y)/VT eφ1 (x,y)/VT − 1 . (17)
t0 εsi
dφF
ID = q · µ · W n(x, y) · dy
dx Assuming that φ1 /VT is small, (17) can be reduced to be a
−t0
Laplace equation. This is a reasonable approximation in well-
t0 behaved devices, with not too strong short-channel effects. This
dφF
= q · µ · ni · W e[φ(x,y)−φF ]/VT dy (8) is equivalent to use the superposition of a 1-D solution of the
dx
−t0 Poisson’s equation assuming a 1-D distribution of the mobile
or charge and a 2-D solution of Laplace’s equation. Therefore,
φ1 (x, y) can be considered the solution of
Vds
e−φF /VT dφF ∂2 ∂2
ID = q · ni · W µ L0 (9) φ1 (x, y) + 2 φ1 (x, y) = 0. (18)
 ∂x ∂y
dx
0
t0 Using (11), the boundary conditions of φ1 (x, y) can be
eφ(x,y)/VT dy
−t0
written as

where W is the device width, µ is the electron low field φ1 (0, y) = Vbi − φ0 (y) (19)
mobility. In the subthreshold regime, the quasi-Fermi potential φ1 (L, y) = VDS + Vbi − φ0 (y) (20)
retains its value at the source end in most of the channel [8];
in fact, this region with a constant value of φF is the only and
region which significantly contributes to the integral in the

εox ∂φ1 (x, y)


numerator on the right-hand side of (9) [18]. Therefore, for · [0 − φ1 (x, y = to )] = −εsi ·
. (21)
practical purposes, in the 2-D Poisson’s equation (1), we can tox ∂y y=to
use the expression of the electron density with φF = 0 (value
The solution for the 1-D potential term φ0 (y) is given by [3]:
of the quasi-Fermi potential at the source)
 2 
Bn
n = ni eφ(x,y)/VT . (10) φ0 (y) = VT · ln sec2 (Bn · y) . (22)
2·δ
In order to find an analytical solution, we apply the superposi-
The solution of (18) with the boundary conditions (19)–(21) is
tion principle, and we write the potential φ (x, y) as the sum of
(for details about the procedure, see Appendix)
two terms: φo (y), which is the solution of the 1-D Poisson’s
equation in the direction perpendicular to the channel, and
 x−L

φ1 (x, y) = C0 · eλ t0 + C1 · e−λ t0 · cos(λ · y)
x
φ1 (x, y), which is the solution of the residual 2-D differential (23)
equation:
where
φ(x, y) = φ0 (y) + φ1 (x, y). (11)
q
δ= ni · t20 (24)
Therefore, φ0 (y) is the solution of εsi · Vt
q and
∇2 φ0 (y) = n (12)
εsi   
C0 = S1 · VDS + Vbi · 1 − e−L to
λ
− S2 · φso (25)
where   
C1 = S1 · Vbi · 1 − e−L to − VDS · e−L to − S2 · φso .
λ λ

n = ni eφ0 (y)/VT . (13)

(26)
The boundary conditions of φ0 (y) are

S1 and S2 depend on the device dimensions and are given by
∂φ0


=0 (14)
∂y
y=0 S1 =
4 · sin(λ)
  (27)
[2 · λ + sin(2 · λ)] · 1 − e−2L to
λ

and


  
4 · λ · cos λ2 · 1 − e−L to
λ
εox ∂φ0


· [VGS − φms − φ0 (y = t0 )] = −εsi · (15)  
tox ∂y
y=to S2 = (28)
[2 · λ + sin(2 · λ)] · 1 − e−2L to
λ

where εox · to
Cr = (29)
tsi tox · εsi
t0 = (16)
2 2 · λ tan(λ) = Cr . (30)
EL HAMID et al.: TWO-DIMENSIONAL THRESHOLD VOLTAGE AND SUBTHRESHOLD SWING MOSFETs 1405

can be calculated from the total potential as

φmin (y) = φ0 (y) + φ1 (x, y)|min . (31)

φ1 (x, y)|min is the minimum potential along the longitudinal

direction and can be obtained from

φ1 (x, y)|min = φ1 (xmin , y) (32)

where


∂φ1 (x, y)



= 0. (33)
∂x xmin

We obtained the following expression of xmin , as shown at

the bottom of the page. We can see from (34) that at zero
drain–source voltage, xmin = 0.5L. At high drain–source volt-
age value, the virtual cathode becomes closer to source end.
By substituting (34) into the total potential equation (31),
we obtain the position of the virtual cathode at different Si
thickness.

IV. INVERSION CHARGE AND THRESHOLD VOLTAGE

Fig. 2. Surface potential distribution along the channel for silicon thickness is
5 nm, and L is 20 nm. The carrier charge sheet density Qinv at the potential min-
imum is obtained by integrating its spatial density throughout
the entire film thickness:
φs0 is the surface potential of long-channel devices [1-D sur-
face potential, obtained from (22) using y = t0 ]. The constant t0
Bn , in (22), can be calculated from the boundary condition Qinv = 2 ni eφ[xmin ,y]/VT dy. (35)
listed in (15). The total potential is calculated by using (22) 0
and (23) in (11).
A good agreement has been obtained between the model we The integral in (35) can be approximated by considering
have introduced and the 2-D numerical simulation results for a the integrand fixed at its value at 0.5t0 , since, as shown by
low and high drain–source voltage values, as shown in Fig. 2 Chen et al. [10], that is the location of the effective conductive
(for VGS = 0.1 V). path (validated with numerical simulations). After some math-
The quantum effects, which become relevant for Si film ematical manipulations, we obtain
thickness smaller than 10 nm, have not been considered in this  
paper. They originate a reduction of the channel charge density 1 QTH
VTH = φms + · VT ln −Sds . (36)
and an increase of the threshold voltage [19]. Anyway, the 1 − Sgs 2ni · to
quantum correction to the threshold voltage is much smaller
in lightly doped devices than in highly doped ones [20]. On the QTH is the value at which the inversion charge a threshold value
other hand, the small reduction of the subthreshold swing [21] and found numerically to be approximately 3.1010 cm−2 [8],
caused by the quantum confinement in thin Si films becomes and φms is the gate work function referenced to intrinsic silicon.
negligible in extremely thin Si films [21]. In (36)
  
λ −L tλ λ
Sds = 2 · S1 · cos ·e 0 VDS · sinh xmin
III. VIRTUAL CATHODE: VALUE AND POSITION 2 t0
   
The minimum point at which the potential reaches its mini- Lλ L λ
+ 2 · Vbi ·sinh ·cosh xmin − (37)
mum value is called “virtual cathode.” The minimum potential 2 t0 2 t0

     
−L tλ cos( λ
2) −L tλ
L t0  V bi · 1 − e 0 + V DS − λ · sin(λ) 1 − e 0 · φ so 
xmin = − · ln       (34)
2 2·λ −L tλ −L tλ cos( λ ) −L λ
Vbi · 1 − e 0 − VDS · e 0 − λ · sin(λ) 2
1 − e t0 · φso
1406 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 6, JUNE 2007

Fig. 3. Threshold voltage roll-off versus channel length for different channel Fig. 4. DIBL coefficient versus channel length for different channel thickness.
thickness. The discrete circles and diamonds lines are accounting for numerical
results by [22] VDS = 1 V.
The threshold voltage value at low drain–source voltage is,
and from (36)
    
λ L λ 1 QTH
· e− 2 t0 · cosh xmin −
L λ
Sgs = 2 · S2 · cos . VTH0 = φms + · VT ln − Sdso (42)
2 2 t0 1 − Sgso 2ni · to
(38)

In devices where the channel is long with respect to the channel where
thickness, Sgs is close to zero. Therefore, the long channel   
threshold voltage can be written as L λ
1 + cos(λ) sinh 2 t0
e−2L t0 ·  
λ
Sgso =  (43)
  1 + sin(2 · λ)/2 · λ
QTH sinh L tλ0
VTH = φms + VT ln − Sds . (39)
2ni · to
and
The threshold voltage derived in (36) tends to the theoretical
  
long channel value (39) as the channel length increases. For

cos λ2 /λ sinh L2 tλ0
long enough channels, Sds tends to zero, and the threshold Sdso = ·   · Vbi . (44)
voltage expression reduces to the one reported by Chen et al. [8] 1 + sin (2 · λ) /2 · λ sinh L tλ0

QTH
VTH = φms + VT ln . (40) The DIBL coefficient can therefore be written as:
2ni · to
   
Equations (40) and (36) constitute the threshold voltage QTH 1 1
compact models for both short and long channel devices. The DIBL = VT ln −
2ni · to 1 − Sgso 1 − Sgs
DG-MOSFET threshold voltage roll-off can be written as the  
difference between the values of threshold voltage calculated Sdso Sds
− − /[Vds,high − Vds,low ].
using (40) and (36) 1 − Sgso 1 − Sgso
   (45)
QTH 1
∆VTH = VT ln 1− − Sds . (41)
2ni · to 1 − Sgs
As shown in Fig. 4, very good agreement has been obtained
with 2-D numerical simulations using DESSIS-ISE for channel
The threshold voltage roll-off shows a good agreement with the
lengths down to 30 nm. This confirms that the approximations
numerical results published by Frank and Dennard [22], which
done do not significantly hamper the accuracy of the model.
includes the DIBL effect, as shown in Fig. 3.
The decrease of the threshold voltage with Vds is due to
the DIBL effect. The DIBL has to be determined from the
V. SUBTHRESHOLD SWING MODEL
difference between the threshold voltage at high drain–source
voltage value (e.g., 1 V) and the threshold voltage value at low To find an expression for the subthreshold swing, following
drain–source voltage (0.1 V), using (36) (see Fig. 4). [10], we assume that the subthreshold drain current ID is
EL HAMID et al.: TWO-DIMENSIONAL THRESHOLD VOLTAGE AND SUBTHRESHOLD SWING MOSFETs 1407

file is analytically obtained, which is valid from low to high

drain–source voltage. Good agreement has been observed with
numerical 2-D simulations for a broad range of film thickness
and drain–source voltage values, and for channel lengths down
to 20 nm.

A PPENDIX
We use variable separations to find the solution of (18), i.e.,

φ1 (x, y) = G(y) · H(x) (A.1)

Using (A.1) in (18) and rearranging the resulting equation,

we get
G (y) H  (x)
=− = −λ2 (A.2)
G(y) H(x)
Fig. 5. Subthreshold swing for DG MOSFET with tox = 2 nm.
where λ is the separation factor, i.e., eigen value.
proportional to the total amount of the free electrons diffusing
over the virtual cathode:
ACKNOWLEDGMENT
to
The authors would like to thank Prof. T. A. Fjeldly for his
ID α ni e(φmin −φF )/VT dy. (46)
helpful comments on this paper.
0

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Hamdy Abd El Hamid was born in 1970. He
received the B.S. degree in electrical engineer-
ing from Higher Technological Institute, Tenth of
Ramadan, Egypt, in 1994, and the M.S. degree in
electronic engineering from Ain Shams University,
Cairo, Egypt, in 2000. Since 2003, he has been
working toward the Ph.D. degree at the Departament
d’ Enginyeria Electrònica, Elèctrica i Automàtica
(DEEEA), Universitat Rovira i Virgili (URV),
Tarragona, Spain.
He was a Graduate Visiting Student in the
Electrical Engineering Department, University of Liverpool, Liverpool, U.K.,
from April to June 2005, and in the Microelectronics Laboratory, Université
catholique de Louvain (UCL), Louvain-la-Neuve, Belgium, from April to June
2006 and in February 2007. His research focuses on the physics and modeling
of nanoscale MOSFETs. He will obtain his Ph.D. in May 2007.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 6, JUNE 2007
Jaume Roig Guitart was born in Roses, Catalonia,
Spain, in 1976. He received the B.S. degree in
physics and the Ph.D. degree in microelectronics en-
gineering from Universitat Autònoma de Barcelona,
Barcelona, Spain, in 1999 and 2004, respectively.
From 2000 to 2005, he was with the Centre Na-
cional de Microelectronica (CNM-IMB), Barcelona,
Spain, where he was involved in high-voltage smart
power devices in SOI and bulk technologies. He
was with the Intégration de Systèmes de Gestion de
l’Energie (ISGE) team in the Laboratoire d’Analyse
et d’Architecture des Systèmes (LAAS)/Centre National de la Recherche
Scientifique (CNRS), Toulouse, France, in 2005. His current research activity
deals with semiconductor power device physics. He is author and coauthor of
more than 40 scientific articles in international journals and conferences.
Benjamin Iñíguez (M’96–SM’03) received the B.S.,
M.S., and Ph.D. degrees in physics from the Uni-
versity of the Balearic Islands (UIB), Palma, Spain,
in 1989, 1992, and 1996, respectively. His doctoral
research focused on the development of computer-
aided design models for short-channel bulk-Si and
SOI MOSFETs.
From 1997 to 1998, he was working as a Post-
doctoral Research Scientist at the Electrical, Com-
puter and Systems Engineering (ECSE) Department,
Rensselaer Polytechnic Institute (RPI), Troy, NY,
where he studied advanced devices such as short-channel a-Si and poly-Si thin-
film transistors, GaN HFETs, and heterodimensional MESFETs. From 1998
to 2001, he was a Research Scientist (Postdoctoral Marie-Curie Grant Holder)
in the Microelectronics Laboratory, Université catholique de Louvain (UCL),
Louvain-la-Neuve, Belgium, working on the characterization and modeling of
thin-film and ultrathin-film SOI MOSFETs from dc to RF conditions. Since
2001, he has been with the Departament d’ Enginyeria Electrònica, Elèctrica i
Automàtica (DEEEA), Universitat Rovira i Virgili (URV), Tarragona, Spain,
as Titular Professor. His current research interests are characterization and
modeling of advanced electron devices, particularly nanoscale multiple-gate
MOSFETs and organic and polymer TFTs.
Dr. Iñíguez was awarded the Distinction of the Catalan Government for
the Promotion of University Research in 2004. In 2007 he obtained the IET
Circuits, Devices and Systems Premium.