Par

chapter 1
VLSI Systems Design The Need for HDLs

Top-
Top-down Design and HDLs A specification is an engineering contract that lists all the
goals for a project:
It seems I goals include area, power, throughput, latency,

have to functionality, test coverage, costs (NREs
(NREs and piece costs).
hurry up!
Helps you figure out when you’re done and how to make
engineering tradeoffs. Later on goals help remind everyone
(especially management) what was agreed to!
partition the project into modules with well-

well-defined
interfaces so that each module can be worked on by a
separate team. Gives the SW types a head start too!
(Hardware/software codesign)
codesign)
A behavioral model serves as an executable specification

that documents the exact behavior of all the individual
Overview modules and their interfaces. Since one can run tests, this
Top down design-
design-flow, VHDL hardware description model can be refined and finally verified through
language, test-
test-bench methodology simulation.
Goal: You are able to design circuits with the VHDL We need a way to talk about what hardware should do
language with behavioral, dataflow and structural without actually designing the hardware itself, i.e., need to
modeling. You are familiar with the top down design flow separate functionality from implementation. We need a
and the test-
test-bench methodology. Hardware Description Language
MicroLab, VLSI-21 (1/95) MicroLab, VLSI-21 (2/95)
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The Need for HDLs cont. Hardware Description Languages
easier to explore ideas in HDLs than in logic gates textual HDLs

stepwise refinement: HDLs allow to describe VHDL, Verilog-
Verilog-HDL, HardwareC,
HardwareC, SystemC,
SystemC, UML, etc.
designs at various levels of abstraction graphic HDLs
HDLs sustain description-
description-synthesis method SpecdChart,
SpecdChart, etc. (control & dataflow graphs)
pitfalls: abstract models are not precise tabular HDLs
BIF, etc. (FSMD models in tabular forms)
first HDLs were introduced in late 70s time-

time-diagram HDLs
Waves, etc.
difficulties to develop general purpose HDL for
signal-
signal-processing and real-
real-time applications and ...
portability needs lead to standardizations (Institute Standardization
of electrical and electronics engineering, IEEE) VHDL: IEEE Std 1067-
1067-1987 & 1993
std_logic package IEEE Std 1164-
1164-1993
Verilog-
Verilog-HDL: IEEE Std 1997
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A Tale of Two HDLs Introduction to VHDL & Verilog
VHDL Verilog-
Verilog-HDL
VHSIC HDL, Very High Speed C-like concise syntax
Integrated Circuits. ADA-
ADA-like VHDL Verilog-
Verilog-HDL
verbose syntax, lots of redundancy
rich & powerful simple & efficient
Extensible types and Built-
Built-in types and logic language language
simulation engine. Logic representations. Oddly,
representations are not this has led to slightly data type driven hardware driven
built in and have evolved incompatible simulators language language
with time (IEEE-
(IEEE-1164). from different vendors.
goal: documentation of goal: automatic
Design is composed of Design is composed of
large complex systems synthesis
entities each of which can have modules.
modules.
multiple architectures.
architectures. A
configuration chooses what language structures language structures
architecture is used for a given entity (hierarchy module (blocks or sub-
sub-
instance of an entity. interface) blocks)
architecture (behavior #include (file
Behavioral, structural, Behavioral, structural, of system) structuring)
logic-
logic-level modeling logic-
logic-level modeling
configuration (binding
Synthesizable subset... Synthesizable subset... of entity and
architecture)
Harder to learn and use, Easy to learn and use,
not technology-
technology-specific, fast simulation, good for package (library of
DoD mandate. logic. Gateway Design global types or
Automation blocks)
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chapter 2 (starter)
Introduction to VHDL & Verilog cont. Signals, Delays, Events, Concurrency
language features digital systems in contrast to software systems are

signal data types (in, out, bidir,
bidir, signal-
signal-strength ...) fundamentally about signals
hardware structures (memory, register-
register-files, ...) signals in contrast to variables do have delays which
leads to signal waveforms
logic operators (shift, rotation, masking, ...)
digital systems are comprised of components
asynchronous structures (set, reset of memories)
digital systems do have concurrency of operation
parallel or synchronous structures
events on signals lead to computations that may
constraints (pin, technology, area, delays, ...) generate events on other signals
event
VHDL b
sum
carry
time (ns)
5 10 15 20 25 30 35 40
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Signal Values Resolved Signals
it is common for components in a digital system to
signal values are physically associated to wires have multiple sources for the value of an input
VHDL language supports signal type: signal
type: bit, values: ‘0’, ‘1’ many designs use buses:
buses: a group of signals that can
be shared among multiple sources
type: bit_vector, values: “0001”, etc
the values on shared signals will be determined
VHDL package IEEE 1164 supports signal type: upon the type of interconnection, like wired logic
type: std_ulogic and vector std_ulogic_vector the signal values depend on its implementation
std_ulogic is a 9 value logic
the
the VHDL simulator has to resolve the signals value
The
The IEEE 1164 package offers std_logic and
value interpretation std_logic_vector signal types for resolved version
of the signal std_ulogic and std_ulogic_vector
U un-
un-initialized
X forcing unknown
0 forcing 0 resolved signal necessary
1 forcing 1 wired-
wired-or logic
Z high impedance
W weak unknown
L weak 0
H weak 1 unresolved signal
- don’t care
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chapter 3 (starter)
Entity Exercises Ex401: Entity
the design entity is a primary programming Ex401 (difficulty: easy): Define the entities of the
abstraction in VHDL following digital components. Use the unresolved 9
entity defines the interface of a component, without value logic of the IEEE 1164 package. Each
giving any information about the component component has to be edited in a separate file with
behavior the components name plus extension “.vhd
“.vhd”
vhd” . The
files have to be analyzed by the Synopsys command:
vhdlan
a sum
sNot
+
b carry i0
Mux4to1 d q
i1 D_ff
z
entity HalfAdder is i2 clk qNot
port (a,b : in bit;
bit i3
sum,carry : out bit);
bit
end HalfAdder; sel rNot
8 bit data
library IEEE; n z
use IEEE.std_logic_1164.all; a
32 bit data Alu32
entity HalfAdder is 6 bit op-
op-code c
port (a,b : in std_ulogic; use first letter of
b component name in capital,
sum,carry : out std_ulogic);
op and first letter of signal
end HalfAdder;
name in small cap
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Architecture Entity-
Entity-Architecture: Hierarchy
(VHDL vs. Verilog)
Verilog)
the design architecture is a primary programming
abstraction in VHDL +
architecture describes the internal behavior of a

component, without giving any information about library IEEE;;
the component IO’s use IEEE.std_logic_1164.all;
entity FullAdder is
The behavioral description can take many forms.
port (a,b,ci: in std_logic; co,s:out
out std_logic);
These forms differ in the levels of abstraction and end FullAdder; VHDL
detail.
architecture behavior of FullAdder is
-- comment: declaration of variables
architecture behavior of HalfAdder is begin
-- comment: declaration of variables functional description
begin of the system
...
functional description
end behavior; module FullAdder (a,b,ci,co,s);
of the system
input a,b,ci;
output co,s;
end behavior;
/* comment: declarations of variables */
...
Verilog-
Verilog-HDL functional description
of the system
endmodule
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Concurrency Dataflow Model #1
The operation of digital systems is inherently

concurrent
+
Within VHDL signals are assigned values using
signal assignment statements <=
Multiple signal assignment statements are executed
concurrently
concurrent architecture concurrent_behavior of HalfAdder is
signal assignment begin
sum <= (a xor b) after 5 ns;
ns library IEEE;;
carry <= (a and b) after 5 ns;
ns use IEEE.std_logic_1164.all;
end concurrent_behavior;
entity HalfAdder is
port (a,b: in std_logic;
a carry,sum:out
out std_logic);
end HalfAdder;
b
architecture dataflow of HalfAdder is
begin
sum sum <= (a xor b) after 5 ns;ns
carry <= (a and b) after 5 ns;
ns
carry end dataflow;
time (ns)
5 10 15 20 25 30 35 40
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Dataflow Model #2 Signal Assignments #1
s1
L1
L4
+ simple signal assignments
L2 s2
L5
L3 s3
sum<=(a xor b) after 5 ns, (a or b) after 10 ns, (not a) after 15 ns;
sig <= ‘0’, ‘1’ after 10 ns, ‘0’ after 20 ns, ‘1’ after 40 ns;
library IEEE;;
use IEEE.std_logic_1164.all; time (ns)
5 10 15 20 25 30 35 40
entity FullAdder is
port (a,b,cIn: in std_logic; clock <= ‘0’, not(clock) after 5 ns;
cOut,sum: out std_logic);
end FullAdder;
time (ns)
architecture architecture dataflow of FullAdder is
declarative signal s1,s2,s3 : std_logic; 5 10 15 20 25 30 35 40
constant gate_delay: Time:=5 ns;ns
segment begin a <= “00000000_00000000”, to_stdlogicvector(x”abcd”) after 5 ns;
L1: s1 <= (a xor b) after gate_delay;
L2: s2 <= (cIn and s1) after gate_delay;
Type conversion from hexadecimal
architecture L3: s3 <= (a and b) after gate_delay; to std_logic_vector is defined in
body L4: sum <= (s1 xor cIn) after gate_delay; package std_logic_1164
L5: cOut <= (s2 or s3) after gate_delay;
end dataflow; goto UNIX directory, where packages are placed:
cd $SYNOPSYS/packages/IEEE/src
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Conditional Signal Assignment #2 Exercises Ex402: Conditional Signal
Assignment
The right hand value is computed immediately and Ex402 (difficulty: easy): Define the VHDL code of
assigned at some point in the future using the after a 1bit ALU with the operations: AND, OR,
clause FullAdder.
FullAdder. Use the resolved 9 value logic of the
IEEE 1164 package. The Simple1bitALU.vhd file has
library IEEE;; to be analyzed and simulated by the Synopsys
use IEEE.std_logic_1164.all; commands: vhdlan &
entity Mux4to1 is
port (i0,i1,i2,i3: in std_logic_vector(7 downto 0); carry
sel : in std_logic_vector(1 downto 0); a
z : out std_logic_vector(7 downto 0)); ALU
carryIn result
end Mux4to1;
b
architecture dataflow of Mux4to1 is opcode
begin
z <= i0 after 5 ns when sel=“00” else
one single i1 after 5 ns when sel=“01” else
signal i2 after 5 ns when sel=“10” else
assignment i3 after 5 ns when sel=“11” else
“00000000” after 5 ns; ns
end dataflow;
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Delays: Delta Delay Model Delays: Inertial Delay Model
The VHDL language distinguished between tree Digital circuits have a certain amount of inertia.
delay models: For example it takes a finite amount of time and a
Delta delay model certain amount of energy for the output of a gate to
Inertial delay model (default) respond to a change on the input
Transport delay model Inertial
Inertial delay model (default)
Delta
Delta delay model a pulse shorter than the propagation delay will not
If no delay is specified, a delta delay is assumed. A delta propagate to the output
delay is as small as zero delay. It is used by the
simulator which sums delta delays to zero. out1 <= (a xor b) after 8 ns;
out2 <= (a xor b) after 2 ns;
in1 architecture delta_delay of Comb is
signal s1,s2,s3,s4: std_logic:=0;
in2 begin
input
out
z s1 <=not(in1); input
s1 s2 <=not(in2); 8 ns
s2 s3 <=not(s1 and in2); out1 output for delay: 8 ns
s4 <=not(s2 and in1);
s3 z <=not(s3 and s4); 2 ns
s4 end delta_delay;; out2 output for delay: 2 ns
time (ns)
0 10 20 30 40 50 60 70
in2
s2 5 10 15 20 25 30 35 40
s3
z VHDL’93!
sum <=reject 2 ns inertial (a xor b) after 5 ns;
10 ∆ 2∆ 3∆
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Delays: Transport Delay Model Delay Model in Practice
Accurate delay library IEEE;;
Unlike switching devices, wires have a modeling of wire use IEEE.std_logic_1164.all;
comparatively less inertia, As a result, wires will delays is possible,
although in practice it entity HalfAdder is
propagate signals with very small pulse width. is difficult to obtain port (a,b: in std_logic;
In modern technologies with increasingly small accurate estimates of carry,sum:out
out std_logic);
feature sizes the wire delays dominate. the wire delay without end HalfAdder;
proceeding through
Transport
Transport delay model physical design and architecture transport_delay of HalfAdder is
any pulse will propagate to the output, independent of layout of the circuit. signal s1,s2: std_logic:=‘0’;
the delay begin
s1 <= (a xor b) after 2 ns;
ns
a s1 s2 <= (a and b) after 2 ns;
sum ns
out1 <= transport (a xor b) after 8 ns; b sum <= transport s1 after 4 ns;
ns
carry <= transport s2 after 4 ns;
ns
s2 end transport_delay;
input carry
out
a
input inertial
b
8 ns
output for delay: 8 ns sum
out1
carry transport
time (ns) s1
5 10 15 20 25 30 35 40 s2
time (ns)
0 2 4 6 8 10 12 14
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chapter 4 (starter)
Exercises vlsi21: Conditional The Process Construct #1

Assignments
Ex403 (difficulty: easy): Write and simulate a The continuous assignment model is used when
VHDL model of a 2-2-bit comparator (compare on components correspond to gates.
equality, filename: Comp2.vhd).
The process construct enables the use of
a
conventional programming language constructs.
Comp2 c In contrast to concurrent signal assignment
b statements a process is a sequentially executed
Ex404 (difficulty: easy): Construct and test a block of code.
VHDL module for generating the following
waveforms. Control flow within a process is strictly sequential.
a With respect to simulation time a process executes
b in zero time.
c time (ns)
0 10 20 30 40 50 60 architecture behavior of MyProcess is
begin
process
process declarative part
Ex vlsi21 (difficulty: easy): Have a look at the
exercises at the end of chapter 3 of “VHDL: begin
Starter’s Guide” process body
end process;
process
end behavior;
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Example: Process Statement The Process Construct #2
library IEEE;;
use IEEE.std_logic_1164.all;
The execution of a process is initiated whenever an
use IEEE.std_logic_unsigned.all;
event occurs on any signal in the sensitivity list
entity Memory is Once started the process executes to completion in
port (addr,wrData: in std_logic_vector(31 downto 0); zero (simulation) time.
wr,rd: in std_logic;
rdData :out
out std_logic_vector(31 downto 0)); Processes execute concurrently with other
end Memory; processes and concurrent signal assignments.
architecture behavioral of Memory is Concurrent signal assignments are in fact only
type memArray is array
array(0 to 1024) of std_logic_vector(31 downto 0); special cases of processes.
begin sensitivity list
MemProcess:: process(addr,wr,rd)
process
variable mem: memArray :=(
identical behavior
(x“00000A06“), -- initializing memory data
others => (x“00000000“));
variable addrIndex: integer;
integer
architecture behavior of MyBlock1 is architecture behavior of MyBlock2 is
begin
immediate begin begin
addrIndex:=conv_integer(addr);
variable c <= a and b after 5 ns;
ns process(a,b)
process
if (wr = ‘1‘) then
assignment end behavior; begin
mem(addrIndex):=wrData;
c <= a and b after 5 ns;
ns
elsif (rd = ‘1’) then
end process;
process
rdData <=mem(addrIndex) after 10 ns; ns concurrent end behavior;
end if;
if signal concurrent signal assignment
end process; assignment
process
end behavioral;
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VHDL vs. Verilog:
Verilog: Events Conditional Programming Constructs
Events are variable or signal changes.

If-
If-then-
then-else statement
Real circuits are event driven.
if condition then sequential statement
[ elsif condition then sequential statement ]
VHDL Verilog-
Verilog-HDL
[ else sequential statement ] end if;
process sensitivity list always @(sensitivity case statement
begin statements; list) statement
end process; case expression is
initial (sensitivity when choices => sequential statements }
{when
wait on/until/for list) statement
event; [ when others => sequential statements ]
end case;
whow!
whow!
everything is
event driven like
in real life
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Example: Condition Statements VHDL vs. Verilog:
Verilog:
library IEEE;; Combinational Logic Example
entity Multiplexer4to1 is
entity HalfAdder is port (sel: in std_logic_vector (1 downto 0);
port (a,b: in std_logic; a,b,c,d: in std_logic_vector (15 downto 0);
sum,carry: out std_logic); z:out std_logic_vector (15 downto0));
downto0
end HalfAdder; end Multiplexer4to1;
VHDL
architecture behavioral of HalfAdder is architecture DemoExample of Multiplexer4to1 is
begin begin
If_Process:: process(a,b)
process process (a,b,c,d,sel)
4 to 1 multiplexer
begin begin (no interfered memory)
if (a = b) then case sel is
sum<= ‘ 0‘ after 5 ns;ns when (“00“) => z <= a;
else when (“01“) => z <= b;
sum<= (a or b) after 5 ns; ns when (“10“) => z <= c;
end if;
if when (“11“) => z <= d; module Multiplexer4to1(sel,a,b,c,d,z);
end process; when others => z<=“-------“;input [1:0]] sel;
end case; input [15:0]] a,b,c,d;
Case_Process:: process(a,b)
process end process; output [15:0]] z;
begin end DemoExample;
case a is assign z =(sel == 2’d0) ? a:
when ‘0‘ => carry <= a after 5 ns;
ns (sel == 2’d1) ? b:
when ‘1‘ => carry <= b after 5 ns;
ns (sel == 2’d2) ? c:
when others => carry <= ‘x‘ after 5 ns;
ns (sel == 2’d3) ? d:
end case;
case Verilog-
Verilog-HDL 16’bx;
end process; endmodule
end behavioral; MicroLab, VLSI-21 (31/95) MicroLab, VLSI-21 (32/95)
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Loop Programming Constructs Example: Loop Statements
library IEEE;;
loop index has not to be
for loop statement declared but can only be
use IEEE.std_logic_unsigned.all; a
Multiplier
for index in range loop used locally (32 bit)
bit) m
entity Multiplier is b
sequential statements port (a,b: in std_logic_vector(31 downto 0);
m: out std_logic_vector(63 downto 0));
end loop; end Multiplier;
architecture behavioral of Multiplier is

while loop statement constant modulDelay: Time:=10
Time ns;
begin
while condition loop process(a,b)
process
sequential statements variable bReg: std_logic_vector(63 downto 0);
variable aReg: std_logic_vector(31 downto 0);
end loop; begin
aReg:=a;
bReg:=(x“00000000“) & b;
for index in 1 to 32 loop
if bReg(0)= ‘ 1‘ then
bReg(63 downto 32):=bReg(63 downto 32)+aReg(31 downto 0);
end if;
if
bReg(63 downto 0):= ‘ 0‘ & bReg(63 downto 1);
end loop;
loop
m<=bReg after modulDelay;
end process;
end behavioral;
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Exercises vlsi21: Loops More on Processes
Ex405 (difficulty: easy): Write a VHDL code for a Never assign a value to a signal in different
combinational shift logic block with 8 bit data processes (multiple drives).
buses with zero fill. Use the 2 bit signal shiftNum
to indicate the number of bits to be shifted. If a process A conflict
- two drivers!
std_logic_vector has to be converted to an integer y<=‘0‘;
- not synthesis
synthesisable!
type, the conv_integer()
conv_integer() function from the
std_logic_unsigned package can be used. process B
y<=‘1‘;
shiftLeft shiftRight
dataIn Shift dataOut Upon initialization all processes are executed at

once.
shiftNum Thereafter processes are executed in a data-
data-driven
manner:
activated by events on signal list of the process or
by waiting on occurrences of specific events using wait
statements
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The Wait Statement Example: Wait Statements
library IEEE;; library IEEE;;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;
A more general way to specify when a process
executes is the wait statement. entity Dff1 is entity Dff2 is
port (d,clk: in std_logic; port (d,clk,rst: in std_logic;
Wait statements explicitly specify the conditions q,qBar: out std_logic); q,qBar: out std_logic);
under which a process may resume execution after end Dff1; end Dff2;
being suspended
suspended.
ed.
With wait statements a process can be suspended at architecture behavioral of Dff1 is architecture behavioral of Dff2 is
multiple points. begin begin
process process(clk,rst);
process
begin begin
wait for time expression; wait until (clk‘event
event and clk=‘1‘); if (rst=‘0‘) then
q <=d after 1 ns; ns q <= ‘0‘ after 1 ns; ns
example: wait for 20 ns; qBar<=not not d after 1 ns;
ns qBar<= ‘1‘ after 1 ns;ns
end process; elsif (clk‘event
event and clk=‘1‘) then
end behavioral; q <=d after 1 ns; ns
wait on signal; qBar<=not not d after 1 ns;
ns
example: wait on clk,reset,status; end if;
if
end process;
end behavioral;
wait until condition;
example: wait until (a = ‘1‘);
if a process has no sensitivity list you MUST
use wait statements, otherwise your process
wait;
never suspends and blocks your simulation
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Latch vs. Flip-
lip-Flop Exercises vlsi21: Synchronous
process(clk,reset,d)
process
begin
if (reset = ‘0’) then d D Q q
q <= ‘0’; Ex406 (difficulty: easy): Write a VHDL code for a
Latch
elsif (clk=‘1’) then clk 16 bit register with an enable and a asynchronous
q <= d; reset input.
end if; Register16
end process;
reset d q
enable
process(clk,reset)
process
begin clk
if (reset = ‘0’) then d D Q q
q <= ‘0’; Flip-
Flip-Flop
elsif (clk’event
event and clk=‘1’) then clk reset
q <= d;
end if;
end process; reset
Ex407
Ex407 (difficulty: easy): Write a VHDL code for a
16 bit counter with an enable a load and a
process(clk,reset)
process
asynchronous reset input.
begin Counter16
if (reset = ‘0‘) then data count
q <= “00000000“; Mux D Q q enable
elsif rising_edge(clk) then d
register load
if (enable = ‘1’) then enable
q <= d; clk clk
end if;
if
end if;
end process; reset reset
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More on Wait: Inter-
Inter-Process Comm. Exercises vlsi21: Handshake
transmitData
request
acknowledge Ex vlsi408a (difficulty: easy, optional): Write a
VHDL model for communication between an input
receiveData
receiveData time process and an output process using handshaking
protocol. The input process can only read a single
entity Handshake is word (32 bit) at a time. The output device requires
port(inputData:
port in std_logic_vector(31 downto 0)); a reversing byte order, which is performed by the
end Handshake;
input process. Assign a delay of 1 ns to each
architecture behavioral of Handshake is handshake signal.
signal transmitData: std_logic_vector(31 downto 0); AsyncComm
signal request, acknowledge: std_logic;
begin inputData outputData
input process output process
producer:: process consumer:: process
begin variable receiveData:
wait until inputData‘event
event;
event std_logic_vector(31 downto 0);
transmitData<=inputData; begin
request<=‘1‘; wait until request=‘1‘;
wait until acknowledge=‘1‘; receiveData:=transmitData;
request<=‘0‘; acknowledge<=‘1‘; Ex vlsi408b (difficulty: medium, optional):
wait until acknowledge=‘0‘; wait until request=‘0‘; Rewrite the above handshake model by using a clk1,
end process; acknowledge<=‘0‘; clk2 signal for the two synchronous processes as
end process;
well as a rst for initialization, and a start signal to
end behavioral;; initiate one data transfer. Do not use any wait
constructions within the processes.
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Attributes Generating Periodic Waveforms
library IEEE;
attribute function use IEEE.std_logic_1164.all; Z
time (ns)
signal’event
’event function returning a Boolean value entity Periodic is
signifying a change in value on this signal port(Z:
port out std_logic); 0 10 20 30 40 50
signal’active
’active function returning a Boolean value end Periodic;
signifying an assignment made to this architecture behavioral of Periodic is
signal (may not be a new value) begin
signal’last_event
’last_event function returning the time since the process
begin
last event Z<=‘0’, ‘1’ after 10 ns,
ns ‘0’ after 20 ns,
ns ‘1’ after 40 ns;
ns
signal’last_active
’last_active function returning the time since the wait for 50 ns;
ns
signal was last active end process;
signal’last_value
’last_value function returning the previous value end behavioral;;
of this signal
signal’left
’left returns the leftmost value of signal in library IEEE; reset
its defined range use IEEE.std_logic_1164.all; phi1
signal’right
’right returns the rightmost value of signal phi2
entity TwoPhase is
in its defined range port(phi1,phi2,reset:
port out std_logic);
end twoPhase; 0 10 20 30 40 50 60
signal’hight
’hight returns the highest value of signal
time (ns)
in its defined range architecture behavioral of TwoPhase is
signal’low
’low returns the lowest value of signal begin
in its defined range reset_process: reset<=‘1’, ‘0’ after 10 ns;ns
clock_process: process
signal’ascending
’ascending returns true if signal has an ascending begin
range of values phi1<=‘1’, ‘0’ after 10 ns;
ns
signal’length
’length returns the number of elements in the phi2<=‘0’, ‘1’ after 12 ns,
ns ‘0’ after 18 ns;
ns
wait for 20 ns;
ns
array signal end process;
end behavioral;;
JMM v1.5 JMM v1.5
page 22
Modeling Finite State Machines Exercises vlsi21: FSM
reset
outputData
inputData state state
transition register output
process enable process outSig0 Ex409 (difficulty: easy): Write a VHDL model for
outSig1 a traffic light controller. Use a Moore type FSM.
outSig2
clk The signal carPresent indicates cars running on the
main street which always have priority. If no cars
architecture behavioral of MooreFSM is
are present on the main street, the secondary street
type StateType is (MyState,YourState,InitState); gets green lights.
signal state : StateType;
signal outputData: std_logic_vector(5 downto 0);
begin output_process: process(state)
process OrangeState
begin
orange
carPresent
green
transition_process: process(reset,clk)
process case state is
red
begin when MyState => main 0 1 0
second 1 0 0
if (reset = ‘0’) then outputData<=“01—00”; carPresent
state <= InitState; when YourState =>
GreenState RedState1
elsif rising_edge(clk) then outputData<=“00100-”;
orange
orange
green
green
case state is when InitState =>
red
red
when MyState => outputData<= “100100”; main 0 0 1 main 1 0 0
state<=YourState; when others => second 1 0 0 second 0 0 1
when YourState => outputData<=“000000”; carPresent
if (inputDataSignal = ‘1’) then end case;
case
state<=MyState; end process;
process RedState2
orange
end if;
if
green
carPresent
red
when others => null;
null outSig0<=outputData(0); reset main 1 0 0
end case;
case outSig1 <=outputData(1); second 0 1 0
end if;
if outSig2<=outputData(2);
end process;
process
end behavioral;
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chapter 5 (starter)
Modeling Structure Example: Structural Model

library IEEE;
a structural model of a system is described in terms
of interconnection of its components entity FullAdder3 is
port (in1,in2,cIn: in std_logic;
a structural model consists of 3 features: sum,cOut: out std_logic);
end FullAdder3; component behavior
component declaration
signal declaration architecture structural of FullAdder3 is described elsewhere
component interconnection component HalfAdder3
component port(a,b:
port in std_logic;
OR2 declaration sum,carry: out std_logic);
HalfAdder3
HalfAdder3 a end component;
component component
a sum z declaration
b carry b component OR2
ports port(a,b:
port in std_logic;
z: out std_logic);
end component;
component
component label
signal s1,s2,s3: std_logic;
signal
component declaration
H1 H2 interconnection
begin
HalfAdder3
HalfAdder3 HalfAdder3
HalfAdder3
s1 sum H1: HalfAdder3 port map(a=>in1,b=>in2,
map
in1 a sum a sum OR2 sum=>s1,carry=>s3);
in2 b carry b carry s2 a H2: HalfAdder3 port map
map(a=>s1,b=>cIn, component
z cOut
s3
b
sum=>sum,carry=>s2); interconnection
O3: OR2 port map(a=>s2,b=>s3,
map
cIn
O3 z=>cOut); (netlist)
netlist)
end structural;
JMM v1.5 JMM v1.5
page 24
Exercises vlsi21: Structural Model VHDL vs. Verilog:
Verilog:
library IEEE;
Structural
entity FullAdder4 is Description
Ex410 (difficulty: medium): Write a VHDL code port (a,b,cIn:in
in std_logic;
for the structural model of the FullAdder3 cOut,sum:out
out std_logic);
described in the previous transparency. Assume a end FullAdder4;
delay of 1 ns for all logic gates architecture flatStructure of FullAdder4 is
a) Write the structural VHDL code for a HalfAdder.
HalfAdder. component XOR
port(a,b:
port in std_logic; z:out
out std_logic); VHDL
b) Write the VHDL codes for the necessary logic end component;
component
gates like OR2 and others in one file component AND2
(logicgates.vhd)
logicgates.vhd) port(a,b:
out std_logic);
end component;
component
b) Write the VHDL code for FullAdder3 component OR3
c) Analyze and simulate the whole circuit. Be aware port(a,b,c:
out std_logic);
module FullAdder4
of the correct sequence of analyzing. end component;
component (a,b,cIn,cOut,sum);
signal net1,net2,net3,net4:std_logic; input a,b,cIn;
begin output cOut,sum;
u1: XOR port map (a,b,net1); wire net1,net2,net3,net4;
u2: XOR port map (cIn,net1,sum);
u3: AND2 port map (cIn,a,net2); XOR u1(net1,a,b);
u4: AND2 port map (cIn,b,net3); XOR u2(sum,cIn,net1);
u5: AND2 port map (a,b,net4); AND2 u3(net2,cIn,a);
u6: OR3 port map (net2,net3,net4,cOut); AND2 u4(net3,cIn,a);
end flatStructure; AND2 u5(net4,a,b);
OR3u6(cOut,net2,net3,net4);
endmodule
Verilog-
Verilog-HDL
JMM v1.5 JMM v1.5
page 25
VHDL vs. Verilog:
Verilog: Hierarchy, Abstraction, and Accuracy
Data Flow Description
Structural models simply describe interconnections
library IEEE;
Structural models do not describe any form of
use IEEE.std_logic_1164.all; behavior
use IEEE.std_logic_unsigned.all; Hierarchy expresses different levels of detail
entity FullAdder5 is Structural models are a way to manage large,
port (a,b,cIn:in
in std_logi;
VHDL complex designs
sum,cOut:out
out std_logic);
end FullAdder5; Modern designs have several 10 millions of gates
Simulation time: the more detailed a design is
architecture dataFlow of FullAdder5 is
described, the more events are generated and thus
signal tmp: std_logic_vector(1 downto 0);
begin the larger the simulation time will be needed.
tmp <= ‘0‘ & a + b + cIn;
cOut <= tmp(1); top level
sum <= tmp(0); FullAdder3
end behavior; module FullAdder5 (a,b,cIn,sum,cOut);
input a,b,cIn;
output cOut,sum; HalfAdder3
OR2
Verilog-
Verilog-HDL
assign {cOut,sum} = a + b + cIn;
endmodule
AND2 XOR2 bottom level
JMM v1.5 JMM v1.5
page 26
Generics More on Generics
Within a structural model there are two ways in
The VHDL language provides the ability to construct which the values of generic constants of lower level
parameterized models using the concept of generics components can be specified:
in the component declaration
entity AND2 is in the component instantiation
generic(andDelay:
generic Time);
Time
library
libraryIEEE;
IEEE;
port(a,b
port : in std_logic; z: out std_logic; If both are specified, then the value provided by the
use end AND2; generic map() takes precedence.
useIEEE.std_logic_1164.all;
IEEE.std_logic_1164.all;
entity
entityHalfAdder4
HalfAdder4isis
architecture genericDelay of AND2 is If neither is specified, then the default value
begin
generic(adderDelay:
generic
generic(adderDelay:
generic Time:=3
Time ns);
Time
Time:=3 nsns);
ns z<=a and b after andDelay;
defined in the model is used.
port(a,b
port : :ininstd_logic;
port
port(a,b std_logic;
sum,carry: end genericDelay;
sum,carry:out
outstd_logic;
std_logic; library IEEE;
end
endHalfAdder4;
HalfAdder4; use IEEE.std_logic_1164.all;
entity GenericOR is
architecture
architecturegenericDelay
genericDelayofofHalfAdder4
HalfAdder4isis generic(n:
generic positive:=2);
positive
component
componentAND2
AND2isis port(in1:
port in std_logic_vector((n-1) downto 0); z: out std_logic);
generic(andDelay:
generic
generic(andDelay:
generic Time);
Time
Time);
Time end GenericOR;
port(a,b
port : :ininstd_logic;
port
port(a,b std_logic;z:z:out
outstd_logic;
std_logic;
end
endcomponent;
component; values to generics architecture behavioral of GenericOR is
can be assigned at begin
component
componentXOR2 XOR2isis different locations process(in1)
process
generic(xorDelay:
generic
generic(xorDelay:
generic Time);
Time
Time);
Time variable sum: std_logic:=‘0‘;
port(a,b
port
port(a,b
port : : in std_logic;z:z:out
in std_logic; outstd_logic;
std_logic; begin
end
endcomponent;
component; sum:=‘0‘;
for i in 0 to (n-1) loop
begin
begin no semi column sum:=sum or in1(i);
C1:
C1:XOR2
XOR2generic map(12
map(12ns)
genericmap
map ns port
nsns) map(a,b,sum);
portmap
map(a,b,sum);
map needed end loop;
loop
C2:
C2:AND2
AND2generic map(adderDelay)
map(adderDelay)port
genericmap
map map(a,b,carry);
portmap
map(a,b,carry);
map z<=sum;
end
endgenericDelay;
genericDelay; end process;
process
end behavioral;
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page 27
Exercises vlsi21: Hierarchy, Generic Configuration
Ex411 (difficulty: medium): Write a VHDL code Structural models may employ different levels of
of an 8 bit ALU based on the definitions made in abstraction
Ex402 with the Simple1BitALU.
Each component in a structural model may be
a) Write a behavioral VHDL code for ALU8b.vhd described as a behavioral or a structural model
b) Write the structural VHDL code for ALU8 in one
file ALU8s.vhd. Assume a delay of 1 ns for all Configuration allows stepwise refinement in a
logic gates. What is the worst case delay of the design cycle
ALU8. Configuration represents resource binding
Description-
Description-synthesis design method
Ex412 (difficulty: easy): Write a VHDL code of
an n bit register with reset and enable inputs
(NbitRegister.vhd).
NbitRegister.vhd). Configuration associates
an architecture
description to each
FullAdder3 component:
- behavioral or
- structural for
OR2 HalfAdder3
FullAdder3
AND2 XOR2
JMM v1.5 JMM v1.5
page 28
Configuration: Component Binding Configuration: Default Binding Rules
Example of binding architectures: A bit-

bit-serial adder
To analyze different implementations, we simply
one of the different architectures must be change the configuration, compile and simulate.
bound to the component C1 for simulation
When newer component models become available we
entity is not bound as interfaces do not change bind the new architecture to the component
architecture gataLevel of Comb is Default binding rules:

- - -
if the entity name is the same as the component
name, then this entity is bound to the component
C1
architecture lowPower of Comb is if there are different architectures in the working
a Comb sum
(combinational
- - - directory, the last compiled architecture is bound to
b
logic)
logic) carry the entity
C2
Dff
q d architecture highSpeed of Comb is
carryIn - - -
clk
rst clock
reset
architecture behavioral of Comb is
- - -
JMM v1.5 JMM v1.5
page 29
Example: Configuration Exercises vlsi21: Configuration
C1 highSpeed
in1 Comb
Ex 413 (difficulty: easy): Write a VHDL code of
sum
in2 (combinational the bit-
bit-serial adder shown in the previous
logic) transparency SerialAdder.vhd
carryIn carry
C2 MyDff
a) Construct a model for the two components Comb
q d and MyDff and place them both in your WORK
clk
rst clock
library (don‘t use the library MyLibrary yet).
configuration name behavioral b) Adapt the configuration, compile and simulate it.
it.
reset entity name
(used for simulation)
library name
Ex414 (difficulty: medium): Consider the circuit
configuration CFG_HighSpeed of SerialAdder is entity name shown below (ConfigExample
(ConfigExample).
ConfigExample). Construct a
for structural
architecture name structural model comprised of three components.
for C1: Comb use entity WORK.Comb(highSpeed); However in the configuration use only two
end for;
for components by using a n-
n-input AND gate.
for C2: Dff use entity MyLibrary.MyDff(behavioral)
generic map(gateDelay=>5
map ns)
port map(my_clk=>clk,
map my_d=>d,
my_q=>q, my_rst=>rst); if different component i1
end for;
for than described in i2 &
entity is used, then i3
end for;
for I/O mapping must ≥1 o1
be declared.
end CFG_HighSpeed; &
JMM v1.5 JMM v1.5
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chapter 6 (starter)
Subprograms, Packages and Libraries Functions

Functions are used to compute a value based on the
VHDL provides mechanisms for structuring values of the input parameters. Functions are
programs, reusing software modules, and otherwise placed in declarative parts. Example of function
managing design complexity. definition:
function rising_edge (signal

signal clock: in std_logic) return boolean;
boolean
Packages contain definitions of procedures and
functions that can be shared across different VHDL
models. Functions cannot modify parameter values
Packages may contain user defined data types and (procedures can). Example of function call:
constants and can be placed in libraries.
rising_edge(clk)
Summary: procedures, functions, packages and Functions execute in zero simulation time, thus
libraries provide facilities for creating and wait statements cannot exist in functions.
maintaining modular and reusable VHDL programs. Parameters are restricted to be of mode in.
mode not necessary
function rising_edge (signal
signal clock: std_logic) return boolean is
variable edge: boolean:=false
boolean false;
false
begin
edge:=(clock= ‘ 1‘ and clock‘event
‘event);
‘event
return(edge);
return
end rising_edge;
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Example: Type Conversion Function Procedures
with Functions Procedures are subprograms that can modify one or
more of the input parameters. Example of procedure
As VHDL is a type sensitive language, type declaration reading from a file f:
conversions are quite often necessary.
procedure read_v1d (variable
variable f: in text; v: out std_logic_vector);
note: size is not declared
if the class of the procedure parameters is not
function to_bitvector(svalue: std_logic_vector) return bit_vector is
explicitly declared, then the following rules apply:
variable outvalue: bit_vector(svalue‘length
‘length-1
‘length downto 0); parameters of mode in are assumed to be of class constant
begin parameters of mode out or inout are assumed to be of class
for i in svalue‘range
‘range loop
case svalue i is
variable
when ‘0‘ => outvalue i:=‘0‘; Variables declared within a procedure are initialized
when ‘1‘ => outvalue i:=‘1‘;
when others => outvalue i:=‘0‘; on each call to the procedure and their values do not
end case;
case persists across invocations of the procedure.
end loop;
loop
end to_bitvector; Signals cannot be declared within procedures
Poor programming: Procedures declared within
process can make assignments to signals
corresponding to the ports of the encompassing
Many conversion procedures as well as resolution entity.
functions can be found in std_logic_1164 or
std_logic_arith libraries and others. Have a look at Procedure call:
$SYNOPSYS/packages/IEEE/src
$SYNOPSYS/packages/IEEE/src/ src/ Dff(clk=>clk,reset=>reset,d=>s2,q=>s1,qbar=>open
open);
open
JMM v1.5 JMM v1.5
page 32
Example: Procedure Overloading
library IEEE;
IEEE
entity CPU is A very useful feature of the VHDL language is the
port(di:
port out std_logic_vector(31 downto );
addr: out std_logic_vector(2 downto 0);
ability to overload a subprogram or an operator.
r,w: out std_logic; Imagine writing different Flip-
Flip-Flop models with no
do: in std_logic_vector(31 downto 0); and with asynchronous inputs and with different
s: in std_logic);
end CPU;
argument types. With the overloading feature only
one single Flip-
Flip-Flop name can be used.
architecture behavioral of CPU is Example for Dff calls:
procedure Mread(address: in std_logic_vector(2 downto 0);
signal r: out std_logic;
signal s: in std_logic; Dff(
Dff(clk,d,q,qbar);
signal addr: out std_logic_vector(2 downto 0);
signal data: out std_logic_vector(31 downto 0)) is Dff(
Dff(clk,d,q,qbar,
clk,d,q,qbar,reset,
reset,clear);
begin
addr<=address; procedure Mwrite(address: in std_logic_vector(2 downto 0); From the type and number of arguments we can tell
r<=‘1‘; signal data: in std_logic_vector(31 downto 0); which procedure we meant to use.
wait until s=‘1‘; signal addr: out std_logic_vector(2 downto 0);
data <= do; Note that in std_logic_1164.vhd the boolean
signal w: out std_logic;
r<=‘0‘; signal di: out std_logic_vector(31 downto 0)) is functions and, or, etc have been defined for
end Mread; begin std_logic types, the functions +,*, etc have been
addr<=address; defined for certain predefined types of the language
w<=‘1‘; such as integer. See also std_logic_arith package.
wait until s=‘1‘;
begin
di <= data; function “*“(arg1,ar2: std_logic_vector) return std_logic_vector;
std_logic_vector;
w<=‘0‘;
-- CPU behavioral end Mwrite;
-- description function “+“(arg1,ar2: singed) return signed;
end behavioral;
JMM v1.5 JMM v1.5
page 33
Packages Example: Package Declaration
Locally related functions and procedures can be
package std_logic_1164 is
grouped into packages, and thus easily be shared
among designs and people. type std_ulogic is (‘U‘, -- uninitialized
‘X‘, -- forcing unknown
package MyLibraryPackage is ‘0‘, -- forcing 0
-- ‘1‘, -- forcing 1
-- type declarations
package declaration ‘Z‘, -- high impedance
-- function declarations ‘W‘, -- weak unknown
-- procedure declarations similar to VHDL entity ‘L‘, -- weak 0
-- defines interfaces ‘H‘, -- weak 1
end MyLibraryPackage; ‘-‘ -- don‘t care);
type std_ulogic_vector is array (natural
natural range <>) of std_ulogic;
subtype std_logic is resolved std_ulogic;
package body MyLibraryPackage is
-- package body type std_logic_vector is array (natural
natural range <>) of std_logic;
-- functions
-- procedures similar to VHDL architecture function “and“ (l,r: std_logic_vector) return std_logic_vector;
-- defines behavior function “and“ (l,r: std_ulogic_vector) return std_ulogic_vector;
end MyLibraryPackage;
-- rest of package declaration
end std_logic_1164;
package declaration needs to be analyzed first, and
then package body can be analyzed.
Packages are used as libraries and referenced within
VHDL design units via the use clause.
JMM v1.5 JMM v1.5
page 34
Synopsys tools on unix workstations
Libraries Example: Libraries and Packages

/home/MyHome/ design environment .synopsys_vss.setup
- VHDLdesign/
- WORK/ all source VHDL design files
library: - lib/ all compiled designs
Each design unit - entity, architecture, package - is MyLibrary - src/
analyzed (compiled) and placed in a design library.
library. compiled package: MyPackage
.synopsys_vss.setup source file: MyPackage.vhd

Libraries are generally implemented as directories
and are referenced by a logical name. DEFAULT: ./WORK
In VHDL the libraries STD and WORK are MyLibrary : ./lib

implicitly declared. use = . ./src
timebase = ns
WORK is the working design library normally
placed in a local directory. MyPackage.vhd in a unix shell:
package MyPackage is analyze the package MyPackage
Once a library has been declared, all of the -- analyze the design MyVHDLdesign
functions, procedures and type declarations of a end MyPackage; cd /home/MyHome/VHDLdesign
package can be accessed. gvan –w MyLibrary src/MyPackage.vhd
package body MyPackage is
all functions, procedures, typed --
are visible end MyPackage; gvan MyVHDLdesign.vhd
library IEEE;
MyVHDLdesign.vhd components
only the „xnor
„xnor“
xnor“ function is visible can also be
library MyLibrary;
library IEEE; use MyLibrary.MyPackage.all; library placed into
use IEEE.std_logic_1164.xnor; visibility must be established -- use MyLibrary.all; libraries
library MyLibrary
for each design unit – entity-
entity- WORK
separately entity MyVHDLdesign is /home/MyHome/VHDLdesign/lib
... /home/MyHome/VHDLdesign/WORK
JMM v1.5 JMM v1.5
page 35
Exercises vlsi21: Libraries & Packages Exercises vlsi21: Packages
Ex415 (difficulty: medium): The small circuit Ex417 (difficulty: medium): The bit-
bit-serial adder of
ConfigExample from exercise Ex414 shall be exercise Ex413 shall we rewritten using a
rewritten by using the components OR2 and ANDn procedure call for the Dff instead of a component
from the library MyLibrary. (SerialAdder2.vhd). Place the procedure into a
a) Write the VHDL file MyComponents.vhd holding package MyPackage and analyze it into the library
the two components OR2 and ANDn and compile it MyLibrary. Verify the functionality.
into the library MyLibrary.
b) Rewrite the ConfigExample circuit using only
library elements and call it LibraryExample.vhd, C1 highSpeed
compile and simulate it.
in1 Comb sum
i1 ANDn in2 (combinational
i2 & OR2 logic)
logic)
i3 carry
ANDn ≥1 o1 carryIn
Dff
q d
& library
clk
rst clock MyLibrary
Ex416 (difficulty: medium): Write the VHDL behavioral
reset
package MyPackage with the functions OneCounter
(counting ‚1‘) and ParityGenerator should accept
std_logic_vectors or bit_vectors of any size),
size), and
analyze it into the library MyLibrary. Use the
defined functions in your design PackageExample to
show its functionality.
JMM v1.5 JMM v1.5
page 36
VHDL vs. Verilog:
Verilog: Data Types VHDL vs. Verilog:
Verilog: Operators
VHDL Verilog-
Verilog-HDL Operator type function VHDL Verilog
arithmetic a+b + +
type driven language arrays a-b - -
a*b * *
predefined data types run-
run-time constants: a/b / /
in packages: parameter
a- b*n a div b mod %
character, integer, real, continuous driven
bit, std_logic, textio,
textio, ... a- (a/b)*b rem
nets: wire, tri, ... logical a and b and &
enumerate types
triggered assignments: a or b or ¦
arrays reg,
reg, integer, real, ... not(a and b) nand ~&
records a exor b xor ^
shift logic srl,sll >>
pointers
shift arith. sra,sla
rotate ror, rol
reduction, & {a,b}
concatenation
replication {4{a}}
relational > > >
>= >= >=
/=
JMM v1.5 JMM v1.5
page 37
VHDL vs. Verilog:
Verilog: VHDL vs. Verilog:
Verilog:
Sequential Structures Parallel Structures
-- in an architecture
-- inside an architecture ...
... variable inp: std_logic_vector (7 downto 0);
);
signal outp,cout:std_logic_vector (7 downto 0);
);
variable inp: std_logic_vector (7 downto 0);
); VHDL
variable outp,cout:std_logic_vector (7 downto 0);
);
VHDL p1: process (clk)
process (clk) begin parallel executed
begin if (clk’even
’event
’even and clk = ‘1’) then statements
if (clk’even
( ’event
’even and clk = ‘1’) then outp <= outp + inp;
outp := outp + inp; cout <= outp + 1;
cout := outp + 1; end if;
end process; /* in a module */
end if;
...
end process;
p2: process (reset) wire [7:0]] inp;
...
/* inside a module */ begin reg [7:0]] outp, cou;
... if (reset = ‘0’) then ...
wire [7:0]] inp; outp <= “00000000“; always @(@(posedge
posedge clk))
reg [7:0]] outp, cou; end if; fork
sequentially executed statements end process; outp = outp + inp;
...
always @(@(posedge
posedge clk)) ... cout = outp + 1;
begin join
outp = oupt + inp;
parallel
cout = outp + 1; executed blocks always @(reset)
@( )
end two drivers if (!!reset)
Verilog-
Verilog-HDL ...
Verilog-
Verilog-HDL outp = 8’b0;
...
JMM v1.5 JMM v1.5
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VHDL vs. Verilog:
Verilog: Assignments VHDL vs. Verilog:
Verilog:
architecture ex1 of AssignExample is Sequential Logic
signal x1, y1, y2, z1, z2:
std_logic_vector (7 downto 0);
); VHDL
variable x2: std_logic_vector (7 downto 0);
); library IEEE; register with
... use IEEE.std_logic_1164.all;
begin package MyDefinition is asynchronous reset
p1: process (clk) type vector16 is array (15 downto 0) of
begin signal assignment std_logic;
end MyDefinition; VHDL
if (clk’even
( ’event
’even and clk = ‘0’) then variable assignment
x1 <= y1;
library IEEE;
y1 <= x1;
z1 <= y1 after 12ns;
ns; Verilog-
Verilog-HDL use work.MyDefinition.all;
end if;
end process; module AssignExample
entity AsynRegister is
wire [7:0]] v,y2,z2;
port (clk,rst: in std_logic;
p2: process (y2) reg [7:0]] x1,y1,z1,x2; Verilog-
Verilog-HDL
a: in vector16; z: out vector16);
begin ...
end AsynRegister;
x2 := y2; always @(
@(posedge
posedge clk)) module AsynRegister(clk,rst,a,z);
y2 <= x2; fork input clk,rst;
architecture DemoExample of AsynRegister is
z2 <= y2 after 12ns; x1 = y1; input [15:0]] a;
begin
end process; y1 = x1; output [15:0]] z;
process (clk, rst);
end ex1; z1 #(12) = y1;
begin
join always @(
@(posedge
posedge clk))
if (rst = ‘0’) then
before the falling edge of clk:
clk: z <= vector16’(others
others => ‘0‘); if (rst == 1’b0)
assign x2 = y2; z = 16’b0;
x=1, y=2, z=3 assign y2 = x2;
elsif (clk’even
’event
’even and clk = ‘1’) then
else
12ns after falling edge of clk:
clk: assign #(12) z2 = y2;
z <= a;
z = a;
x= y= z= ? end if;
endmodule endmodule
end process;
MicroLab, VLSI-21 (77/95) end DemoExample; MicroLab, VLSI-21 (78/95)
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“Dataflow” Modeling VHDL Example: Behavioral Modeling
library IEEE;
use IEEE.std_logic_1164.all; library IEEE;
entity Demux
Demux2x4
emux2x4 is port( use IEEE.std_logic_arith.all;
IEEE.std_logic_arith.all;
a,b,enable: in std_logic;
z: out std_logic_vector(0 to 3);); entity Demux2x4 is port(
end Demux
Demux2x4;
emux2x4; a,b,enable: in std_logic;
z: out std_logic_vector(0 to 3););
architecture dataflowof
dataflowof Demux
Demux2x4
emux2x4 is end Demux2x4;
signal abar,bbar:
abar,bbar: std_logic;
begin architecture behavioral of Demux2x4 is
z(3) <= not(a and b and enable); begin
z(0) <= not(abar and bbar and enable); process(a,b,enable)
abar <= not a; variable abar,bbar:
abar,bbar: std_logic;
z(2) <= not(a and bbar and enable); begin
abar <= not a; abar := not a; local variables (separate
z(1) <= not(abar and b and enable); bbar := not b; copies for each instance
end dataflow;
dataflow; if (enable = ‘1’) then of Demux
Demux2x4)
emux2x4)
z(3) <= not(a and b);
Process statements z(2) <= not(a and bbar);
bbar);
can be compiled so z(1) <= not(abar and b);
behavioral simulations z(0) <= not(abar and bbar);
bbar);
All the signal assignment statements (“<=“) happen can be quite fast.
concurrently after some specified delay which defaults else
z <= “1111”;
to 1 “delta”, an infinitesimally small delay. Note that end if;
concurrent statements are always “running” so whenever end process;
A, B or ENABLE change then ABAR, BBAR, and Z(0 to 3) end behavioral; vector constant
will also change after some delay.
The delay in assigning a signal its new value means that Statements within a process are executed sequentially,
the following statement is meaningful (it generates a like a program. The process is scheduled for execution
periodic waveform): after any events are processed for variables on its
CLK <= not CLK after 10 ns; sensitivity list. Values of local variables are maintained
between executions.
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page 40
Logic Synthesis
Synthesis
Z <= (A and B) or C; if (SEL = ‘1’) then Z <= B;
else Z <= A;
A end if;
Idea:
Idea: once an behavioral model has been finished why not B
use it to automatically synthesize a logic implementation in C Z B 1
Z
0
much the same was as a compiler generates executable code A
A
from a source program? B SEL
C Z
a.k.a. “silicon compilers” B
Synthesis programs process the HDL then SEL Z
A
signal x,y,sum: std_logic_vector(3 downto 0);

sum <= unsigned(x) + unsigned(y);
infer logic and state elements
SUM(0) SUM(1) SUM(2) SUM(3)
perform technology-
technology-independent optimiz
optimizations
(e.g., logic simplification, state assignment) full full full full
0 adder adder adder adder NC
map elements to the target technology
perform technology-
technology-dependent optimizations X(0) Y(0) X(1) Y(1) X(2) Y(2) X(3) Y(3)
(e.g., multi-
multi-level logic optimization, choose
gate strengths to achieve speed goals) process(word)
variable result: std_logic;
Synopsys,
Synopsys, Inc. is the current leader in begin WORD(3)
PARITY
result := ‘0’;
providing synthesis tools and synthesizable for j in 0 to 3 loop
HDL modules. result := result xor word(j); WORD(2)
end loop;
parity <= result;
WORD(1)
end process; WORD(0)
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Further Reading Test Bench /1
avoid interactive simulation, because it can never

be used again
test benches reduce total simulation development
time
test benches are used to verify designs during
stepwise refinement
test bench methodology bridges simulation with
automatic test equipment (ATE)
ISBN 0-
0-13-
13-181447-
181447-8 ISBN 0-
0-7923-
7923-9472-
9472-0
Also: I can relax

my test bench does
D. Perry, VHDL, Second Edition, McGraw Hill, 1993 everything automatically
see VHDL tutorials at I3S-

I3S-CD or on the web
http://www.microlab.ch/academics/courses/vlsi/g.html
http://www.microlab.ch/academics/courses/vlsi/g.html
don‘t forget to study the CBT tutorial on VHDL
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page 42
Test Bench /2 Test Bench in Design Flow
design of
compare a test bench with MicroLab-
MicroLab-I3S: VHDL model
there are chips and PCBs needed to be tested
simulation of test bench
there is a nice measurement equipment
VHDL model inp VHDL out
there are skilled and hard working people FPGA synthesis model
there are no signals coming or going to the outside of the place & route
lab
FPGA test
(debugger)
Test Bench test bench synthesis of
test machine logic model
inp FPGA out test bench
chip simulation of
control response logic model inp out
and generation
stimulus and place & route
generation verification physical design
simulation of test bench

device under test (DUT) extracted model inp out
why do we need MicroLab

if my test bench does the ASIC fabrication
job as well test bench
test machine
prototype test
(ASIC) inp ASIC out
chip
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VHDL Test Bench Test Bench - Test Cycle
use IEEE.std_logic_1164.all
entity TestBench is test bench has
end TestBench; no inputs, no outputs
architecture sample of TestBench is design strictly synchronous circuits
signal clk, a: bit;
signal b: bit;
cycle
cycle based test benches
component MyCircuit
port(clk,a:in
port in bit; b: out bit);
end component;
component
begin test cycle
call of device under test
DUT: MyCircuit port map (clk,a,b); (DUT)
process apply input patterns capture output response
begin clk generation
clk <= ‘0’, ‘1‘ after 20 ns, ‘0‘ after 70 ns;
wait for 100 ns;
end process;
TestPatternGenerator: block clock
begin test pattern generation
process on a cycle by cycle basis
begin
a <= ‘0’; -- test cycle 1 input valid
wait for 100 ns;
ns
a <= ‘1’; -- test cycle 2
wait for 100 ns;
ns response pattern output stable stable stable
... verification not
end process; yet implemented!
end block;
end sample;
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ProTest Test Machine Conclusions
test bench controls CAD simulator and test machine HDLs are very useful for behavioral hardware
low cost rapid prototyping and test system system descriptions
abstract models do not precisely reflect the reality
restriction to synthesizable coding is necessary
technology independency opens the possibility to
fast FPGA prototyping
test benches increase chip quality and highly
decrease simulation time
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Coming Up...
Exercises: VLSI-
VLSI-21: Test-
Test-Bench
CAD Ex418: Test-

Test-Bench (difficulty: easy) Instead Next topic…
of interactive simulation or writing macros for CAD exercises and mini FPGA projects PWM, blackjack
dealer, simple microprocessor, etc
interactive simulation, it is state-
state-of-
of-the-
the-art to use
test-
test-benches for simulation and chip test. Write a
test bench file tb_SerialAdder2.vhd for the
previous exercise Ex417. Generate the clock signal Readings for next time...
with a process and write sequential test cycles for VHDL tutorials
the input signals. Be aware that the test-
test-bench has
A Prototype Test System for ASICs and FPGAs with a Tight
no input and output signals, but calls the unit-
unit- Link to VHDL and Verilog-
Verilog-HDL Based CAD Simulators,
under-
under-test (UUT) and generates all stimuli. DATE’99. Design Automation and Test Engineering in
Europe Conference, Jacomet et. al. (see on the MicroLab
web)
On a Development Environment for Real-
Real-Time information
test bench
Processing in System-
System-on-
on-Chip Solutions, SBCCI’01,
inp VHDL out IEEE 14th Symposium on Integrated Circuit and System
model
Design, Brazil Sept. 2001, Jacomet et. al. (see on the
MicroLab web)
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page 46
Project 1: De-
De-Bounce Circuit Project 2: Traffic Light
CAD Ex440_1: De- De-Bounce Project (difficulty: CAD Ex440_2: Traffic Light (difficulty: easy;
easy; time: medium): Design of a push button de-de- time: medium): Redesign and implement your
bounce circuit. Start with a FSM design and traffic light design from exercise Ex409 into an
synthesize the logic manually (only 1 flip-
flip-flip is FPGA on the GECKO main board. Use the push
necessary). Code and simulate the VHDL design. buttons and LEDs from the GECKO I/O Expansion
For example, on the GECKO I/O Expansion board board. The clock oscillator frequency of the GECKO
are different switches and push buttons available. main board is 13.56 MHz. The time between a
The push buttons schematic is as follows. De-
De- change of the traffic lights is 1.5 seconds. The
bounce the push-
push-buttons. main street has a minimum green phase time of 6
seconds.
draw the timing diagram of the signals SWx and
main secondary
SWx_inverted when switching
street street
develop the finite state machine to generate the signal
button
develop the schematic of the circuitry
carPresent
simulate your VHDL code including the push button SW
Vdd Traffic Light
Circuitry 3
SWx reset 3
SWx_inverted
de-
de-bounce clock
button
SWx circuitry
SWx button
released ‘0‘
pressed ‘1‘
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page 47
Project 3: Stop Watch
CAD Ex440_3: Stop Watch (difficulty: easy; time:
medium): Design an implement a stop watch into an
FPGA on the GECKO main board. Use the push
buttons and 7-
7-segment LCD from the GECKO I/O
Expansion board. The clock oscillator frequency of
the GECKO main board is 13.56 MHz. The stop
watch resolution is 1/100 seconds, its maximum
value is 99.99 seconds for the 4 digit display.
Show the value “End” on the display when the
watch exceeds 99.99 seconds. Use only one single
push button for “start” and “stop”.
start/stop
Stop Watch 29
reset Circuitry
clock
MicroLab, VLSI-21 (95/95)
JMM v1.5
page 48

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chapter 1

VLSI Systems Design The Need for HDLs

It seems I goals include area, power, throughput, latency,

partition the project into modules with well-

A behavioral model serves as an executable specification

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easier to explore ideas in HDLs than in logic gates textual HDLs

first HDLs were introduced in late 70s time-

MicroLab, VLSI-21 (3/95) MicroLab, VLSI-21 (4/95)

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Introduction to VHDL & Verilog cont. Signals, Delays, Events, Concurrency

language features digital systems in contrast to software systems are

MicroLab, VLSI-21 (7/95) MicroLab, VLSI-21 (8/95)

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MicroLab, VLSI-21 (9/95) MicroLab, VLSI-21 (10/95)

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Entity Exercises Ex401: Entity

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architecture describes the internal behavior of a

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The operation of digital systems is inherently

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MicroLab, VLSI-21 (19/95) MicroLab, VLSI-21 (20/95)

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Exercises vlsi21: Conditional The Process Construct #1

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Events are variable or signal changes.

MicroLab, VLSI-21 (29/95) MicroLab, VLSI-21 (30/95)

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architecture behavioral of Multiplier is

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dataIn Shift dataOut Upon initialization all processes are executed at

MicroLab, VLSI-21 (35/95) MicroLab, VLSI-21 (36/95)

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Modeling Structure Example: Structural Model

MicroLab, VLSI-21 (47/95) MicroLab, VLSI-21 (48/95)

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MicroLab, VLSI-21 (55/95) MicroLab, VLSI-21 (56/95)

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Example of binding architectures: A bit-

architecture gataLevel of Comb is Default binding rules:

MicroLab, VLSI-21 (57/95) MicroLab, VLSI-21 (58/95)

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MicroLab, VLSI-21 (59/95) MicroLab, VLSI-21 (60/95)

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Subprograms, Packages and Libraries Functions

function rising_edge (signal

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