SyncnronousSequential tircuits

SYNCHRONOUSCOMPONENTS
AsYNCHRONOUS QRCUITS: lATCHES

SRLATCH:
s R Qt+l Qt+l
R
Q o o Qt Qt

o 1 o 1

s Q
1 o 1 o
restricted
1 1 o º_)

s
SR Latch
R
s Q
Q
R Q
Q

SR LATCHWITH ENABLE:

R
E s R Qt+l Qt+l
o X X Qt Ot
Q
1 o o e, Ot
E
1 o 1 o 1

Q 1 1 o 1 o
s
1 1 1 o o

D LATCHWITH ENABLE:

• This is essentially an SR Latch, where R = not(D), s=D

D
E O Qt+l

o X Or.
1 o o
1 1 1

1
SVNCHRONOUS ORCUITS: FUP FLOPS

• Flip flops are made out of:

o A Latch with an enable input.
o An Edge detector circuit.

• The figure depicts an SR Latch, where the enable is connected to the output of an Edge Detectorarcuit. The input to the
Edge Detector is a signal called 'clocN. A clock signal is a square wave with a fixed frequency.

clock
1 1

~
T~Period Frequency = 1/T
SR Flip Flop
R

Edge _jl JLE

Detector

s _jort_

• The edge detector circuit generates short-duration pulses during rising (or falling) edges. These pulses actas short-time
enables of the Latch.
• The behavior of the flip flops can be described as that of a Latch that is only enabled during rising (or falling edges).

• Depending on what type of edge we are detecting, flip flops can be classified as:
o Positive-edge triggered flip flop: The edge detector circuit generates pulses during rising edges.
o Negative-edge triggered flip flop: The edge detector circuit generates pulses during falling edges.
o Dual-edge triggered flip flop: The edge detector circuit generates pulses during both rising and falling edges. Current
FPGA technology does not support dual-edge triggered flip flops.

s Q s Q
clock- clock
R Q R Q
Positive Negative
edge-triggered edge-triggered

FLIP FLOP TYPES

SR Flip Flop
clock s R Ot+1 Ot+1

_J o o Ot Ot s Q
_J o 1 o 1 clock

_J 1 o 1 o R
Q

_J 1 1 o o
Excitation Equation:

Qt+t =SR+ Q,SR = R(S + Q,f) = R(S + f)(S + Q,) = RS + RQ, (on the edge)

2
D Flip Flop
clock D Qt+l D Q

_J o o
clock
Q
_J 1 1
D Flip Flop

1 D

Edge
Detector

1 ----1
Excitation Equation: Q,+1 = D (on the edge)

T Flip F1op
clock T Ot+1
D Q T Q-

clock
q clock

Q Q

Excitation Equation: Qm = TeQ, (on the edge)

JK Flip Flop
cloclt J I(
Qt+l
J
J Q _J o o Qt
D Qt-t---~
L.-,/ clock _J o 1 o
cloclt K Q _J 1 o 1
. _ _Q
. t-+--+--
_J 1 1 Qt

Excitation Equation: Q,+1 = JQ, + KQ, (on the edge)

SYNCHRONOUSAND ASYNCHRONOUS INPUTS

Synchronous Inputs
• Typically, flip flops only change their outputs on the rising (or falling edge). Usually, a change on the inputs forces a change
on the outputs. These inputs are known as synchronous inputs, as the inputs' state is only checked on the rising (or falling)
edges. Example: Input D of a D flip flop, Inputs J, K of a JK flip flop.

Asynchronouslnputs prn
• However, in many instances, it is useful to have inputs that force the outputs to a value
immediately, disregarding the rising (or falling edges). These inputs are known as asynchronous o D
inputs. Common asynchronous inputs are prn and clrn (they can be active-low ar active high)
• The figure depicts a D Flip Flop with two asynchronous inputs:
o prn: Preset (active low). When prn = O .._. Q = 1. clock
o clrn (sometimes called resetn): Clear (active low). When clrn =O .._. Q = O. Q-
o If prn and clrn are both O, usually clrn is given priority.
• A Flip flop can have more than ene asynchronous inputs, or nene.

3
PRACTICE EXERCISES

l. C.Omplete the timing diagram of the circuit shown below:

clk

clrn _¡J
D Q Q
D
D
E
E

clk -------1"'> Q
clrn Q ---:

2. C.Omplete the VHDL description of the circuit shown below:

library ieee;
use ieee.std_logic_ll64.all;

entity circ is D Q Q
port (a, b, s, clk, clrn: in std_logic;
q: out std_logic);

end circ;

architecture a of circ is clk Q

begin clrn
-- ???

end a;

3. C.Omplete the timing diagram of the circuit shown below. If the frequency of the signal clock is 25 MHz, what is the frequency
(in MHz) of the signal Q?
clrn
clock
'1' T Q
clrn _¡J
clock
Q Q ,'
1

4. C.Omplete the timing diagram of the circuit whose VHDL description is shown below:
library ieee; elsif (clk'event and clk 'l') then
use ieee.std_logic_l164.all; if x = '1' then
qt <= not (qt);
entity circ is end if;
port ( clrn, x, clk: in std logic; end if;
q: out std_logic); - end proccss;
end circ; q <= qt
cnd a;
architecture a of circ is clk
signal qt: std logic;
1
begin - 1

process (clrn, clk, x)

begin clrn _j_J
if clrn = '0' then
qt <= '0';
X

Q -
4
5. Complete tne timing diagram of the circuit shown below:

a Full Adder 8
X s r

b
y FA
cin cout ._
- D Q ._

clk -
t> Q

e lrn 1 8
---..
1

6. Complete tne VHDL description of the synchronous sequential circuit whose truth table is shown below:

library ieee;
use ieee.std_logic_ 1164.all; clrn clk A B Qt+l

entity circ is 1 _J o o 1
port A, B, C: in std logic;
clrn, clk: in std_logic; 1 _J o 1 e
q: o t std_logic);
end circ;
1 _J 1 o Qt
architecture a of circ is
begin 1 _J 1 1 Q~
-- ???
end a; o X X X o

7. Complete tne timing diagram of the circuit shown below:

clk
J Q
clk
clrn _J
K Q
X

clrn y

X Q ---..
1

8. Complete the timing diagram of the circuit shown below:

clrn
Q
º---- ---1 o
clk -- ~
Q

Q
clrn

o
'

JJTlJ
1
1 1

1
1

L
1 1

- ..... .... 1
1
1
1
1

1
Latch Q~
Q 1 1

o Q 1
1
1
QL~
1 1
E Q 5
SYNCHRONOUS 0RCUITS: REGISTERS

n-bit Register:This is a collection of 'n' D·type flip flops,

where each flip flop independently stores one bit. The flip
flops are connected in parallel. They also share the same
resetn and clock signals.

Q
n Q

clk

n-bit shift: registers:This is a collection of 'n' D-type flip flops, connected serially. The flip flops share tne same resetn and
clock signals. The serial input is called 'din', and the serial output is called 'dout'. The flip flop outputs (also called the parallel
output) are called Q = Qn-i Qn_2 ••• Q0• Depending on how we la bel the bits, we can have:
• Rightshift: register:The input bit moves from the MSB to the LSB, and
• Left:shift:register':The input bit moves from the LSB to the MSB.
RIGBT SBIFT REGISTER:
rcseln ----.
din~ din dout dout
dout
clk

.... N M
1 1 1e
e e ()1 o
()1 ()1 ()1

LEFT SBIFT REGISTER:

reseln----
din ~din dout
dout
clk

....1
O .... N e
()1 ()1 ()1 ()1

Timing Diagram example:

clk

:n
1
1

X -~-~, .~-~-
, ~:
:r-t_J......---- . . . . --
: 1 ~~--~-~--

_.. _.. .r:-:i ;~

----..---n :~ L-+J:1
1

1:
1 '---...,...--...- :
1

1
6
1 1 1 1 1 1 :
1
 ºº
- - - - r - - - -1- - - - ,- - - -T - - - - r - - - -i- - - - -,- - - - T - - - - r - - - -r - - - ,- - - - 'T - - - - r - - - -r
Q 0000: 0000: 0000: 1000 :0100 : 0010: 1001: 0100: 1010: 1101: 1110: 0111, 0011: 0001:
----r--------,----T----r----1-----,----T----r----r---,----,----r----r

7
PARALLEL ACCESS SHIFT REGISTER
• This is a shift register in which we can write data on the flip flops in parallel. s_l = o -+ shifting operation, s_l = 1 -+ parallel
load. The figure shows a 4-bit parallel access right shift register.
Q3 Q2 Ql QO

D Q D Q D Q D Q

clk

o 1

din D3 s 1 D2 Dl DO

s l
din
1 1

D '. 0000: X.._ ~_10_1_: :>GE<.. . !.-~--1'._10_-0~_~:-----

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

----r---,----r---,----r---,----T----.----1----r---,----r---,----T----,----1----r----
Q 0000:000011000:1100:0110:0011:1001:1101:1110:0111:1011:1100:0110; 0011:1100:1110:0111: 0011
----r---,----r---~----r---~----T----~---~----r---~----r---~----r--------~----r---·
' 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

ADDING AN ENABLE INPUT TO FUP FLOPS

• In many instances, it is very useful to have a signal that controls whether the flip flop works. The following circuit represents
a D flip flop with synchronous enable. When E = 'O', the flip flop does not work, i.e., the flip flop keeps its value. When E =
'1', the flip flop works, i.e., Q=D on the rising edge.
• We can thus create n-bit registers and n-bit shift registers with enable. Here, all the flip flops share the same enable input.

clk 1
1

resetill
D D Q
Q
D
clk----+>
'---=--' E
resetn----~
Q

REGISTER: RIGHT SHIFT REGISTER: LEFT SHIFT REGISTER:

resctn ------. resetn-----. resetn -----.

n-+--1 D n din~ din dout-+ dout din dout

D Q Q
E~E E
E

clk----<'
.... N M 1
O - N e
e:1 e:1 e:1 o ()1 ()1 ()1 ()1
()1 ()1 ()1 ()1

8
Parallel access shift register with enable
• All the flip flops share the same enable input.
Q3 02 Ql QO

D Q D Q D Q Q

o l

din 03 s 1 02 Dl DO

clk fLfLfLfL
E

5 l
din

o 0000 :1101: 1100:

----r----r---,----·----r----r---,----~---- r----r---~- ---~----r-- --r---~---- ,----T----

1 1 ' t ' 1 1 1 1 1 1 1 1 1

Q 0000:0000:1000:1100:0110:1011:1101:1101:0110:1101:0110:
----~--------~--------------1----~----·----~----~---~---1-1·0-0:-0-1-1~0:-0-0-1-1~: ---1~0-01-:-1-1~0-0-:0-1-1·0-:0-0-1-1
• • • • • • • • • ' • • • • • 1 •

ADDING A SYNCHRONOUS CLEARINPUT TO FLIP FLOPS

• In many instances, it is very useful to have a signal that can clear the value of the flip flap but only on the rising (or falling
edges): synchronous clear (sclr). Typically, ali synchronous signals are validated by enable. Far example, far a D flip flap,
the table show how the output state Q changes (on the rising edge):

E sclr o Q Q
o X
1 o Q <-D o
E
1 1 Q <-o

resctn

• We can thus create n-bit registers and n-blt shift registers with enable and sclr. Here, all the flip flops share the same enable
and sclr inputs.
REGISTER: RIGHT SHIFT REGISTER: LEFT SHIFT REGISTER:
reseln----.. reseln ------. reseln -----.

o--n-1--1 D Q n Q din-din dout- dout din-din dout dout

E-E E-E
E----t

sclr----t sclr- sclr sclr- sclr

clk clk
clk----o._ _,

~ N M
1 1 1
e e e e e1
()1 ()1 ()1 ()1 ()1

9
SVNCHRONOUS COUNTERS
• Counters are useful for: counting the number of occurrences of a certain event, generate time intervals for task control,
track elapsed time between two events, etc. Counters are made of flip flops and combinatoria! logic. Common design
strategies indude using the Finite State Machines (FSM) method or a synchronous accumulator.
• Synchronous counters change their output on the clock edge (rising or falling). Each flip flop shares the same clock input
signal. If the initial count is zero, each flip flop shares the resetn input signa l.

COUNTER CLASSIFICATION:
a) Binary counter: An n - bit counter counts from O to 2n - l. The figure depicts a 2-bit counter.

Qo clk
1
1
resetn_j_J
1
1 1 1 1 t 1 1
J L J i L---~----L 1 J _
1 1 1 1 1 1 1 1

Q 00:
---y.--0-0-~:. --0-1,--:. -1-0r--:. -1,-1--:.-r-0-0-~:.--0-1-r-:. -1-0- :. 11

b) Modulus count:er: A counter modulo - N counts from O to N-1. Special case: BCD (or decade) counter: Counts from O
to 9.
resetn
clk
1

resetn_LJ
'

Clk
----~' ---A----~---~----~---~-
Q 0000:
' ---¿----~---A----~---~----~----
0000: 0001: 0010: 0011: 0100: 0101: 0110:0111: 1000: 1001: 0000: 0001
'
BCD counter ----L! ---~-! ---L-! --~--! --L---! ~----! L----! '----!~----! L---~-! ---L-!--- !

e) Up/down count:er: Counts both up and down, under command of a control

input. d) Parallel load count:er: The count can be given an arbitrary value.
e) Counter with enable: If enable = O, the count stops. If enable = 1, the counter counts. This is usually done by
connecting the enable inputs of the flip flops to a single enable.
f) Ring count:er: Also called one-hot counter (only one bit is 1 ata time). It can be constructed using a shift register. The
output of the last stage is fed back to the input to the first stage, which creates a ring-like structure. The asynchronous
signa! startn sets the initial count to 100 ... 000 (first bit set to 1). Example (4-bits): 1000, 0100, 0010, 0001, 1000, ...
The figure below depicts an n - bit ring counter.

g) Johnson counter: Also called twisted ring counter. It can be constructed using a shift register, where the Q output of
the last flip flop is fed back to the first stage. The result is a counter where only a single bit has a different value for two
consecutive counts. Ali the flip flops share the asynchronous signal 'resetn', which sets the initial count to 000 ... 000.
Example (4 bits): 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000, ... The figure below depicts
an n - bit Johnson counter.

10
COUNTER DESIGN USING AN ACCUMULATOR:
• The figure shows a counter moclulo-200 that uses a register, and adder, a comparator, and logic gates.
• Q: count. z: output signa! asserted only when the maximum count (199) is reached.

n = ílog2 2001 =8

E
11000111
sclr 8

sclr: synchronousdear 8 1-----.i 199?

lfE=sc!F1,thenQ=O Q A~--.--~
A=B
z

RANDOM ACCESS MEMORY EMULATOR

• The following sequential circuit represents a memory with 8 addresses, where each address holds a 4-bit data. The memory
positions are implemented by 4-bit registers. The reset and dock signals are shared by all the registers. Data is written or
read onto/from one of the registers (selected by the signa! address).

• Writing onto memory (wr .ra = 1): The 4-bit input data (D_in) is written into one of the 8 registers. The addre.ss signa!
select:s which register is to be written. Here, the 7-segment display must show O. For example: if address = "101", then D_in
is written into register 5.

• Reading from memory (wr_rd = O): The MUX output appears on the 7-segment display (hexadecimal value). The
address signa! select:s the register from which data is read.
For example: If address = "010", then data in register 2 must appear on the 7-segment display. If data in register 2 is '1010',
then the symbol 'A' appears on the 7-segment display.
resetn ----------------------------------------------------------
wr_rd

o Q

1 Q
clock ~·'

2 Q

address _3 M 3 Q
Decoder Decoder:
4

HEX to 7
segments
4 Q
wr rd -~.i E

7
5 Q

6 Q

D 7 Q

11
 LINEAR FEEDBACK SHIFT REGISTERS (LFSRs)
• LFSRs have a simple and fairly regular structure. Typical components: D-type flip flops, and logic gates.
• Advantages: very little hardware and high speed operation.
• Inputs to flip flops are linear functions of the previous state.
• Despite the simple appearance, LFSRs are based on rather complex mathematical theory and have interestlng
applications
in the area of digital system testing, cryptography, and fault-tolerant computing.
• Typical applications: Error correction/detection, pseudo random number generators, fast counters.
• A generic 4-bit LFSR is depicted below:

ºº

▪ Este código de detección de errores se usa en comunicaciones digitales (por ejemplo:

Ethernet, CAN) y dispositivos de almacenamiento (por ejemplo: RAM).

LINEAR FUNCTION

APPUCATION: CYCUC REDUNDANCYCHECK (CRC)

• This error-detection code is used in digital communications (e.g.: Ethernet, CAN), and storage devices (e.g.: RAMs).

Communicationsystem
• k-bit message: M = mk-imk-2 ... m¡mo.
• CRC code: R = Tn-1Tn-2 T1To.
• Stream sent: mk-imk-z m1m0rn_1rn-z ... r1r0
,
m'2
m'1
n, m'o
. ,
Transmitted bits
- CRC
R 1 - CRC ----+ err or
- Generator
-
Checker
R'

• Associated polynomials:
./ M(x) = mk_1xk-l + mk_2xk-2 + ... + m1x1 + m0x0• Order: k - 1
./ R(x) = Tn-1Xn-t + Tn-2x"-2 + ... + r1x1 + roxº. Order: n - 1
• The CRC code is calrulated as a remainder: R(x) = remainder c·:7;;>)
• G(x) = BnX" + Bn-ix"-1 + ··· + g1x1 + g0x0• This is the generating polynomial of order n. G = BnBn-1 ... g1g0
• Here, when dealing with polynomial operations, we use modulo-2 polynomial arithmetic (Galois field of two elements: GF(2)).
The coefficients of the polynomials can only be O or l. The multiplication operation can be implemented as a simple ANO
gate, and the addition (or subtraction) operation can be implemented by a XOR gate: a± b = a€Db,a e {0,1} .
./ Example: x" + x" = x" - x" = O.

• CRCgenerator: It computes R(x). Its input is x"M(x) = mk-im1<_2 ... m1m000 ... O.

• 12CRC code might be corrupted by the channel: M'(x) and R'(x) .

CRCchecker: On the receiver side, both the message and
e·:~~~x))
./ So, we must check if remainder = R'(x). If so, we say that the system passed the CRC check .
./ Note that this implies: x"M'(x) = Q'(x)G(x) + R'(x)-+ x"M'(x) - R'(x) = x"M'(x) + R'(x) = Q'(x)G(x). In modulo-2
arithmetic, R'(x) = -R'(x). It follows that x"M'(x) + R'(x) should be divisible by G(x) .
./ The CRC checker tests if remainder (x"M'(x)+R'(x))
C(x)
=O. If the remainder is zero, we say that it passed the CRC check. It
is still possible for R'(x) and M'(x) to make the remalnder equal to zero but this is far less likely .
=
./ The input to the CRC checker is x"M'(x) + R'(x) m'k-1m'k-2 ... m'0r'n-1r'n-2 ... r'0.

13
• Example: CRC-4 (n = 4): M = 11100110, G = 11001
M(x) = x7 + x6 + x5 + x2 + x
= =
x" + xl + y xH + xio + x9 + x6 + xs
_. xnM(x)
G(x)=
x4(x1 + x6 + xs + xz + x)
x4 + x3 + 1
x11 + x10 + x9 + x6 + xs x11+x1º+x1 ¡ ¡
R(x)= x2 +x x9 + x1 + x6 + x5
x9 + x8 + x5
CRC drcuit x8 + x1 + x6
• The following LFSR implements 4-bit CRC. Components: flip flops, ANO, XOR gates. x8 + x1 + x4
• Note that 94 = 1 is not used. This is because it is common in CRC to have Bn = 1.
This is already considered in the design of the circuit. x6 +x4
• Example with M = 11100110, G = 11001: x6 + xs + x2
./ When integrated into the CRC generator, the input is given by:
+ x4 + xz
xnM(x) =
111001100000. The output result is R = 0110.
./ When integrated into the CRC checker, the input is given by:
xs
x5 + X4 +X

xnM'(x) + R'(x) =
111001100110. The result of the circuit is remainder =
0000, indicating a valid transmission.
x2 +x

clk
'
resetn_J
E j_J~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1 '--~~---'
1

X
1 1 1 1

----r----r----r----r----r----r----r----,----,----,
1 1 1 1 1 1
---,----,----,----,----,----,
R 0000: 0000: 0001:0011:0111: 1110: 0101:1011:1110: 0101: 1010: 1101 :0011 ,0110 0110 0110:
- - - - r - - - - r - - - - r - - - - r - - - -r - - - -r - - - -¡- - - - -,- - - - -,- - - - -.- - - - 1- - - - ,- - - - ,- - - - , - - - - , - - - - i
1 1 • 1 1 1 1 1 1 1 1 1 1 1 • 1

clk
1

resetn_J
E j_J~~~~~~~~~~~~~~~~~:I
1 ~~~~~

X
1 1 • 1 1 1 1 1 '
1 1 1 1 1 1 1 1 1 1
--- - r---- r- --- r- ---r----r- -- -,-- --.-- -- -,- -- --,-- -- .... - -- --.-- --,-- --,----,-- -------,
R 0000: 0000: 0001:0011:0111: 1110: 0101:1011:1110: 0101: 1010: 1100:0000 0000 00001 0000:
----r----r----r----r----r----r----r----,----,----~----,----,----,----,----,----,
1 1 • 1 • • 1 1 1 1 t 1 t

• Applications: The drcuit above can be implemented for any number of bits n. For
example: CRC-32 (Ethernet), CRC-15 (CAN), and CRC-1 (trivial even parity generator X
with G(x) = x + 1).
• This is a serial implementation, i.e., each bit is fed to the circuit at a time. E-+-----1
Other clk -+-----...-
implementation process sorne bits in parallel (for CRC-1, the parity generator in Notes
- Unit 1 processes ali the bits at once).
• The de.sign of the generating polynomial G(x) is outside the scope of this dass .
• These circuits are better implemented in hardware for high speed and low resource
utilization.

14
FINITE STA TE MACHThTES:

• 5equential circuit:s are also called Rnite State Machines (FSMs), because the functional behavior of these circuit:s can be
represented using a finite number of states (flip flop outputs).
• The signa! resetn sets the flip flops to an initial state.
• Classification:
- Moore machine: Outputs depend solely on the current state of the flip flops.
- Mealy machine: Outputs depend on the current state of the flip flops as well as on the input to the circuit.
Onlyfor MealyMachine

.._
,

Inp uts Flip n, Q(states) ~ Combinatoria! Out

.._ puts
.._ Combinatoria! .._

, ,
Circuit
r
Flops Circuit

~ ~ t>
u

clock
resetn

• Any general sequential circuit can be represented by the figure above (Finite State Machine model).
• A sequential circuit with certain behavior and/or specification can be formally designed using the Finite 5tate Machine
method: drawing a 5tate Diagram and coming up the Excitation Table.
• Designing sequential circuits using Finite 5tate Machines is a powerful method in Digital Logic Design.

Example: 2-bit gray-code counter with enable and 'z' output: 00, 01, 11, 10, 00, ... The output 'r is 1 when the present
count is '10'. The count is the same as the states encoded in binary.
• Rrst step: Draw the 5tate Diagram and 5tate Table. If we were to implement the state machine in VHDL, this is the only
step we need.
E/z
E PRESENT NEXT NEXT
STATE STATE COUNT z
o Sl Sl 00 o
o S2 S2 01 o
0/0 o S3 S3 11 o
o S4 S4 10 1
1 Sl S2 01 o
1 S2 S3 11 o
1 S3 S4 10 o
1 S4 Sl 00 1
• Second step: State Assignment. We assign unique flip flop states to our state labels (51, 52, 53, 54). Notice that this is
arbitrary. However, we can save resources if we assign each state to the count that we desire. Then, the output 'count' is
just the flip flops' outputs.

../ 51: Q = 00
../ 52: Q = 01
../ 53: Q = 11
../ 54: Q = 10

15
• Third step: Exdtation table. Here, we replacethe state labels by the flip flop states:
PRESENTSTATE NEXTSTATE

E 01 (t) Oo (t) Qi(t+l) Oo(t+l) z

o o o o o o
o o 1 o 1 o
o 1 1 1 1 o
o 1 o 1 o 1
1 o o o 1 o
1 o 1 1 1 o
1 1 1 1 o o
1 1 o o o 1
• Fourth step: Exdtation equations and minimization. Q1 (t + 1) and Q0(t + 1) are the next state of the flip flops, i.e. these
signals are to be connected to the inputs of the flip flops.
Q¡ (t+l) EQ1 Qo (t+l) EQ1 z EQ
ºº 00 01 11 10 ~ 00 01 11 10 Q
1
00 01 11 10

o
o o o o o o o o r 1 1 o
1 o 1 1 o o o o
Q1(t + 1) = EQ1 + EQo
Q0(t + 1) = EQ1 + EQ0
z = Q1Qo
Output z only depends on the present state. Outputs Q1, Q0 are the states and they only depend
(in termsof the combinational output circuit) on the present state. Thus, this is a Moore F5M.

• Rtth step: Circuit implementation.

reseLn~----------~~
clk~---;::::::::¡:::============:::::iH---l-----. clock
''
resetn_JJ:
ºº
E
-- -¡- - - -1- - - -r'-- --,---- ,-- - -,-- --r- - - -,--- --,-- --
state 51 : 51 : 52 : 53 : 53 : 54 : 54 : 51 : 52 : 52
01 ---~----~----~----~---~----~----~----~---~-----
---,----T----r----r---,----,----r----r---,----
! 1 j 1 1 ' • 1 1

Q 00 : 00 : 01 : 11 : 11 : 10 : 10 : 00 : 01 : 01
---~----·----~----~---~----~----~----~---~-----
i---------+-z
z
'

.
1

.
1

'
1

.
1

!I
1

. !1
1

.
1 1

Example: 2-bit counter with enable and 'Z: output. The output 'z' is 1 when the present count is '11'. The count is the same as
the states encoded in binary.
• Rrst step: Draw the State Diagram and 5tate Table. If we were to implement the state machine in VHDL, this is the only
step we need.
E/z E PRESENT NEXT NEXT
STATE STATE COUNT z
o Sl Sl 00 o
o S2 S2 01 o
0/0
o S3 S3 10 o
o S4 S4 11 1
1 Sl S2 01 o
1 S2 S3 10 o
1 S3 S4 11 o
16 1 S4 Sl 00 1
• Second step: 5tate Assignment. We assign unique flip flop states to our state labels (51, 52, 53, 54). Notice that this is
arbitrary. However, we can save resources if we assign each state to the count that we desire. Then, the output 'count' is
just the flip flops' outputs.

,/ 51: Q = 00
,/ 52: Q = 01
,/ 53: Q = 10
,/ 54: Q = 11

• Thírd step: Excitation table. Here, we replacethe state labels by the flip flop states:
PRESENT STATE NEXTSTATE

E 01 (t)
ºº (t)
Q1(t+l) ºº (t+l) z
o o o o o o
o o 1 o 1 o
o 1 o 1 o o
o 1 1 1 1 1
1 o o o 1 o
1 o 1 1 o o
1 1 o 1 1 o
1 1 1 o o 1

• Fourth step: Exdtation equations and minimization. Q1 (t + 1) and Q0(t + 1) are the next state of the flip flops, i.e. these
signals are to be connected to the inputs of the flip flops.
Ql (t+l) EQ Qo (t+l) EQ1 EQl
l

Q 00 01 11 10 ~ 00 01 11 10 z 00 01 11 10
o Qo

o o 0. r
1 o o o o l1 1 o o o o o
1 o 1 1

Q1(t + 1) = Q1Qo + EQ1 + EQ1Qo

o ~
1
~ ~
o o 1 o 1
-- 1 o

Q0(t + 1) = EQ0 + EQ0

z = Q1Qo

Output z only depends on the present state. Outputs Q1, Q0 are the states and they only depend
(in termsof the combinational output circuit) on the present state. Thus, this is a Moore F5M.

• Rfth step: Circuit implementation.

clock
1
1

resetn _LJ
E '~-i--
---,----y----r----r---,----,----r----r---,----
1 1 ' 1
z 1 1 1 • 1

state 51 : 51 : 52 : 53 : 53 : 54 : 54 : 51 : 52 : 52
---~----?----~----~---~----~----~----~---~-----
' 1 1 1 1 1 1 1 1

>----Oc ---,----T----r----r---,-- --T----r----r---,----

t 1 1 1 1 1 1 ' 1

Q
-0--0~-: -0--0+-:--0-1~--: --1~0--: -~1-0--: -~1-1--:-~1-1--:-~0-0--~:--0-1--: 01
' 1 1 1 1 1 1 1 1
1 1 1 1 ¡1 1 ¡1 1 1

Note: In these 2-bit counters, the states are represented by the outputs of the flip flops: Q11 Q0• They also happen to be
the outputs of the FSM. This is common in counters, as the count is usually the same as the flip flop outputs.

17
Example: BCD counter. Output:s: Q(3 .. O), z. When the count reaches 1001, z becomes l. Moore FSM

Example: FSM. Input: w. Output: z. This is a Moore FSM as z only depends on the present state.
resetn =O

clk
1

rstn_j_J
1
w 1 ' 1 1 1
•
1
1
L 1
1
'
J 11 L
1 1
1
1
J 11 L
1 1
L J1 J1 L1 L J1 _

1 1 1 1 1 1 1 ' 1 f 1 1 1 1 1
state Sl : Sl : S2 : S9 : SS : S9 : Sl : S2 : S3 : S2 : S3 : S4 : SS : S4 : S3 : S4
----r---,----,----T----r----,----,----T----r----r---,----,----r----r---,------·
1 1 1 1 1 1 1 1 1 1 1

18
ALGORITHMIC STATEMACHINE (ASM) CHARTS:
Sequence Detector (with overlap)
Gray counter, z=l when Q=lO 010011

E/z

1/0

0/0

51 51

52 52

53 53

54 54

$5

56

o
z +- 1

19
ExAMPLE: ARBITER 0RCUIT

• Three devices can request access to a certain resource at any time (example: access to a bus made of tri·state buffers, only
one tri·state buffer can be enabled at a time). The FSM can only grant access to one device at a time.There should be a
priority level among devices.
• If the FSM grants access to one device, one must wait until the request signal to that device is deasserted (i.e. set to zero)
before granting access to a different device.

DEVICE 1 j-:eql priority

t
grantl
resetn
DEVICE 2 j-:eq2 A
rl~ gl
g2
t
grant2 clock
r2------+
r3~
>
FINITESTATE
MACHINE ~ g3

CONTROL CIRCUT

DEVICE 3 j-:eq3

i
grant3

• Algorithmic State Machine (ASM) chart:

51

20
Redudng rate of change of a synchronous circuit:

• Here, we use FSM asan example of a synchronous circuit. But we can apply this technique to any synchronous circuit.

• We usually would like to reduce the rate at which FSM transitions occur. A straightforward optíon is to reduce the frequency
of the input dock. But this is a very complicated problem when a high precision clock is required.

• Alternatively, we can reduce the rate at which FSM transitions occur by including an enable signal in our FSM: this means
including an enable to every flip flop in the FSM. For any FSM transition to occur, the enable signal has to be 'l'. Then we
assert the enable signal only when we need it. The effect is the same as reducing the frequency of the input clock .

./ The figure below depict:s a counter modulo-N (from O to N-1) connected to a comparator that generates a pulse (output
signal 'z') of one dock period every time we hit the count 'N-1'. The number of bits the counter is given by n = flog2 N].
The effect is the same as reducing the frequency of the FSM to f /N, where f is the frequency of the clock .

./ A modulo-N counter is better designed using VHDL behavioral description, where the count is increased by 1 every clock
cycle and 'z' is generated by comparing the count to 'N-1'. A modulo-N counter could be designed by the State Machine
method, but this can be very cumbersome if N is a large number. For example, if N = 1000, we need 1000 states.

E
Outputs
Inputs FSM
E----tE Q 1--"n"+--...-+

comparator z

Q=N-17
counter
0 toN-1
clock-_... ,

./ Asan example, we provide the timing diagram of the counter from O to N-1, when N= 10. Notice that 'r is only activated
when the count reaches "1001". This 'z' signal controls the enable of a state machine, so that the FSM transitions only
occur every 10 dock cycles, thereby having the same effect as reducing the frequency by 10.

----~---~----~---~----~---~----+--- ~---~----~---~----~----
o 0000:0000:0001:0010:0011!0100:0101: 0110 0111: 1000: 1001: 0000: 0001
----~---~----~---~----~---~----~----~---~----~---~----~----
• 1 1 1 1 1 1 1 1 1 1 1

• We can apply the same technique not only to FSMs, but also to any sequential circuit. This way, we can reduce the rate of
any sequential drcuit (e.g. another counter) by including an enable signal of every flip flop in the drcuit.

Flip flop timing parameters:

• Propagation Delay.
• Setup Time: Interval of time befo re the
clock edge where the data must be

held stable.
resetnu clk
tsETUP

--~,~.
1
"' """'
1

t ~~
. ......._~
t
L
• Hold Time: Interval of time after the
dock where the data must be held
D -o Q Q
D JM/i; ' 1
stable. clk- 1
1

• If setup time or hold time are violated, Q

1

the output may become unpredictable,

or even worse it might enter into
metastability.
--
1
1
1
1

restricted
region

21