数字集成电路原理

Sequential Logic Circuits

刘佳欣
liujiaxin@uestc.edu.cn
Outline
pIntroduction
pStatic Latches and Registers
pBistability Principle
pMultiplexer-Based Latches
pMaster-Slave Edge-Triggered Registers
pDynamic Latches and Registers
pDynamic Transmission-gate Edge Triggered Registers
pC2MOS Registers
pTrue Single-Phase Clocked Registers
pPipelining

2
Logic Circuits
p Combinational logic p Sequential logic
p Output depends on current p Output depends on current
inputs and previous inputs

3
Sequential Logic

I n p u O u t
C O M B
L O G I

C u r r tSt
ae
N e x
R e g i
Q D

C L K

p 2 types of storage mechanisms

• positive feedback: static
• charge-based: dynamic

4
Sequential Logic
q Latch and register are two types of typical sequential
logic, both in static and dynamic

q Name conventions
§ In our text:
– a latch is level sensitive
– a register is edge-triggered

§ There are many different naming conventions

– For instance, many books call edge-triggered elements
flip-flops
– This leads to confusion however

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Latch versus Register
q Latch q Register
level sensitive edge triggered

D Q D Q

Clk Clk

Clk Clk

D D

Q Q

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Latches

P o s i veLatc h N e g

I n D Q O u t I n D Q O u
G G

C L K C L K

c l k c l k

I n I n

O u t O u t

O u Ot u t O u Ot u t
s t f a o l b l s tsIn f a o l

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Latch versus Register: Timing

tD 2 Q

D Q D Q

C l k C l k

tC 2 Q tC 2 Q

Register Latch

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Outline
pIntroduction
pStatic Latches and Registers
pBistability Principle
pMultiplexer-Based Latches
pMaster-Slave Edge-Triggered Registers
pDynamic Latches and Registers
pDynamic Transmission-gate Edge Triggered Registers
pC2MOS Registers
pTrue Single-Phase Clocked Registers
pPipelining

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Static Latch

V i1 V o1 V i2 = V o2

V o2 V i1 =
Cross-coupled inverter pair

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Static Latch
V o1 Vi2

V i1 V o1 V i2 = V o2
V i1 V o2

A
V i 2 = V o1
V o2 V i1 =
C

Cross-coupled inverter pair B

Ø Positive feedback V i 1 = V o2

Ø 3 possile operation points

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Bi-Stability & Meta-Stability

p A and B are stable states

Ø Gain at A/B is <<1

p C is meta-stable state
Ø Gain at C >>1
Ø A small disturbance at C will move the latch to A/B

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Changing the State for a Flip Flop
p Flip Flop: Another name for bistable circuits

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Outline
pIntroduction
pStatic Latches and Registers
pBistability Principle
pMultiplexer-Based Latches
pMaster-Slave Edge-Triggered Registers
pDynamic Latches and Registers
pDynamic Transmission-gate Edge Triggered Registers
pC2MOS Registers
pTrue Single-Phase Clocked Registers
pPipelining

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Mux-Based Latches

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Mux-Based Latches

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Outline
pIntroduction
pStatic Latches and Registers
pBistability Principle
pMultiplexer-Based Latches
pMaster-Slave Edge-Triggered Registers
pDynamic Latches and Registers
pDynamic Transmission-gate Edge Triggered Registers
pC2MOS Registers
pTrue Single-Phase Clocked Registers
pPipelining

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Master-Slave Register

p Two opposite latches make a register

p Also called master-slave latch pair

p How to make a negtive edge-triggered register?

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Master-Slave Register

p CLK=0, T1 is on, T2 is off, input D is sampled on QM

p T3 is off, T4 is on, slave latch holds the last state
p CLK=1, T1 is off, T2 is on, master latch holds the state QM
p T3 is on, T4 is off, QM is copied to Q
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Register: Timing Definitions
CLK
Register t
D Q tsetup thold

D DATA
CLK STABLE t
tcq

Q DATA
STABLE t

p Setup time (Tsetup)

Ø the time before the rising edge of the clock that the input data D
must become valid.
p Hold time (Thold)
Ø the time that the input must be held stable after the rising edge of
the clock.
p Propagation delay (tcq)
Ø the time for the value of QM to propagate to the output Q.
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Register: Timing Definitions

pSetup time (Tsetup)

Ø the 2*tpd_inv + tpd_tx
pHold time (Thold)
Ø0
pPropagation delay (tcq)
Ø tpd_tx + tpd_inv
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Simulation of Propagation Delay

160ps
180ps

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Timing Constraints

Tc > tpcq + tpd + tsetup

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Reduced Clock Load Master-Slave Register

CLK CLK

D T1 I1 T2 I3 Q

I2 I4
CLK CLK

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Reduced Clock Load Master-Slave Register

CLK CLK

D T1 I1 T2 I3 Q

I2 I4
CLK CLK

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Outline
pIntroduction
pStatic Latches and Registers
pBistability Principle
pMultiplexer-Based Latches
pMaster-Slave Edge-Triggered Registers
pDynamic Latches and Registers
pDynamic Transmission-gate Edge Triggered Registers
pC2MOS Registers
pTrue Single-Phase Clocked Registers
pPipelining

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Static VS. Dynamic: Storage Mechanisms

Static Latch Dynamic Latch

C L K CLK

Q D Q

C L K

D CLK

C L K

• positive feedback • charge-based

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Dynamic Edge-Triggered Register

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Dynamic Edge-Triggered Register

• Timing constraint:
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Making a Dynamic Latch Pseudo-Static
CLK Easily disturbed node

D Q

CLK

C L K

D D

Keeper
C L K
Robustness can be improved significantly !

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Pseudo-Static Register

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Outline
pIntroduction
pStatic Latches and Registers
pBistability Principle
pMultiplexer-Based Latches
pMaster-Slave Edge-Triggered Registers
pDynamic Latches and Registers
pDynamic Transmission-gate Edge Triggered Registers
pC2MOS Registers
pTrue Single-Phase Clocked Registers
pPipelining

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Other Latches/Registers: C2MOS
p C2MOS: clock controlled MOS logic

“Keepers” can be added to make circuit pseudo-static

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Insensitive to Clock-Overlap
p Block the direct connection from D to Q

0 0 1 1

0 0 1 1

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Outline
pIntroduction
pStatic Latches and Registers
pBistability Principle
pMultiplexer-Based Latches
pMaster-Slave Edge-Triggered Registers
pDynamic Latches and Registers
pDynamic Transmission-gate Edge Triggered Registers
pC2MOS Registers
pTrue Single-Phase Clocked Registers
pPipelining

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True Single-Phase Clocked Latches
p True Single-Phase Clocked (TSPC)

VD D VD D VD D VD D

O u t

I nC L K C L K I nC L K C L K

O u t

Positive latch Negative latch

(transparent when CLK= 1) (transparent when CLK= 0)

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True Single-Phase Clocked Register
p Build register using two opposite latches

VD D VD D VD D VD D

O u t

I nC L K C L K I nC L K C L K

O u t

Positive latch Negative latch

(transparent when CLK= 1) (transparent when CLK= 0)

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Outline
pIntroduction
pStatic Latches and Registers
pBistability Principle
pMultiplexer-Based Latches
pMaster-Slave Edge-Triggered Registers
pDynamic Latches and Registers
pDynamic Transmission-gate Edge Triggered Registers
pC2MOS Registers
pTrue Single-Phase Clocked Registers
pPipelining

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Pipelining

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Pipelined Computations

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Thank you!