Reliability in Multilayer Ceramic Capacitors
journal
Fractography of Thermal-Shock-Cracked
Multilayer Capacitors
KEMET Electronics Corporation, Greenville, South Carolina 29606
Cracking of multilayer ceramic chips due to mechanical and
thermal stresses during surface mounting is a major problem.
Two types of tests were performed to study the susceptibility
of chips for thermal shock cracking. In one test, chips were
immersed in molten solder at different temperatures and,
after cooling, chips were examined for visible cracks. In
another test, chips were mounted on a printed circuit board
and, then, wave soldered to simulate the actual usage condi-
tions. After the soldering process, chips were exposed to load
humidity conditions and, then, tested for insulation resist-
ance. Cracked chips from both tests were analyzed by fracto-
graphic methods to determine the source of failure. Causes of
the defects leading to fracture and their relationship to the
processing of multilayer capacitors are discussed. The rela-
tive advantages and disadvantages of the two thermal shock
test methods in evaluating the integrity of the chips are pre-
sented. [Key words: capacitors, multilayer, thermal shock,
cracks, fractography.]
I. Introduction
C RACKING of multilayer ceramic (MLC) chip capacitors dur-
ing soldering is a major problem for surface mount applica-
tions. Understanding the thermal shock behavior and the knowledge
of the flaw population is important in improving the reliability of
the ceramic capacitors. Mechanical behavior studies of dielectric
ceramics' and finite-element analysis of stresses in the capacitor
during provide useful information in predicting the
thermal shock behavior. Thermal shock testing on actual devices
is also preferred to characterize the thermal shock resistance of a
particular batch of capacitors. Johnson-Walls and co-workers4
described a thermal stress method for evaluating surface flaw
population in ceramic capacitors. They identified corner flaws on
MLC capacitors as the primary source of failure during thermal
cycling. Van Den Avyle and Mecholsky' studied the thermal
shock behavior of two different batches of capacitors. Using fracto-
graphic analysis, they identified the fracture initiation sites on the
outer surfaces at the ceramiciend terminations interface. From the
fracture toughness measurements, they concluded that the differ-
ence in the thermal shock behavior of the two batches is not due
to the material differences, but due to differences in the stresses
acting on the parts. In an earlier paper,6 we showed the effect of
internal flaws in controlling the thermal shock resistance of dif-
ferent batches of capacitors.
In this work, two types of thermal shock testing were per-
formed on MLC chip capacitors to evaluate their susceptibility to
cracking. Cracked capacitors from these tests were analyzed by
fractography methods to determine the sources of failure. The
tests reported here were performed on one type of capacitor from
different lots manufactured over a period of time. Through an
iterative process of thermal shock testing and failure analysis,
flaws responsible for the cracking were identified and process
improvements were suggested to eliminate them.
Manuscript No. 198494. Received April 6, 1989; approved August 15, 1989.
Presented at the Symposium for the Improvement of Multilayer Capacitor Reli-
ability, The Pennsylvania State University, University Park, PA, May 11, 1989
(Paper No. 7).
*Member, American Ceramic Society.
224 1
J. Am. Ceram. SOC., 12 [I21 2241-46 (1989)
Chowdary R. Koripella* and Henry V, DeMatos
11. Experimental Procedure
Thermal shock experiments were performed on 1206 size X7R
capacitors rated at 0.1 pF. Dielectric material is modified barium
titanate, liquid-phase sintered at I IOO'C. Internal electrodes are
made of a silveripalladium alloy.
Two types of thermal shock experiments were performed. In
one, the capacitors were held by small metal clips in a fixture and
were dipped into a liquid RMA flux before being immersed
suddenly into molten solder at different temperatures. In this
arrangement, the capacitor is free to expand in all directions at
both ends, but is restrained in the middle. Fifty capacitors were
tested at each of the following temperatures: 260°, 290°, 320",
350", and 400°C. After the capacitors were allowed to cool to
room temperature, they were cleaned with a solvent to remove
the flux. The samples were then inspected microscopically for
visible cracks.
In the second test method, the capacitors were exposed to ther-
mal shock while mounted on an FR-4 grade printed circuit board,
by passing them through a solder wave at 260°C. The capacitors
were then subjected to a 24-h load humidity test at 85°C and 85%
relative humidity with an applied voltage of 50 V. Insulation re-
sistance (IR) at rated voltage was used to determine failure.
Capacitors that failed the IR test were inspected visually for cracks.
Cracked capacitors were carefully removed from the board for
failure analysis by fractographic techniques. Samples were pre-
pared by removing the end terminations by grinding or by dis-
solving in dilute nitric acid. Aftcr the samples were cleaned,
cracks were opened gently with a sharp blade to expose the frac-
ture surfaces. Fracture surfaces were then examined using a
stereomicroscope and scanning electron microscopy (SEM).
111. Results and Discussion
(1) Solder Immersion Thermal Shock Test
Thermal shock performance data for different batches of MLC
capacitors manufactured ovcr a period of time are given in
Tables I and 11. Table I presents the thermal shock test results on
batches 1 to 4, which represent the earlier batches of capacitors,
and Table I1 shows the thermal shock results on batches 5 to 8,
which had process improvements. On batches 1 to 4, testing was
done at 260°, 290", 320", and 350°C. Table I gives the number of
capacitors cracked out of the SO capacitors tested at each tem-
perature. Figure 1 shows the cumulative failure rate distribution
over the test temperature range. As seen from these results, some
batches which are highly resistant did not exhibit any cracking
until exposure to high temperatures, while others show cracking
at normal use temperatures and experience high failure rates at
all temperatures.
Figure 2 depicts the typical crack shapes found during visual
examination of the failures. These cracks are classified as moon
cracks, corner cracks, and side cracks, based on their shape and
site of failure. Samples of the failed capacitors were mounted and
cross-sectioned for internal examination. Cracks were seen to
propagate through several dielectric and electrode layers, but the
analysis by cross-sectioning failed to positively identify failure
sites and provided very little information. Fractography methods
were used to analyze the failed samples in greater detail to deter-
mine the source of failure and to study the crack propagation.
2242 Journal of the American Ceramic Society-Koripella and DeMatos Vol. 72, No. 12

Table I. Solder Immersion Thermal Shock Test Results for Table 11. Solder Immersion Thermal Shock Test Results for
Capacitors from Batches 1 to 4 Capacitors from Batches 5 to 8
Number of chios cracked at each test temuerature Number of chips cracked at each test temperature
Batch No 260 290 320 350 Total Batch No. 260 290 320 350 400 Total
1 0150 0150 0/50 5/50 51200 5 0/50 0/50 1/50 0150 1/50 21250
2 0150 2/50 1/50 10/50 131200 6 0/50 0150 1/50 0/50 3/50 41250
3 1/50 2/50 6/50 8/50 11/200 I 0/50 0150 0/50 1/50 1/50 21250
4 12/50 11/50 16/50 L1/50 621200 8 0/50 0/50 0150 0/50 0150 01250

~ B A
TEST TEMPERATlllRE
T Q l i
BATCH 2

Fig. 1. Cumulative distribution of cracked parts

-
mnnWnrmWTCH3
BATCH 4
Fig. 2. Sketch showing typical crack formations

lamination can be seen at the lower left corner of the picture.

Figures 3 to 9 show the SEM micrographs o’f fracture surfaces
of the failed capacitors. The source of failure aind the propagating
radial cracks can be clearly seen in these pictures. Figure 3 shows
the fracture surface of a sample exhibiting a moon crack. The
white lines running across the picture are the electrode planes.
The source of failure, in this case, is a delamination between the
electrode and the ceramic in the middle of the capacitor. This de-
Most of the fractures originated from the flaws in this region,
because the corners of the capacitor are in the high-stress
regions.3 Figure 4 shows the delaminated region at higher magni-
fication. The electrode is seen to be in the form of a large globule
and not as a uniform metal film. This may be due to the lack of
bonding and the differences in the sintering rates of the metal and
the ceramic. This delamination is probably caused by the decom-
position of the organic binders from the electrode ink and the
ceramic sheet. This “bakeout” process is a critical step during
the processing of MLC capacitors, and understanding it is very

Fig. 3. Fracture surface of a sample exhibiting “moon Fig. 4. Source of failure, a delamination between the
crack,” showing the source of failure. ceramic and the electrode.
December 1989 Fractography of Thermal-Shock-CrackedMultilayer Capacitors
Fig. 5. Fracture surface of a sample exhibiting “side
crack,” showing several delaminated regions.
important in preventing these Delaminations can, also,
be caused by external contaminants that are trapped between the
ceramic and the electrode. These can easily be avoided by using
a clean-room atmosphere.
Figures 5 and 6 show fracture surfaces of a sample exhibiting a
longitudinal side crack. Here again, the source of failure is
delamination between the ceramic and the electrode. Several
flaws are present on the surface. Figure 6 shows one of the
delaminated regions at higher magnification. Figure 7 shows an
example of device failure due to a delamination between two
ceramic layers. Proximity of the delamination toward the edge of
the capacitor suggests that this defect must have been formed
during the process where the individual capacitors are separated.
Careless handling, or dull cutters, are the most likely reasons.
Figure 8 shows the fracture surface of a sample where the
source of the failure is a void in the ceramic sheet. This is shown
Fig. 7. Micrograph showing a sample failure due to
delamination between two ceramic layers.
2243
Fig. 6. Micrograph showing one of the delaminations at
higher magnification.
at a higher magnification in Fig. 9. Voids in a ceramic sheet can
result from entrapped air in the ceramic slip, poor dispersion of
the slip, or agglomerates in the ceramic powder.
These micrographs show that flaws of various types and sizes
formed during processing were the sources of failure. The reason
for the large number of failures in some groups must be due to
the presence of a large number of flaws of critical size. In all
these cases, the presence of internal flaws formed during the proc-
essing appears to control the thermal shock resistance of a particu-
lar batch of capacitors.
These thermal shock tests and their failure analysis led to sev-
eral process improvements to eliminate the flaws causing thermal
shock failures. These process improvements include elimination
of organic agglomerates in the ink and the ceramic binders, better
dispersion of the raw materials in the ceramic slip, slower rate of
organic binder removal, and a cleaner environment.
Fig. 8. Fracture surface of a sample exhibiting “corner
crack,” showing the source of failure as a void in the
ceramic.
2244 Journal of the American Ceramic Society- Koripella and DeMatos Vol. 12, No. 12

Table 111. Board Mount Thermal Shock Test Results for

Capacitors from Batches 9 to 12
Batch No. Number of chips failed Failure rate (ppm)
9 11760 1315
10 1/760 1315
11 11755 1324
12 11800 1250

Fig. 9. Micrograph hhowing the void where the fracture

initiated.

Table I1 gives the thermal shock test results on batches 5 to 8,

which are prepared after the process improvements. There are
fewer failures in these batches. In most cases, no failures were
observed until 350°C thermal shock. To differentiate among the
various batches, thermal shock testing was, also, performed at Fig. 10. Sample failure due to a contami-
400°C on these batches. Cracked capacitors from these batches nant at the electrodeiceramic interface.
were also analyzed to determine the source of failure. Failure
analysis on these samples revealed that the voids are the main
source of failure. Occasionally, small delaminations were also
observed as the source of failure.
Through an interative process of thermal shock testing, frac- were also reduced in the solder immersion thermal shock test.
tography, and process improvements, the number of internal The lowered failure rates require testing of large sample popula-
flaws responsible for high failure rates were eliminated. This pro- tions. Another disadvantage with the solder immersion test is that
cedure is very similar to the method suggested to improve the it does not represent the actual use conditions, as capacitors are
reliability of structural ceramic^.^.'" Here, the sensitivity of the not exposed to the differential thermal expansion of the board and
thermal shock test was used to detect the internal flaws in MLC the capacitor. However, the solder immersion test is very valuable
capacitors. With continued process improvements, failure rates in the initial evaluations, because it is simple and inexpensive.

Fig. 11. Micrograph showing the flaw, caused by the Fig. 12. Micrograph showing a sample failure due to sur-
contaminant. face flaw.
December 1989 Fractography of Thermal-Shock-CrackedMultilayer Capacitors 2245

Fig. 13. Surface flaw, where the fracture initiated Fig. 14. Fracture surface of a sample failed after wave
soldering and load humidity testing.

During this test, when the capacitor is immersed in the hot solder, IV. Conclusions
compressive stresses develop on the outer surface, and tensile
stresses develop inside the capacitor, which makes it vulnerable Thermal shock testing by immersing the MLC capacitors in
to internal flaws. Fractographic analysis of these capacitors molten solder is a quick and simple test, which is extremely use-
clearly showed the internal flaws responsible for the thermal ful in detecting the internal flaws in the capacitors. Because the
shock cracking. capacitors are exposed to different types of stresses in this test
than under actual usage conditions, board mount and wave sol-
(2) Board Mount Thermal Shock Testing der, followed by load humidity testing should, also, be performed
Thermal shock performance data for different batches of MLC to characterize the capacitors for thermal shock resistance.
capacitors from this test are given in Table Ill. For each batch, Failure analysis of the thermal-shock-cracked capacitors
the number of failed capacitors out of the 750 capacitors tested reveals that the internal flaws were the main source of failure in
and the corresponding failure rate in ppm are given. As seen from several capacitors. Delaminations and voids are the two main
these results, the failure rate varies between 1000 and 1500 ppm. internal flaws observed. Surface flaws are, also, observed as the
Cracked chips after the board mount thermal shock test were source of failure in some capacitors.
also analyzed by fractography methods. Figures 10 and 11 show Through an iterative.process of thermal shock testing, frac-
the fracture surfaces of a sample cracked because of delamination tography and process improvements, flaws responsible for ther-
at the electrode-ceramic interface, caused by a contaminant. mal shock cracking of MLC capacitors can be eliminated, to
Figures 12 and 13 show the fracture surfaces from another produce capacitors with improved thermal shock resistance.
sample. Here, the source of failure is a surface defect on the bot-
tom surface of the capacitor. The capacitor cracked at this flaw
because of the stresses from the thermal expansion mismatch of
the capacitor and the board. It shows the importance of control-
ling surface flaws, as well as internal flaws, to prevent thermal
shock failures. This kind of failure would not have been detected
in the earlier thermal shock test, where the capacitor is immersed
in molten solder, because of the absence of the stresses from
the board.
Figures 14 and 15 show the fracture surface of the sample with
a corner crack. A dielectric breakdown can be observed in the
middle of the sample which appears to be the source of failure.
However, in this case, the dielectric melt could have been formed
after the sample was cracked, because of some other defect.
Since these samples were subjected to load humidity testing, it is
possible that metal migration, or humidity, could have formed the
conducting path between two electrodes, contributing to the
dielectric breakdown.
The advantages of this type of thermal shock testing include
simulating stress situations that are close to the actual usage con-
ditions, and the application of voltage under high humidity condi-
tions to detect microcracks that could have gone unnoticed in the
earlier test method. Disadvantages are that this is an expensive
test and, because of the complicated nature of stresses acting on
the part during thermal shock test, it is more difficult to detect Fig. 15. Micrograph showing dielectric breakdown at the
internal flaws in the multilayer capacitors. source of failure.
2246 Journal of the American Ceramic Society- Winzer et al.
References
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Charles Stark Draper Laboratories, Cambridge, MA, June 1077.
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unpublished work.
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Cerum. Soc.. 68 171 363-67 (1985).
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of BaTiO, Ceramic Capacitors,” Ferroelectrics. 50, 293-98 (1983).
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Reliability in Multilayer Ceramic Capacitors
journal
Designing Cofired Multilayer Electrostrictive
Actuators for Reliability
Stephen R. Winzer,* Natarajan Shankar, and Andrew P. Ritter
h,,..ilayer electrostrictive actuators are large capacitors with
the added complexity of having to perform mechanically as
well as electrically. High operating fields and severe operating
conditions make it necessary to predict and liimit stress levels
generated in the device. A constitutive three-dimensional
model for electrostrictors has been develoiped and imple-
mented as a design tool for actuators. The effects of electrode
geometry and transition-layer thickness on stress levels have
been modeled and failure in high-stress regioins has been cor-
related with the presence of flaws (pores andl delaminations)
in the devices. [Key words: capacitors, electrical properties,
stress, multilayer, modeling.]
I. Introduction
E LECTROMECHANICAL actuators, based on piezoelectric mate-
rials, have existed for many years. More recently, actuators
using electrostrictive materials have been propoised, and several
designs have appeared in the literature and as patents. Up until
Manuscnpt No. 198359. Received May 26, 1989; approved July 20, 1989.
Presented at the Symposium for the Improvement of Multilayer Capacitor Reli-
ability, The Pennsylvania State University, University Park, PA, May 11, 1989
(Paper No. 15).
’Member, American Ceramic Society.
Table I. Material Characteristics of Doped
PMN-PT Ceramics
Strain (1 MV/m) 1.0 x
Hysteresis* 2-3%
Young’s modulus 113.8 GPa
Flexural strength 88.3 MPa
Poisson’s ratio 0.26
*Average differential strain, at constant field, under conditions of increasing and
decreasing electric field.
Vol. 12, No. 12
Chips Subjected to Thermal Stresses”; pp. 25-31 in Proceedings of the 8th Capacl-
tor and Resistor Technology Symposium (CARTS), 1988.
’3. G. Pepin, R. J. Bouchard, R. J. S . Young, and W. A. Craig, “Delamination in
Multilayer Ceramic Capacitors”; presented at the Joint Meeting of the Basic
Science, Electronics, and Glass Divisions of the American Ceramic Society,
New Orleans, LA, November 3, 1986 (Paper No. 49-BEG-86F).
XD.W. Sproson and G. L. Messing, “Organic Removal Processes in Closed Pore
Powder-Binder Systems”; pp. 528-37 in Ceramic Transactions. Vol. 1, Part A ,
Ceramic Powder Science 11. Edited by G . L. Messing, E. R. Fuller, and H. Hausner.
American Ceramic Society, Westerville, OH, 1988.
9F.F. Lange, “Fabrication Reliability of Ceramics: Controlling Flaw Popula-
tions,” M a w . R r s . SOC. Synp. Proc., 60,143-52 (1986).
‘“A. G . Evans, “Aspects of Reliability of Ceramics for Engine Applications”;
pp. 364-85 in Fracture in Ceramic Materials. Edited by A. G. Evans. Noyes Publica-
tions, Park Ridge, NJ, 1984. n
J . Am. Ceram. SOC., 12 [I21 2246-57 (1989)
Martin Marietta Laboratories, Baltimore, Maryland 21227
the early 1980s, actuators were made virtually by hand by wafer-
ing ceramic (usually lead zirconate titanate (PZT)) and gluing the
wafers together using a conductive epoxy. This technique was ex-
pensive, as well as inappropriate for large-volume production of
devices. More recent efforts to produce actuators have focused on
using multilayer ceramic capacitor technology for two principal
reasons. The first is to alter the power requirement by reducing
the thickness of each layer, thereby increasing the field across the
layer for a given voltage. The second reason relates to the desire
to produce large numbers of devices cheaply while increasing re-
producibility and reliability. In this paper, we address some of the
issues encountered in developing multilayer electrostrictive actua-
tors for large-volume production.
A multilayer electrostrictive actuator is simply a capacitor
with the added requirement that it function actively as a mechani-
cal device. This added requirement precipitates a number of other
considerations in device design, the principal ones being the dis-
tribution of stress in the devices and the overall mechanical integ-
rity of the various bonds in the device. The former depends on the
design of the device (electrode geometry, layer thickness, inter-
connects, and the like) and the stress environment in which it is
used; the second relates to the degree to which an adequate bond
is achieved between electrodes and ceramic in their various con-
figurations. In this paper, we will describe models developed to
calculate stress distributions in multilayer electrostrictive ac-
tuators and different types of failure encountered with different
actuator designs. The results will be summarized and suggestions
made for design and fabrication of high-reliability actuators.
11. Actuator Materials
Electrostrictive actuator materials used to fabricate the multi-
layer actuators described in this paper are modifications of lead
magnesium niobate (Pb(MgIi3NbZi3)O3) or PMN, which was dis-
covered in 1958.4 In subsequent research5-’ the structure and di-
electric properties of PMN were defined and explanations for the